gem5  v20.1.0.0
malta_cchip.cc
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28 
33 #include "dev/mips/malta_cchip.hh"
34 
35 #include <deque>
36 #include <string>
37 #include <vector>
38 
39 #include "base/trace.hh"
40 #include "cpu/intr_control.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/Malta.hh"
43 #include "dev/mips/malta.hh"
44 #include "dev/mips/maltareg.h"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "mem/port.hh"
48 #include "params/MaltaCChip.hh"
49 #include "sim/system.hh"
50 
51 using namespace std;
52 
54  : BasicPioDevice(p, 0xfffffff), malta(p->malta)
55 {
56  warn("MaltaCCHIP::MaltaCChip() not implemented.");
57 
58  //Put back pointer in malta
59  malta->cchip = this;
60 
61 }
62 
63 Tick
65 {
66  panic("MaltaCCHIP::read() not implemented.");
67  return pioDelay;
68 }
69 
70 Tick
72 {
73  panic("MaltaCCHIP::write() not implemented.");
74  return pioDelay;
75 }
76 
77 void
78 MaltaCChip::clearIPI(uint64_t ipintr)
79 {
80  panic("MaltaCCHIP::clear() not implemented.");
81 }
82 
83 void
84 MaltaCChip::clearITI(uint64_t itintr)
85 {
86  panic("MaltaCCHIP::clearITI() not implemented.");
87 }
88 
89 void
90 MaltaCChip::reqIPI(uint64_t ipreq)
91 {
92  panic("MaltaCCHIP::reqIPI() not implemented.");
93 }
94 
95 
96 void
98 {
99  panic("MaltaCCHIP::postRTC() not implemented.");
100 }
101 
102 void
103 MaltaCChip::postIntr(uint32_t interrupt)
104 {
105  uint64_t size = sys->threads.size();
106  assert(size <= Malta::Max_CPUs);
107 
108  for (int i=0; i < size; i++) {
109  //Note: Malta does not use index, but this was added to use the
110  //pre-existing implementation
111  malta->intrctrl->post(i, interrupt, 0);
112  DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
113  i, interrupt);
114  }
115 }
116 
117 void
118 MaltaCChip::clearIntr(uint32_t interrupt)
119 {
120  uint64_t size = sys->threads.size();
121  assert(size <= Malta::Max_CPUs);
122 
123  for (int i=0; i < size; i++) {
124  //Note: Malta does not use index, but this was added to use the
125  //pre-existing implementation
126  malta->intrctrl->clear(i, interrupt, 0);
127  DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
128  i, interrupt);
129  }
130 }
131 
132 
133 void
135 {
136 }
137 
138 void
140 {
141 }
142 
143 MaltaCChip *
144 MaltaCChipParams::create()
145 {
146  return new MaltaCChip(this);
147 }
148 
Malta::cchip
MaltaCChip * cchip
Pointer to the Malta CChip.
Definition: malta.hh:69
warn
#define warn(...)
Definition: logging.hh:239
IntrControl::clear
void clear(int cpu_id, int int_num, int index)
Definition: intr_control.cc:55
malta.hh
system.hh
IntrControl::post
void post(int cpu_id, int int_num, int index)
Definition: intr_control.cc:47
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
MaltaCChip::clearIntr
void clearIntr(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Definition: malta_cchip.cc:118
MaltaCChip::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:64
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
malta_cchip.hh
packet.hh
PioDevice::sys
System * sys
Definition: io_device.hh:102
maltareg.h
Malta::Max_CPUs
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition: malta.hh:57
MaltaCChip::postIntr
void postIntr(uint32_t interrupt)
post an interrupt to the CPU.
Definition: malta_cchip.cc:103
cp
Definition: cprintf.cc:40
MaltaCChip::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:71
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
MaltaCChip::reqIPI
void reqIPI(uint64_t ipreq)
request an interrupt be posted to the CPU.
Definition: malta_cchip.cc:90
PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:131
port.hh
MaltaCChip::malta
Malta * malta
pointer to the malta object.
Definition: malta_cchip.hh:52
System::Threads::size
int size() const
Definition: system.hh:204
MaltaCChip
Malta CChip CSR Emulation.
Definition: malta_cchip.hh:44
packet_access.hh
MaltaCChip::postRTC
void postRTC()
post an RTC interrupt to the CPU
Definition: malta_cchip.cc:97
MaltaCChip::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta_cchip.cc:134
System::threads
Threads threads
Definition: system.hh:309
MaltaCChip::clearITI
void clearITI(uint64_t itintr)
clear a timer interrupt previously posted to the CPU.
Definition: malta_cchip.cc:84
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:53
intr_control.hh
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
BasicPioDevice
Definition: io_device.hh:150
Platform::intrctrl
IntrControl * intrctrl
Pointer to the interrupt controller.
Definition: platform.hh:53
BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:160
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
MaltaCChip::MaltaCChip
MaltaCChip(Params *p)
Initialize the Malta CChip by setting all of the device register to 0.
Definition: malta_cchip.cc:53
MaltaCChip::clearIPI
void clearIPI(uint64_t ipintr)
post an ipi interrupt to the CPU.
Definition: malta_cchip.cc:78
trace.hh
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
CheckpointIn
Definition: serialize.hh:67
MaltaCChip::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta_cchip.cc:139
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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