gem5  v20.1.0.0
noncaching.cc
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37 
38 #include "cpu/simple/noncaching.hh"
39 
40 NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
42 {
43 }
44 
45 void
47 {
48  if (!(system->isAtomicMode() && system->bypassCaches())) {
49  fatal("The direct CPU requires the memory system to be in the "
50  "'atomic_noncaching' mode.\n");
51  }
52 }
53 
54 Tick
56 {
57  if (system->isMemAddr(pkt->getAddr())) {
58  system->getPhysMem().access(pkt);
59  return 0;
60  } else {
61  return port.sendAtomic(pkt);
62  }
63 }
64 
66 NonCachingSimpleCPUParams::create()
67 {
68  numThreads = 1;
69  if (!FullSystem && workload.size() != 1)
70  fatal("only one workload allowed");
71  return new NonCachingSimpleCPU(this);
72 }
NonCachingSimpleCPU::NonCachingSimpleCPU
NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
Definition: noncaching.cc:40
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:183
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
System::getPhysMem
PhysicalMemory & getPhysMem()
Get a pointer to access the physical memory of the system.
Definition: system.hh:342
NonCachingSimpleCPU::verifyMemoryMode
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: noncaching.cc:46
NonCachingSimpleCPU::sendPacket
Tick sendPacket(RequestPort &port, const PacketPtr &pkt) override
Definition: noncaching.cc:55
NonCachingSimpleCPU
The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of ju...
Definition: noncaching.hh:48
System::bypassCaches
bool bypassCaches() const
Should caches be bypassed?
Definition: system.hh:279
AtomicSimpleCPU
Definition: atomic.hh:50
RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:74
noncaching.hh
BaseCPU::system
System * system
Definition: base.hh:371
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
PhysicalMemory::access
void access(PacketPtr pkt)
Perform an untimed memory access and update all the state (e.g.
Definition: physical.cc:294
RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:461
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
System::isAtomicMode
bool isAtomicMode() const
Is the system in atomic mode?
Definition: system.hh:258
System::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: system.cc:417

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