regfile.hh

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 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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#ifndef __CPU_O3_REGFILE_HH__
#define __CPU_O3_REGFILE_HH__
 
#include <vector>
 
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "debug/IEW.hh"
#include "enums/VecRegRenameMode.hh"
 
class UnifiedFreeList;
 
class PhysRegFile
{
  private:
 
    using VecElem = TheISA::VecElem;
    using VecRegContainer = TheISA::VecRegContainer;
    using PhysIds = std::vector<PhysRegId>;
    using VecMode = Enums::VecRegRenameMode;
    using VecPredRegContainer = TheISA::VecPredRegContainer;
  public:
    using IdRange = std::pair<PhysIds::iterator,
                              PhysIds::iterator>;
  private:
    static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
 
    std::vector<RegVal> intRegFile;
    std::vector<PhysRegId> intRegIds;
 
    std::vector<RegVal> floatRegFile;
    std::vector<PhysRegId> floatRegIds;
 
    std::vector<VecRegContainer> vectorRegFile;
    std::vector<PhysRegId> vecRegIds;
    std::vector<PhysRegId> vecElemIds;
 
    std::vector<VecPredRegContainer> vecPredRegFile;
    std::vector<PhysRegId> vecPredRegIds;
 
    std::vector<RegVal> ccRegFile;
    std::vector<PhysRegId> ccRegIds;
 
    std::vector<PhysRegId> miscRegIds;
 
    unsigned numPhysicalIntRegs;
 
    unsigned numPhysicalFloatRegs;
 
    unsigned numPhysicalVecRegs;
 
    unsigned numPhysicalVecElemRegs;
 
    unsigned numPhysicalVecPredRegs;
 
    unsigned numPhysicalCCRegs;
 
    unsigned totalNumRegs;
 
    VecMode vecMode;
 
  public:
    PhysRegFile(unsigned _numPhysicalIntRegs,
                unsigned _numPhysicalFloatRegs,
                unsigned _numPhysicalVecRegs,
                unsigned _numPhysicalVecPredRegs,
                unsigned _numPhysicalCCRegs,
                VecMode vmode
                );
 
    ~PhysRegFile() {}
 
    void initFreeList(UnifiedFreeList *freeList);
 
    unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
 
    unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
    unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
    unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
 
    unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
 
    unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
 
    unsigned totalNumPhysRegs() const { return totalNumRegs; }
 
    PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
        return &miscRegIds[reg_idx];
    }
 
    RegVal
    readIntReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->isIntPhysReg());
 
        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
                "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
        return intRegFile[phys_reg->index()];
    }
 
    RegVal
    readFloatReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->isFloatPhysReg());
 
        RegVal floatRegBits = floatRegFile[phys_reg->index()];
 
        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
                "has data %#x\n", phys_reg->index(), floatRegBits);
 
        return floatRegBits;
    }
 
    const VecRegContainer &
    readVecReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->isVectorPhysReg());
 
        DPRINTF(IEW, "RegFile: Access to vector register %i, has "
                "data %s\n", int(phys_reg->index()),
                vectorRegFile[phys_reg->index()].print());
 
        return vectorRegFile[phys_reg->index()];
    }
 
    VecRegContainer &
    getWritableVecReg(PhysRegIdPtr phys_reg)
    {
        /* const_cast for not duplicating code above. */
        return const_cast<VecRegContainer&>(readVecReg(phys_reg));
    }
 
    template <typename VecElem, int LaneIdx>
    VecLaneT<VecElem, true>
    readVecLane(PhysRegIdPtr phys_reg) const
    {
        return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
    }
 
    template <typename VecElem>
    VecLaneT<VecElem, true>
    readVecLane(PhysRegIdPtr phys_reg) const
    {
        return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
    }
 
    template <typename LD>
    void
    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
    {
        assert(phys_reg->isVectorPhysReg());
 
        DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
                int(phys_reg->index()), phys_reg->elemIndex(), val);
 
        vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
                phys_reg->elemIndex()) = val;
    }
 
    const VecElem &
    readVecElem(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->isVectorPhysElem());
        auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
        const VecElem& val = ret[phys_reg->elemIndex()];
        DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
                " has data %#x\n", phys_reg->elemIndex(),
                int(phys_reg->index()), val);
 
        return val;
    }
 
    const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
    {
        assert(phys_reg->isVecPredPhysReg());
 
        DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
                "data %s\n", int(phys_reg->index()),
                vecPredRegFile[phys_reg->index()].print());
 
        return vecPredRegFile[phys_reg->index()];
    }
 
    VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
    {
        /* const_cast for not duplicating code above. */
        return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
    }
 
    RegVal
    readCCReg(PhysRegIdPtr phys_reg)
    {
        assert(phys_reg->isCCPhysReg());
 
        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
                "data %#x\n", phys_reg->index(),
                ccRegFile[phys_reg->index()]);
 
        return ccRegFile[phys_reg->index()];
    }
 
    void
    setIntReg(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->isIntPhysReg());
 
        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
                phys_reg->index(), val);
 
        if (!phys_reg->isZeroReg())
            intRegFile[phys_reg->index()] = val;
    }
 
    void
    setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->isFloatPhysReg());
 
        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
                phys_reg->index(), (uint64_t)val);
 
        if (!phys_reg->isZeroReg())
            floatRegFile[phys_reg->index()] = val;
    }
 
    void
    setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
    {
        assert(phys_reg->isVectorPhysReg());
 
        DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
                int(phys_reg->index()), val.print());
 
        vectorRegFile[phys_reg->index()] = val;
    }
 
    void
    setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
    {
        assert(phys_reg->isVectorPhysElem());
 
        DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
                " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
 
        vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
                val;
    }
 
    void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
    {
        assert(phys_reg->isVecPredPhysReg());
 
        DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
                int(phys_reg->index()), val.print());
 
        vecPredRegFile[phys_reg->index()] = val;
    }
 
    void
    setCCReg(PhysRegIdPtr phys_reg, RegVal val)
    {
        assert(phys_reg->isCCPhysReg());
 
        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
                phys_reg->index(), (uint64_t)val);
 
        ccRegFile[phys_reg->index()] = val;
    }
 
    IdRange getRegElemIds(PhysRegIdPtr reg);
 
    IdRange getRegIds(RegClass cls);
 
    PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
};
 
 
#endif //__CPU_O3_REGFILE_HH__