gem5  v20.1.0.0
tlm_to_gem5.cc
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39  * documentation and/or other materials provided with the distribution.
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42  * contributors may be used to endorse or promote products derived from
43  * this software without specific prior written permission.
44  *
45  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
46  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
47  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
48  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
49  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
50  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
51  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
52  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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57 
59 
60 #include "params/TlmToGem5Bridge32.hh"
61 #include "params/TlmToGem5Bridge64.hh"
62 #include "sim/system.hh"
65 
66 namespace sc_gem5
67 {
68 
71 {
72  MemCmd cmd;
73 
74  switch (trans.get_command()) {
76  cmd = MemCmd::ReadReq;
77  break;
79  cmd = MemCmd::WriteReq;
80  break;
82  return nullptr;
83  default:
84  SC_REPORT_FATAL("TlmToGem5Bridge",
85  "received transaction with unsupported command");
86  }
87 
88  Request::Flags flags;
89  auto req = std::make_shared<Request>(
90  trans.get_address(), trans.get_data_length(), flags, _id);
91 
92  /*
93  * Allocate a new Packet. The packet will be deleted when it returns from
94  * the gem5 world as a response.
95  */
96  auto pkt = new Packet(req, cmd);
97  pkt->dataStatic(trans.get_data_ptr());
98 
99  return pkt;
100 }
101 
102 template <unsigned int BITWIDTH>
103 void
105 {
107  auto delay = sc_core::SC_ZERO_TIME;
108 
109  auto status = socket->nb_transport_bw(trans, phase, delay);
111  "Unexpected status after sending END_REQ");
112 }
113 
114 template <unsigned int BITWIDTH>
115 void
117  sc_core::sc_time &delay)
118 {
120 
122 
123  auto status = socket->nb_transport_bw(trans, phase, delay);
124 
125  if (status == tlm::TLM_COMPLETED ||
126  (status == tlm::TLM_UPDATED && phase == tlm::END_RESP)) {
127  // transaction completed -> no need to wait for tlm::END_RESP
128  responseInProgress = false;
129  } else if (status == tlm::TLM_ACCEPTED) {
130  // we need to wait for tlm::END_RESP
131  responseInProgress = true;
132  } else {
133  panic("Unexpected status after sending BEGIN_RESP");
134  }
135 }
136 
137 template <unsigned int BITWIDTH>
138 void
140 {
141  sc_assert(!waitForRetry);
142  sc_assert(pendingRequest == nullptr);
143  sc_assert(pendingPacket == nullptr);
144 
145  trans.acquire();
146 
147  PacketPtr pkt = nullptr;
148 
149  Gem5SystemC::Gem5Extension *extension = nullptr;
150  trans.get_extension(extension);
151 
152  // If there is an extension, this transaction was initiated by the gem5
153  // world and we can pipe through the original packet. Otherwise, we
154  // generate a new packet based on the transaction.
155  if (extension != nullptr) {
156  extension->setPipeThrough();
157  pkt = extension->getPacket();
158  } else {
159  pkt = payload2packet(_id, trans);
160  }
161 
162  auto tlmSenderState = new TlmSenderState(trans);
163  pkt->pushSenderState(tlmSenderState);
164 
165  // If the packet doesn't need a response, we should send BEGIN_RESP by
166  // ourselves.
167  bool needsResponse = pkt->needsResponse();
168  if (bmp.sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
169  sendEndReq(trans);
170  if (!needsResponse) {
171  auto delay = sc_core::SC_ZERO_TIME;
172  sendBeginResp(trans, delay);
173  }
174  trans.release();
175  } else { // port is blocked -> wait for retry before sending END_REQ
176  waitForRetry = true;
177  pendingRequest = &trans;
178  pendingPacket = pkt;
179  }
180 }
181 
182 template <unsigned int BITWIDTH>
183 void
185 {
186  sc_assert(responseInProgress);
187 
188  responseInProgress = false;
189 
190  checkTransaction(trans);
191 
192  if (needToSendRetry) {
193  bmp.sendRetryResp();
194  needToSendRetry = false;
195  }
196 }
197 
198 template <unsigned int BITWIDTH>
199 void
201 {
202  delete pkt;
203 }
204 
205 template <unsigned int BITWIDTH>
206 void
208 {
209  if (trans.is_response_error()) {
210  std::stringstream ss;
211  ss << "Transaction returned with error, response status = "
212  << trans.get_response_string();
213  SC_REPORT_ERROR("TLM-2", ss.str().c_str());
214  }
215 }
216 
217 template <unsigned int BITWIDTH>
218 void
219 TlmToGem5Bridge<BITWIDTH>::invalidateDmi(const ::MemBackdoor &backdoor)
220 {
221  socket->invalidate_direct_mem_ptr(
222  backdoor.range().start(), backdoor.range().end());
223 }
224 
225 template <unsigned int BITWIDTH>
226 void
228  const tlm::tlm_phase &phase)
229 {
230  switch (phase) {
231  case tlm::BEGIN_REQ:
232  handleBeginReq(trans);
233  break;
234  case tlm::END_RESP:
235  handleEndResp(trans);
236  break;
237  default:
238  panic("unimplemented phase in callback");
239  }
240 }
241 
242 template <unsigned int BITWIDTH>
246  sc_core::sc_time &delay)
247 {
248  unsigned len = trans.get_data_length();
249  unsigned char *byteEnable = trans.get_byte_enable_ptr();
250  unsigned width = trans.get_streaming_width();
251 
252  // check the transaction attributes for unsupported features ...
253  if (byteEnable != 0) {
255  return tlm::TLM_COMPLETED;
256  }
257  if (width < len) { // is this a burst request?
259  return tlm::TLM_COMPLETED;
260  }
261 
262  // ... and queue the valid transaction
263  trans.acquire();
264  peq.notify(trans, phase, delay);
265  return tlm::TLM_ACCEPTED;
266 }
267 
268 template <unsigned int BITWIDTH>
269 void
272 {
273  Gem5SystemC::Gem5Extension *extension = nullptr;
274  trans.get_extension(extension);
275 
276  PacketPtr pkt = nullptr;
277 
278  // If there is an extension, this transaction was initiated by the gem5
279  // world and we can pipe through the original packet.
280  if (extension != nullptr) {
281  extension->setPipeThrough();
282  pkt = extension->getPacket();
283  } else {
284  pkt = payload2packet(_id, trans);
285  }
286 
287  MemBackdoorPtr backdoor = nullptr;
288  Tick ticks = bmp.sendAtomicBackdoor(pkt, backdoor);
289  if (backdoor)
290  trans.set_dmi_allowed(true);
291 
292  // send an atomic request to gem5
293  panic_if(pkt->needsResponse() && !pkt->isResponse(),
294  "Packet sending failed!\n");
295 
296  auto delay =
298 
299  // update time
300  t += delay;
301 
302  if (extension == nullptr)
303  destroyPacket(pkt);
304 
306 }
307 
308 template <unsigned int BITWIDTH>
309 unsigned int
311 {
312  Gem5SystemC::Gem5Extension *extension = nullptr;
313  trans.get_extension(extension);
314 
315  // If there is an extension, this transaction was initiated by the gem5
316  // world and we can pipe through the original packet.
317  if (extension != nullptr) {
318  extension->setPipeThrough();
319  bmp.sendFunctional(extension->getPacket());
320  } else {
321  auto pkt = payload2packet(_id, trans);
322  if (pkt) {
323  bmp.sendFunctional(pkt);
324  destroyPacket(pkt);
325  }
326  }
327 
328  return trans.get_data_length();
329 }
330 
331 template <unsigned int BITWIDTH>
332 bool
334  tlm::tlm_dmi &dmi_data)
335 {
336  Gem5SystemC::Gem5Extension *extension = nullptr;
337  trans.get_extension(extension);
338 
339  PacketPtr pkt = nullptr;
340 
341  // If there is an extension, this transaction was initiated by the gem5
342  // world and we can pipe through the original packet.
343  if (extension != nullptr) {
344  extension->setPipeThrough();
345  pkt = extension->getPacket();
346  } else {
347  pkt = payload2packet(_id, trans);
348  pkt->req->setFlags(Request::NO_ACCESS);
349  }
350 
351  MemBackdoorPtr backdoor = nullptr;
352  bmp.sendAtomicBackdoor(pkt, backdoor);
353  if (backdoor) {
354  trans.set_dmi_allowed(true);
355  dmi_data.set_dmi_ptr(backdoor->ptr());
356  dmi_data.set_start_address(backdoor->range().start());
357  dmi_data.set_end_address(backdoor->range().end());
358 
359  typedef tlm::tlm_dmi::dmi_access_e access_t;
360  access_t access = tlm::tlm_dmi::DMI_ACCESS_NONE;
361  if (backdoor->readable())
362  access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_READ);
363  if (backdoor->writeable())
364  access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_WRITE);
365  dmi_data.set_granted_access(access);
366 
367  backdoor->addInvalidationCallback(
368  [this](const MemBackdoor &backdoor)
369  {
370  invalidateDmi(backdoor);
371  }
372  );
373  }
374 
375  if (extension == nullptr)
376  destroyPacket(pkt);
377 
379 
380  return backdoor != nullptr;
381 }
382 
383 template <unsigned int BITWIDTH>
384 bool
386 {
387  // exclusion rule
388  // We need to Wait for END_RESP before sending next BEGIN_RESP
389  if (responseInProgress) {
390  sc_assert(!needToSendRetry);
391  needToSendRetry = true;
392  return false;
393  }
394 
395  sc_assert(pkt->isResponse());
396 
397  /*
398  * Pay for annotated transport delays.
399  *
400  * See recvTimingReq in sc_slave_port.cc for a detailed description.
401  */
402  auto delay = sc_core::sc_time::from_value(pkt->payloadDelay);
403  // reset the delays
404  pkt->payloadDelay = 0;
405  pkt->headerDelay = 0;
406 
407  auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
408  sc_assert(tlmSenderState != nullptr);
409 
410  auto &trans = tlmSenderState->trans;
411 
412  Gem5SystemC::Gem5Extension *extension = nullptr;
413  trans.get_extension(extension);
414 
415  // clean up
416  delete tlmSenderState;
417 
418  // If there is an extension the packet was piped through and we must not
419  // delete it. The packet travels back with the transaction.
420  if (extension == nullptr)
421  destroyPacket(pkt);
422  else
423  sc_assert(extension->isPipeThrough());
424 
425  sendBeginResp(trans, delay);
426  trans.release();
427 
428  return true;
429 }
430 
431 template <unsigned int BITWIDTH>
432 void
434 {
435  sc_assert(waitForRetry);
436  sc_assert(pendingRequest != nullptr);
437  sc_assert(pendingPacket != nullptr);
438 
439  // If the packet doesn't need a response, we should send BEGIN_RESP by
440  // ourselves.
441  bool needsResponse = pendingPacket->needsResponse();
442  if (bmp.sendTimingReq(pendingPacket)) {
443  waitForRetry = false;
444  pendingPacket = nullptr;
445 
446  auto &trans = *pendingRequest;
447  sendEndReq(trans);
448  if (!needsResponse) {
449  auto delay = sc_core::SC_ZERO_TIME;
450  sendBeginResp(trans, delay);
451  }
452  trans.release();
453 
454  pendingRequest = nullptr;
455  }
456 }
457 
458 template <unsigned int BITWIDTH>
459 void
461 {
462  SC_REPORT_WARNING("TlmToGem5Bridge",
463  "received address range change but ignored it");
464 }
465 
466 template <unsigned int BITWIDTH>
467 ::Port &
468 TlmToGem5Bridge<BITWIDTH>::gem5_getPort(const std::string &if_name, int idx)
469 {
470  if (if_name == "gem5")
471  return bmp;
472  else if (if_name == "tlm")
473  return wrapper;
474 
475  return sc_core::sc_module::gem5_getPort(if_name, idx);
476 }
477 
478 template <unsigned int BITWIDTH>
480  Params *params, const sc_core::sc_module_name &mn) :
481  TlmToGem5BridgeBase(mn), peq(this, &TlmToGem5Bridge<BITWIDTH>::peq_cb),
482  waitForRetry(false), pendingRequest(nullptr), pendingPacket(nullptr),
483  needToSendRetry(false), responseInProgress(false),
484  bmp(std::string(name()) + "master", *this), socket("tlm_socket"),
485  wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
486  system(params->system),
487  _id(params->system->getGlobalRequestorId(
488  std::string("[systemc].") + name()))
489 {
490 }
491 
492 template <unsigned int BITWIDTH>
493 void
495 {
496  /*
497  * Register the TLM non-blocking interface when using gem5 Timing mode and
498  * the TLM blocking interface when using the gem5 Atomic mode.
499  * Then the magic (TM) in simple_target_socket automatically transforms
500  * non-blocking in blocking transactions and vice versa.
501  *
502  * NOTE: The mode may change during execution.
503  */
504  if (system->isTimingMode()) {
505  SC_REPORT_INFO("TlmToGem5Bridge", "register non-blocking interface");
506  socket.register_nb_transport_fw(
508  } else if (system->isAtomicMode()) {
509  SC_REPORT_INFO("TlmToGem5Bridge", "register blocking interface");
510  socket.register_b_transport(
512  socket.register_get_direct_mem_ptr(
514  } else {
515  panic("gem5 operates neither in Timing nor in Atomic mode");
516  }
517 
518  socket.register_transport_dbg(
520 
522 }
523 
524 } // namespace sc_gem5
525 
527 TlmToGem5Bridge32Params::create()
528 {
529  return new sc_gem5::TlmToGem5Bridge<32>(
530  this, sc_core::sc_module_name(name.c_str()));
531 }
532 
534 TlmToGem5Bridge64Params::create()
535 {
536  return new sc_gem5::TlmToGem5Bridge<64>(
537  this, sc_core::sc_module_name(name.c_str()));
538 }
sc_gem5::payload2packet
PacketPtr payload2packet(RequestorID _id, tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:70
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
sc_core::sc_time::from_value
static sc_time from_value(sc_dt::uint64)
Definition: sc_time.cc:210
Packet::isResponse
bool isResponse() const
Definition: packet.hh:560
MemBackdoor
Definition: backdoor.hh:38
system.hh
sc_gem5::TlmToGem5Bridge::recvRangeChange
void recvRangeChange()
Definition: tlm_to_gem5.cc:460
tlm_to_gem5.hh
tlm::tlm_phase
Definition: phase.hh:47
Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:412
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:238
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
Flags< FlagsType >
tlm::tlm_generic_payload::get_streaming_width
unsigned int get_streaming_width() const
Definition: gp.hh:228
Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:135
ArmISA::width
Bitfield< 4 > width
Definition: miscregs_types.hh:68
sc_module_name.hh
sc_gem5::TlmToGem5Bridge::invalidateDmi
void invalidateDmi(const ::MemBackdoor &backdoor)
Definition: tlm_to_gem5.cc:219
tlm::tlm_dmi
Definition: dmi.hh:46
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
tlm::TLM_UPDATED
@ TLM_UPDATED
Definition: fw_bw_ifs.hh:65
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:82
tlm::END_REQ
@ END_REQ
Definition: phase.hh:42
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE
@ TLM_BYTE_ENABLE_ERROR_RESPONSE
Definition: gp.hh:114
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SC_REPORT_FATAL
#define SC_REPORT_FATAL(msg_type, msg)
Definition: sc_report_handler.hh:131
tlm::tlm_dmi::DMI_ACCESS_READ
@ DMI_ACCESS_READ
Definition: dmi.hh:90
AddrRange::end
Addr end() const
Get the end address of the range.
Definition: addr_range.hh:321
Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:340
Gem5SystemC::Gem5Extension::getPacket
PacketPtr getPacket()
Definition: sc_ext.cc:63
tlm::tlm_generic_payload::release
void release()
Definition: gp.hh:147
sc_gem5::TlmToGem5Bridge::TlmToGem5Bridge
TlmToGem5Bridge(Params *p, const sc_core::sc_module_name &mn)
Definition: tlm_to_gem5.cc:479
sc_assert
#define sc_assert(expr)
Definition: sc_report_handler.hh:135
sc_gem5::TlmToGem5Bridge::Params
TlmToGem5BridgeBaseParams Params
Definition: tlm_to_gem5.hh:163
Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:394
sc_gem5::TlmToGem5Bridge::recvReqRetry
void recvReqRetry()
Definition: tlm_to_gem5.cc:433
tlm::tlm_generic_payload::set_dmi_allowed
void set_dmi_allowed(bool dmi_allowed)
Definition: gp.hh:256
tlm::tlm_generic_payload::get_response_string
std::string get_response_string() const
Definition: gp.cc:292
sc_gem5::TlmToGem5Bridge::nb_transport_fw
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &t)
Definition: tlm_to_gem5.cc:244
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:85
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
RequestorID
uint16_t RequestorID
Definition: request.hh:85
sc_gem5::TlmToGem5Bridge::destroyPacket
void destroyPacket(PacketPtr pkt)
Definition: tlm_to_gem5.cc:200
tlm::TLM_BURST_ERROR_RESPONSE
@ TLM_BURST_ERROR_RESPONSE
Definition: gp.hh:113
tlm::tlm_dmi::set_end_address
void set_end_address(sc_dt::uint64 addr)
Definition: dmi.hh:117
tlm::tlm_generic_payload::get_command
tlm_command get_command() const
Definition: gp.hh:197
tlm::tlm_generic_payload::get_byte_enable_ptr
unsigned char * get_byte_enable_ptr() const
Definition: gp.hh:236
sc_core::sc_module::gem5_getPort
virtual ::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
SC_REPORT_ERROR
#define SC_REPORT_ERROR(msg_type, msg)
Definition: sc_report_handler.hh:127
tlm::tlm_generic_payload::get_data_length
unsigned int get_data_length() const
Definition: gp.hh:209
sc_gem5::TlmToGem5BridgeBase
Definition: tlm_to_gem5.hh:74
sc_gem5::TlmToGem5Bridge::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: tlm_to_gem5.cc:494
MemCmd
Definition: packet.hh:71
MemBackdoor::ptr
uint8_t * ptr() const
Definition: backdoor.hh:58
Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:570
sc_core::sc_time
Definition: sc_time.hh:49
sc_gem5::TlmToGem5Bridge::sendEndReq
void sendEndReq(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:104
sc_gem5::TlmToGem5Bridge::TlmSenderState
Definition: tlm_to_gem5.hh:86
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
MemBackdoor::range
const AddrRange & range() const
Definition: backdoor.hh:54
SimClock::Int::ps
Tick ps
picosecond
Definition: core.cc:66
sc_core::sc_module_name
Definition: sc_module_name.hh:41
tlm::tlm_generic_payload::acquire
void acquire()
Definition: gp.hh:140
sc_gem5::TlmToGem5Bridge::sendBeginResp
void sendBeginResp(tlm::tlm_generic_payload &trans, sc_core::sc_time &delay)
Definition: tlm_to_gem5.cc:116
tlm::tlm_generic_payload::get_extension
void get_extension(T *&ext) const
Definition: gp.hh:381
tlm::END_RESP
@ END_RESP
Definition: phase.hh:44
sc_gem5::TlmToGem5Bridge::checkTransaction
void checkTransaction(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:207
ProbePoints::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:103
tlm::TLM_IGNORE_COMMAND
@ TLM_IGNORE_COMMAND
Definition: gp.hh:103
sc_gem5::TlmToGem5Bridge::gem5_getPort
::Port & gem5_getPort(const std::string &if_name, int idx=-1) override
Definition: tlm_to_gem5.cc:468
sc_gem5::TlmToGem5Bridge::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: tlm_to_gem5.cc:385
name
const std::string & name()
Definition: trace.cc:50
SC_REPORT_INFO
#define SC_REPORT_INFO(msg_type, msg)
Definition: sc_report_handler.hh:119
sc_gem5::TlmToGem5Bridge::handleBeginReq
void handleBeginReq(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:139
SC_REPORT_WARNING
#define SC_REPORT_WARNING(msg_type, msg)
Definition: sc_report_handler.hh:123
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
sc_gem5::TlmToGem5Bridge::b_transport
void b_transport(tlm::tlm_generic_payload &trans, sc_core::sc_time &t)
Definition: tlm_to_gem5.cc:270
MemBackdoor::addInvalidationCallback
void addInvalidationCallback(CbFunction func)
Definition: backdoor.hh:99
MemBackdoor::readable
bool readable() const
Definition: backdoor.hh:65
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
sc_core::SC_PS
@ SC_PS
Definition: sc_time.hh:42
Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:332
tlm::tlm_generic_payload
Definition: gp.hh:133
AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:314
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
sc_gem5::TlmToGem5Bridge
Definition: tlm_to_gem5.hh:83
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:340
sc_core::sc_module::before_end_of_elaboration
virtual void before_end_of_elaboration()
Definition: sc_module.hh:248
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
Gem5SystemC::Gem5Extension::setPipeThrough
void setPipeThrough()
Definition: sc_ext.hh:58
sc_gem5::Port
Definition: port.hh:50
tlm::tlm_generic_payload::is_response_error
bool is_response_error() const
Definition: gp.hh:214
tlm::tlm_dmi::set_dmi_ptr
void set_dmi_ptr(unsigned char *p)
Definition: dmi.hh:115
Gem5SystemC::Gem5Extension::isPipeThrough
bool isPipeThrough() const
Definition: sc_ext.hh:57
tlm::tlm_dmi::DMI_ACCESS_NONE
@ DMI_ACCESS_NONE
Definition: dmi.hh:89
sc_gem5::TlmToGem5Bridge::handleEndResp
void handleEndResp(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:184
sc_gem5
Definition: sc_clock.cc:42
sc_gem5::TlmToGem5Bridge::transport_dbg
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:310
Gem5SystemC::Gem5Extension
Definition: sc_ext.hh:43
tlm::tlm_dmi::set_start_address
void set_start_address(sc_dt::uint64 addr)
Definition: dmi.hh:116
tlm::tlm_dmi::dmi_access_e
dmi_access_e
Definition: dmi.hh:71
sc_gem5::TlmToGem5Bridge::get_direct_mem_ptr
bool get_direct_mem_ptr(tlm::tlm_generic_payload &trans, tlm::tlm_dmi &dmi_data)
Definition: tlm_to_gem5.cc:333
sc_gem5::TlmToGem5Bridge::peq_cb
void peq_cb(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
Definition: tlm_to_gem5.cc:227
sc_time.hh
tlm::tlm_dmi::DMI_ACCESS_WRITE
@ DMI_ACCESS_WRITE
Definition: dmi.hh:91
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
tlm::tlm_generic_payload::get_data_ptr
unsigned char * get_data_ptr() const
Definition: gp.hh:205
MemBackdoor::writeable
bool writeable() const
Definition: backdoor.hh:75
tlm::BEGIN_RESP
@ BEGIN_RESP
Definition: phase.hh:43
tlm::tlm_dmi::set_granted_access
void set_granted_access(dmi_access_e a)
Definition: dmi.hh:120
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
tlm::tlm_generic_payload::set_response_status
void set_response_status(const tlm_response_status response_status)
Definition: gp.hh:221
tlm::TLM_ACCEPTED
@ TLM_ACCEPTED
Definition: fw_bw_ifs.hh:65

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