gem5  v20.1.0.0
fs_workload.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * Copyright (c) 2018 TU Dresden
4  * All rights reserved.
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are
17  * met: redistributions of source code must retain the above copyright
18  * notice, this list of conditions and the following disclaimer;
19  * redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in the
21  * documentation and/or other materials provided with the distribution;
22  * neither the name of the copyright holders nor the names of its
23  * contributors may be used to endorse or promote products derived from
24  * this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #include "arch/x86/fs_workload.hh"
40 
41 #include "arch/x86/bios/intelmp.hh"
42 #include "arch/x86/bios/smbios.hh"
43 #include "arch/x86/faults.hh"
44 #include "arch/x86/isa_traits.hh"
46 #include "cpu/thread_context.hh"
47 #include "params/X86FsWorkload.hh"
48 #include "sim/system.hh"
49 
50 namespace X86ISA
51 {
52 
54  smbiosTable(p->smbios_table),
55  mpFloatingPointer(p->intel_mp_pointer),
56  mpConfigTable(p->intel_mp_table),
57  rsdp(p->acpi_description_table_pointer)
58 {}
59 
60 void
62  SegDescriptor desc, bool longmode)
63 {
64  bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
65  seg == SEGMENT_REG_GS ||
66  seg == SEGMENT_REG_TSL ||
68 
69  SegAttr attr = 0;
70 
71  attr.dpl = desc.dpl;
72  attr.unusable = 0;
73  attr.defaultSize = desc.d;
74  attr.longMode = desc.l;
75  attr.avl = desc.avl;
76  attr.granularity = desc.g;
77  attr.present = desc.p;
78  attr.system = desc.s;
79  attr.type = desc.type;
80  if (desc.s) {
81  if (desc.type.codeOrData) {
82  // Code segment
83  attr.expandDown = 0;
84  attr.readable = desc.type.r;
85  attr.writable = 0;
86  } else {
87  // Data segment
88  attr.expandDown = desc.type.e;
89  attr.readable = 1;
90  attr.writable = desc.type.w;
91  }
92  } else {
93  attr.readable = 1;
94  attr.writable = 1;
95  attr.expandDown = 0;
96  }
97 
98  tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
99  tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
100  tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
102 }
103 
104 void
106 {
108 
109  for (auto *tc: system->threads) {
111 
112  if (tc->contextId() == 0) {
113  tc->activate();
114  } else {
115  // This is an application processor (AP). It should be initialized
116  // to look like only the BIOS POST has run on it and put then put
117  // it into a halted state.
118  tc->suspend();
119  }
120  }
121 
122  fatal_if(!kernelObj, "No kernel to load.");
123 
125  "Loading a 32 bit x86 kernel is not supported.");
126 
127  ThreadContext *tc = system->threads[0];
128  auto phys_proxy = system->physProxy;
129 
130  // This is the boot strap processor (BSP). Initialize it to look like
131  // the boot loader has just turned control over to the 64 bit OS. We
132  // won't actually set up real mode or legacy protected mode descriptor
133  // tables because we aren't executing any code that would require
134  // them. We do, however toggle the control bits in the correct order
135  // while allowing consistency checks and the underlying mechansims
136  // just to be safe.
137 
138  const int NumPDTs = 4;
139 
140  const Addr PageMapLevel4 = 0x70000;
141  const Addr PageDirPtrTable = 0x71000;
142  const Addr PageDirTable[NumPDTs] =
143  {0x72000, 0x73000, 0x74000, 0x75000};
144  const Addr GDTBase = 0x76000;
145 
146  const int PML4Bits = 9;
147  const int PDPTBits = 9;
148  const int PDTBits = 9;
149 
150  /*
151  * Set up the gdt.
152  */
153  uint8_t numGDTEntries = 0;
154  // Place holder at selector 0
155  uint64_t nullDescriptor = 0;
156  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, &nullDescriptor, 8);
157  numGDTEntries++;
158 
159  SegDescriptor initDesc = 0;
160  initDesc.type.codeOrData = 0; // code or data type
161  initDesc.type.c = 0; // conforming
162  initDesc.type.r = 1; // readable
163  initDesc.dpl = 0; // privilege
164  initDesc.p = 1; // present
165  initDesc.l = 1; // longmode - 64 bit
166  initDesc.d = 0; // operand size
167  initDesc.g = 1; // granularity
168  initDesc.s = 1; // system segment
169  initDesc.limit = 0xFFFFFFFF;
170  initDesc.base = 0;
171 
172  // 64 bit code segment
173  SegDescriptor csDesc = initDesc;
174  csDesc.type.codeOrData = 1;
175  csDesc.dpl = 0;
176  // Because we're dealing with a pointer and I don't think it's
177  // guaranteed that there isn't anything in a nonvirtual class between
178  // it's beginning in memory and it's actual data, we'll use an
179  // intermediary.
180  uint64_t csDescVal = csDesc;
181  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&csDescVal), 8);
182 
183  numGDTEntries++;
184 
185  SegSelector cs = 0;
186  cs.si = numGDTEntries - 1;
187 
188  tc->setMiscReg(MISCREG_CS, (RegVal)cs);
189 
190  // 32 bit data segment
191  SegDescriptor dsDesc = initDesc;
192  uint64_t dsDescVal = dsDesc;
193  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
194 
195  numGDTEntries++;
196 
197  SegSelector ds = 0;
198  ds.si = numGDTEntries - 1;
199 
205 
206  tc->setMiscReg(MISCREG_TSL, 0);
207  tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
208  tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
209 
210  SegDescriptor tssDesc = initDesc;
211  uint64_t tssDescVal = tssDesc;
212  phys_proxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);
213 
214  numGDTEntries++;
215 
216  SegSelector tss = 0;
217  tss.si = numGDTEntries - 1;
218 
219  tc->setMiscReg(MISCREG_TR, (RegVal)tss);
220  installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
221 
222  /*
223  * Identity map the first 4GB of memory. In order to map this region
224  * of memory in long mode, there needs to be one actual page map level
225  * 4 entry which points to one page directory pointer table which
226  * points to 4 different page directory tables which are full of two
227  * megabyte pages. All of the other entries in valid tables are set
228  * to indicate that they don't pertain to anything valid and will
229  * cause a fault if used.
230  */
231 
232  // Put valid values in all of the various table entries which indicate
233  // that those entries don't point to further tables or pages. Then
234  // set the values of those entries which are needed.
235 
236  // Page Map Level 4
237 
238  // read/write, user, not present
239  uint64_t pml4e = htole<uint64_t>(0x6);
240  for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8)
241  phys_proxy.writeBlob(PageMapLevel4 + offset, (&pml4e), 8);
242  // Point to the only PDPT
243  pml4e = htole<uint64_t>(0x7 | PageDirPtrTable);
244  phys_proxy.writeBlob(PageMapLevel4, (&pml4e), 8);
245 
246  // Page Directory Pointer Table
247 
248  // read/write, user, not present
249  uint64_t pdpe = htole<uint64_t>(0x6);
250  for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8)
251  phys_proxy.writeBlob(PageDirPtrTable + offset, &pdpe, 8);
252  // Point to the PDTs
253  for (int table = 0; table < NumPDTs; table++) {
254  pdpe = htole<uint64_t>(0x7 | PageDirTable[table]);
255  phys_proxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
256  }
257 
258  // Page Directory Tables
259 
260  Addr base = 0;
261  const Addr pageSize = 2 << 20;
262  for (int table = 0; table < NumPDTs; table++) {
263  for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
264  // read/write, user, present, 4MB
265  uint64_t pdte = htole(0x87 | base);
266  phys_proxy.writeBlob(PageDirTable[table] + offset, &pdte, 8);
267  base += pageSize;
268  }
269  }
270 
271  /*
272  * Transition from real mode all the way up to Long mode
273  */
274  CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
275  // Turn off paging.
276  cr0.pg = 0;
277  tc->setMiscReg(MISCREG_CR0, cr0);
278  // Turn on protected mode.
279  cr0.pe = 1;
280  tc->setMiscReg(MISCREG_CR0, cr0);
281 
282  CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
283  // Turn on pae.
284  cr4.pae = 1;
285  tc->setMiscReg(MISCREG_CR4, cr4);
286 
287  // Point to the page tables.
288  tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
289 
290  Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
291  // Enable long mode.
292  efer.lme = 1;
293  tc->setMiscReg(MISCREG_EFER, efer);
294 
295  // Start using longmode segments.
296  installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
297  installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
298  installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
299  installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
300  installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
301  installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
302 
303  // Activate long mode.
304  cr0.pg = 1;
305  tc->setMiscReg(MISCREG_CR0, cr0);
306 
307  tc->pcState(kernelObj->entryPoint());
308 
309  // We should now be in long mode. Yay!
310 
311  Addr ebdaPos = 0xF0000;
312  Addr fixed, table;
313 
314  // Write out the SMBios/DMI table.
315  writeOutSMBiosTable(ebdaPos, fixed, table);
316  ebdaPos += (fixed + table);
317  ebdaPos = roundUp(ebdaPos, 16);
318 
319  // Write out the Intel MP Specification configuration table.
320  writeOutMPTable(ebdaPos, fixed, table);
321  ebdaPos += (fixed + table);
322 }
323 
324 void
326  Addr &headerSize, Addr &structSize, Addr table)
327 {
328  // If the table location isn't specified, just put it after the header.
329  // The header size as of the 2.5 SMBios specification is 0x1F bytes.
330  if (!table)
331  table = header + 0x1F;
332  smbiosTable->setTableAddr(table);
333 
334  smbiosTable->writeOut(system->physProxy, header, headerSize, structSize);
335 
336  // Do some bounds checking to make sure we at least didn't step on
337  // ourselves.
338  assert(header > table || header + headerSize <= table);
339  assert(table > header || table + structSize <= header);
340 }
341 
342 void
343 FsWorkload::writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table)
344 {
345  // If the table location isn't specified and it exists, just put
346  // it after the floating pointer. The fp size as of the 1.4 Intel MP
347  // specification is 0x10 bytes.
348  if (mpConfigTable) {
349  if (!table)
350  table = fp + 0x10;
352  }
353 
355  if (mpConfigTable)
356  tableSize = mpConfigTable->writeOut(system->physProxy, table);
357  else
358  tableSize = 0;
359 
360  // Do some bounds checking to make sure we at least didn't step on
361  // ourselves and the fp structure was the size we thought it was.
362  assert(fp > table || fp + fpSize <= table);
363  assert(table > fp || table + tableSize <= fp);
364  assert(fpSize == 0x10);
365 }
366 
367 } // namespace X86ISA
368 
370 X86FsWorkloadParams::create()
371 {
372  return new X86ISA::FsWorkload(this);
373 }
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
X86ISA::IntelMP::FloatingPointer::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:109
ArmISA::fp
Bitfield< 19, 16 > fp
Definition: miscregs_types.hh:173
MipsISA::ds
Bitfield< 15, 13 > ds
Definition: pra_constants.hh:235
X86ISA::FsWorkload::mpConfigTable
IntelMP::ConfigTable * mpConfigTable
Definition: fs_workload.hh:95
X86ISA::MISCREG_TSG_LIMIT
@ MISCREG_TSG_LIMIT
Definition: misc.hh:354
system.hh
X86ISA::SEGMENT_REG_FS
@ SEGMENT_REG_FS
Definition: segment.hh:49
System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:324
X86ISA::MISCREG_TSL
@ MISCREG_TSL
Definition: misc.hh:303
X86ISA::FsWorkload::FsWorkload
FsWorkload(Params *p)
Definition: fs_workload.cc:53
KernelWorkload
Definition: kernel_workload.hh:42
X86ISA::MISCREG_ES
@ MISCREG_ES
Definition: misc.hh:296
intelmp.hh
X86ISA::IntelMP::FloatingPointer::setTableAddr
void setTableAddr(Addr addr)
Definition: intelmp.hh:107
htole
T htole(T value)
Definition: byteswap.hh:140
X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:297
X86ISA::MISCREG_SEG_LIMIT
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:526
Workload::system
System * system
Definition: workload.hh:64
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
header
output header
Definition: nop.cc:36
X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:245
X86ISA::IntelMP::ConfigTable::writeOut
Addr writeOut(PortProxy &proxy, Addr addr)
Definition: intelmp.cc:191
faults.hh
PortProxy::writeBlob
void writeBlob(Addr addr, const void *p, int size) const
Same as tryWriteBlob, but insists on success.
Definition: port_proxy.hh:187
smbios.hh
X86ISA::FsWorkload
Definition: fs_workload.hh:82
X86ISA::MISCREG_DS
@ MISCREG_DS
Definition: misc.hh:299
X86ISA::SEGMENT_REG_TSL
@ SEGMENT_REG_TSL
Definition: segment.hh:52
KernelWorkload::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: kernel_workload.cc:86
X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:109
Loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:108
X86ISA::SMBios::SMBiosTable::writeOut
void writeOut(PortProxy &proxy, Addr addr, Addr &headerSize, Addr &structSize)
Definition: smbios.cc:215
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
X86ISA::InitInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr) override
Definition: faults.cc:183
isa_traits.hh
ArmISA::attr
attr
Definition: miscregs_types.hh:649
Loader::I386
@ I386
Definition: object_file.hh:50
X86ISA::MISCREG_SEG_ATTR
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:533
X86ISA::InitInterrupt
Definition: faults.hh:346
KernelWorkload::kernelObj
Loader::ObjectFile * kernelObj
Definition: kernel_workload.hh:71
X86ISA::FsWorkload::mpFloatingPointer
IntelMP::FloatingPointer * mpFloatingPointer
Definition: fs_workload.hh:94
X86ISA::SegmentRegIndex
SegmentRegIndex
Definition: segment.hh:43
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
X86ISA::FsWorkload::writeOutMPTable
void writeOutMPTable(Addr fp, Addr &fpSize, Addr &tableSize, Addr table=0)
Definition: fs_workload.cc:343
X86ISA::MISCREG_FS
@ MISCREG_FS
Definition: misc.hh:300
X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:108
X86ISA::offset
offset
Definition: misc.hh:1024
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
X86ISA::FsWorkload::writeOutSMBiosTable
void writeOutSMBiosTable(Addr header, Addr &headerSize, Addr &tableSize, Addr table=0)
Definition: fs_workload.cc:325
X86ISA::FsWorkload::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: fs_workload.cc:105
X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:519
X86ISA::MISCREG_SS
@ MISCREG_SS
Definition: misc.hh:298
System::threads
Threads threads
Definition: system.hh:309
X86ISA::SEGMENT_REG_DS
@ SEGMENT_REG_DS
Definition: segment.hh:48
X86ISA::SEGMENT_REG_SS
@ SEGMENT_REG_SS
Definition: segment.hh:47
Loader::ObjectFile::getArch
Arch getArch() const
Definition: object_file.hh:99
X86ISA::SEGMENT_REG_CS
@ SEGMENT_REG_CS
Definition: segment.hh:46
X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
X86ISA::SYS_SEGMENT_REG_TR
@ SYS_SEGMENT_REG_TR
Definition: segment.hh:59
roundUp
T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:131
X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:105
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
X86ISA::installSegDesc
void installSegDesc(ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode)
Definition: fs_workload.cc:61
X86ISA::SEGMENT_REG_ES
@ SEGMENT_REG_ES
Definition: segment.hh:45
X86ISA::MISCREG_TR
@ MISCREG_TR
Definition: misc.hh:307
X86ISA::SEGMENT_REG_GS
@ SEGMENT_REG_GS
Definition: segment.hh:50
X86ISA::MISCREG_SEG_BASE
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:512
fs_workload.hh
X86ISA::MISCREG_GS
@ MISCREG_GS
Definition: misc.hh:301
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:219
X86ISA::FsWorkload::Params
X86FsWorkloadParams Params
Definition: fs_workload.hh:85
object_file.hh
X86ISA::FsWorkload::smbiosTable
SMBios::SMBiosTable * smbiosTable
Definition: fs_workload.hh:93
thread_context.hh
X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:82
RegVal
uint64_t RegVal
Definition: types.hh:168
X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:320
X86ISA::SMBios::SMBiosTable::setTableAddr
void setTableAddr(Addr addr)
Definition: smbios.hh:219

Generated on Wed Sep 30 2020 14:01:59 for gem5 by doxygen 1.8.17