gem5
v20.1.0.0
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#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/x86/generated/max_inst_regs.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
Go to the source code of this file.
Namespaces | |
X86ISA | |
This is exposed globally, independent of the ISA. | |
Typedefs | |
using | X86ISA::VecElem = ::DummyVecElem |
using | X86ISA::VecReg = ::DummyVecReg |
using | X86ISA::ConstVecReg = ::DummyConstVecReg |
using | X86ISA::VecRegContainer = ::DummyVecRegContainer |
using | X86ISA::VecPredReg = ::DummyVecPredReg |
using | X86ISA::ConstVecPredReg = ::DummyConstVecPredReg |
using | X86ISA::VecPredRegContainer = ::DummyVecPredRegContainer |
Enumerations | |
enum | X86ISA::DependenceTags { X86ISA::FP_Reg_Base = 128, X86ISA::CC_Reg_Base = FP_Reg_Base + NumFloatRegs, X86ISA::Misc_Reg_Base = CC_Reg_Base + NumCCRegs, X86ISA::Max_Reg_Index = Misc_Reg_Base + NumMiscRegs } |
Variables | |
const int | X86ISA::NumMiscRegs = NUM_MISCREGS |
const int | X86ISA::NumIntArchRegs = NUM_INTREGS |
const int | X86ISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs |
const int | X86ISA::NumCCRegs = NUM_CCREGS |
const int | X86ISA::NumFloatRegs |
const int | X86ISA::NumVecRegs = 1 |
const int | X86ISA::NumVecPredRegs = 1 |
const int | X86ISA::ZeroReg = NUM_INTREGS |
const int | X86ISA::StackPointerReg = INTREG_RSP |
const int | X86ISA::ReturnAddressReg = 0 |
const int | X86ISA::ReturnValueReg = INTREG_RAX |
const int | X86ISA::FramePointerReg = INTREG_RBP |
const int | X86ISA::SyscallPseudoReturnReg = INTREG_RDX |
constexpr unsigned | X86ISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg |
constexpr size_t | X86ISA::VecRegSizeBytes = ::DummyVecRegSizeBytes |
constexpr size_t | X86ISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits |
constexpr bool | X86ISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr |