gem5  v20.1.0.0
registers.hh
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38 
39 #ifndef __ARCH_X86_REGISTERS_HH__
40 #define __ARCH_X86_REGISTERS_HH__
41 
43 #include "arch/generic/vec_reg.hh"
44 #include "arch/x86/generated/max_inst_regs.hh"
45 #include "arch/x86/regs/int.hh"
46 #include "arch/x86/regs/ccr.hh"
47 #include "arch/x86/regs/misc.hh"
48 #include "arch/x86/x86_traits.hh"
49 
50 namespace X86ISA
51 {
53 using X86ISAInst::MaxInstDestRegs;
56 
59 const int NumCCRegs = NUM_CCREGS;
60 
61 // Each 128 bit xmm register is broken into two effective 64 bit registers.
62 // Add 8 for the indices that are mapped over the fp stack
63 const int NumFloatRegs =
65 
66 // These enumerate all the registers for dependence tracking.
68  // FP_Reg_Base must be large enough to be bigger than any integer
69  // register index which has the IntFoldBit (1 << 6) set. To be safe
70  // we just start at (1 << 7) == 128.
71  FP_Reg_Base = 128,
75 };
76 
77 const int NumVecRegs = 1; // Not applicable to x86
78  // (1 to prevent warnings)
79 const int NumVecPredRegs = 1; // Not applicable to x86
80  // (1 to prevent warnings)
81 
82 // semantically meaningful register indices
83 //There is no such register in X86
84 const int ZeroReg = NUM_INTREGS;
85 const int StackPointerReg = INTREG_RSP;
86 //X86 doesn't seem to have a link register
87 const int ReturnAddressReg = 0;
88 const int ReturnValueReg = INTREG_RAX;
89 const int FramePointerReg = INTREG_RBP;
90 
91 // Some OS syscalls use a second register (rdx) to return a second
92 // value
93 const int SyscallPseudoReturnReg = INTREG_RDX;
94 
95 // Not applicable to x86
102 
103 // Not applicable to x86
109 
110 } // namespace X86ISA
111 
112 #endif // __ARCH_X86_REGFILE_HH__
DummyVecRegSizeBytes
constexpr size_t DummyVecRegSizeBytes
Definition: vec_reg.hh:669
x86_traits.hh
X86ISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:58
DummyVecPredRegSizeBits
constexpr size_t DummyVecPredRegSizeBits
Definition: vec_pred_reg.hh:398
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
X86ISA::ReturnValueReg
const int ReturnValueReg
Definition: registers.hh:88
X86ISA::NumVecPredRegs
const int NumVecPredRegs
Definition: registers.hh:79
DummyVecPredRegHasPackedRepr
constexpr bool DummyVecPredRegHasPackedRepr
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:391
X86ISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:55
ccr.hh
X86ISA::NUM_CCREGS
@ NUM_CCREGS
Definition: ccr.hh:53
X86ISA::NumImplicitIntRegs
const int NumImplicitIntRegs
Definition: x86_traits.hh:49
X86ISA::CC_Reg_Base
@ CC_Reg_Base
Definition: registers.hh:72
X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:59
DummyVecPredReg
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, false > DummyVecPredReg
Definition: vec_pred_reg.hh:393
ArmISA::MaxInstSrcRegs
const int MaxInstSrcRegs
Definition: registers.hh:57
X86ISA::SyscallPseudoReturnReg
const int SyscallPseudoReturnReg
Definition: registers.hh:93
X86ISA::ReturnAddressReg
const int ReturnAddressReg
Definition: registers.hh:87
X86ISA::FP_Reg_Base
@ FP_Reg_Base
Definition: registers.hh:71
X86ISA::Max_Reg_Index
@ Max_Reg_Index
Definition: registers.hh:74
DummyVecRegContainer
DummyVecReg::Container DummyVecRegContainer
Definition: vec_reg.hh:668
X86ISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:100
X86ISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:398
X86ISA::Misc_Reg_Base
@ Misc_Reg_Base
Definition: registers.hh:73
VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:66
DummyConstVecReg
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, true > DummyConstVecReg
Definition: vec_reg.hh:667
X86ISA::VecRegSizeBytes
constexpr size_t VecRegSizeBytes
Definition: registers.hh:101
X86ISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:63
int.hh
DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:664
vec_pred_reg.hh
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
DummyVecReg
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, false > DummyVecReg
Definition: vec_reg.hh:666
DummyVecPredRegContainer
DummyVecPredReg::Container DummyVecPredRegContainer
Definition: vec_pred_reg.hh:397
X86ISA::DependenceTags
DependenceTags
Definition: registers.hh:67
X86ISA::ZeroReg
const int ZeroReg
Definition: registers.hh:84
X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:58
X86ISA::NumIntArchRegs
const int NumIntArchRegs
Definition: registers.hh:57
vec_reg.hh
X86ISA::VecElem
::DummyVecElem VecElem
Definition: registers.hh:96
X86ISA::VecPredRegHasPackedRepr
constexpr bool VecPredRegHasPackedRepr
Definition: registers.hh:108
X86ISA::VecPredRegSizeBits
constexpr size_t VecPredRegSizeBits
Definition: registers.hh:107
DummyConstVecPredReg
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, true > DummyConstVecPredReg
Definition: vec_pred_reg.hh:396
ArmISA::NUM_INTREGS
@ NUM_INTREGS
Definition: intregs.hh:123
RiscvISA::MaxMiscDestRegs
const int MaxMiscDestRegs
Definition: registers.hh:62
DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:665
X86ISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: x86_traits.hh:47
misc.hh
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
X86ISA::NumVecRegs
const int NumVecRegs
Definition: registers.hh:77
X86ISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:85
X86ISA::NumCCRegs
const int NumCCRegs
Definition: registers.hh:59
VecRegT
Vector Register Abstraction This generic class is a view in a particularization of MVC,...
Definition: vec_reg.hh:170
X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:57
X86ISA::FramePointerReg
const int FramePointerReg
Definition: registers.hh:89

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