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cortex_a76.cc
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27 
28 #include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"
29 
30 #include "arch/arm/fastmodel/iris/cpu.hh"
31 #include "base/logging.hh"
32 #include "dev/arm/base_gic.hh"
33 #include "sim/core.hh"
34 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
35 
36 namespace FastModel
37 {
38 
39 void
40 CortexA76::initState()
41 {
42  for (auto *tc : threadContexts)
43  tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq);
44 
45  evs_base_cpu->setSysCounterFrq(params().cntfrq);
46 }
47 
48 void
49 CortexA76::setCluster(CortexA76Cluster *_cluster, int _num)
50 {
51  cluster = _cluster;
52  num = _num;
53 
54  set_evs_param("CFGEND", params().CFGEND);
55  set_evs_param("CFGTE", params().CFGTE);
56  set_evs_param("CRYPTODISABLE", params().CRYPTODISABLE);
57  set_evs_param("RVBARADDR", params().RVBARADDR);
58  set_evs_param("VINITHI", params().VINITHI);
59  set_evs_param("enable_trace_special_hlt_imm16",
60  params().enable_trace_special_hlt_imm16);
61  set_evs_param("l2cache-hit_latency", params().l2cache_hit_latency);
62  set_evs_param("l2cache-maintenance_latency",
63  params().l2cache_maintenance_latency);
64  set_evs_param("l2cache-miss_latency", params().l2cache_miss_latency);
65  set_evs_param("l2cache-read_access_latency",
66  params().l2cache_read_access_latency);
67  set_evs_param("l2cache-read_latency", params().l2cache_read_latency);
68  set_evs_param("l2cache-size", params().l2cache_size);
69  set_evs_param("l2cache-snoop_data_transfer_latency",
70  params().l2cache_snoop_data_transfer_latency);
71  set_evs_param("l2cache-snoop_issue_latency",
72  params().l2cache_snoop_issue_latency);
73  set_evs_param("l2cache-write_access_latency",
74  params().l2cache_write_access_latency);
75  set_evs_param("l2cache-write_latency", params().l2cache_write_latency);
76  set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
77  set_evs_param("min_sync_level", params().min_sync_level);
78  set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
79  set_evs_param("semihosting-A64_HLT", params().semihosting_A64_HLT);
80  set_evs_param("semihosting-ARM_SVC", params().semihosting_ARM_SVC);
81  set_evs_param("semihosting-T32_HLT", params().semihosting_T32_HLT);
82  set_evs_param("semihosting-Thumb_SVC", params().semihosting_Thumb_SVC);
83  set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
84  set_evs_param("semihosting-cwd", params().semihosting_cwd);
85  set_evs_param("semihosting-enable", params().semihosting_enable);
86  set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
87  set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
88  set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
89  set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
90  set_evs_param("trace_special_hlt_imm16", params().trace_special_hlt_imm16);
91  set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
92 }
93 
94 Port &
95 CortexA76::getPort(const std::string &if_name, PortID idx)
96 {
97  if (if_name == "redistributor")
98  return cluster->getEvs()->gem5_getPort(if_name, num);
99  else
100  return Base::getPort(if_name, idx);
101 }
102 
103 CortexA76Cluster::CortexA76Cluster(const Params &p) :
104  SimObject(p), cores(p.cores), evs(p.evs)
105 {
106  for (int i = 0; i < p.cores.size(); i++)
107  p.cores[i]->setCluster(this, i);
108 
109  Iris::BaseCpuEvs *e = dynamic_cast<Iris::BaseCpuEvs *>(evs);
110  panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
111  e->setCluster(this);
112 
113  set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC);
114  set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT);
115  set_evs_param("core.BROADCASTOUTER", p.BROADCASTOUTER);
116  set_evs_param("core.BROADCASTPERSIST", p.BROADCASTPERSIST);
117  set_evs_param("core.CLUSTER_ID", p.CLUSTER_ID);
118  set_evs_param("core.GICDISABLE", p.GICDISABLE);
119  set_evs_param("core.cpi_div", p.cpi_div);
120  set_evs_param("core.cpi_mul", p.cpi_mul);
121  set_evs_param("core.dcache-hit_latency", p.dcache_hit_latency);
122  set_evs_param("core.dcache-maintenance_latency",
123  p.dcache_maintenance_latency);
124  set_evs_param("core.dcache-miss_latency", p.dcache_miss_latency);
125  set_evs_param("core.dcache-prefetch_enabled",
126  p.dcache_prefetch_enabled);
127  set_evs_param("core.dcache-read_access_latency",
128  p.dcache_read_access_latency);
129  set_evs_param("core.dcache-read_latency", p.dcache_read_latency);
130  set_evs_param("core.dcache-snoop_data_transfer_latency",
131  p.dcache_snoop_data_transfer_latency);
132  set_evs_param("core.dcache-state_modelled", p.dcache_state_modelled);
133  set_evs_param("core.dcache-write_access_latency",
134  p.dcache_write_access_latency);
135  set_evs_param("core.dcache-write_latency", p.dcache_write_latency);
136  set_evs_param("core.default_opmode", p.default_opmode);
137  set_evs_param("core.diagnostics", p.diagnostics);
138  set_evs_param("core.enable_simulation_performance_optimizations",
139  p.enable_simulation_performance_optimizations);
140  set_evs_param("core.ext_abort_device_read_is_sync",
141  p.ext_abort_device_read_is_sync);
142  set_evs_param("core.ext_abort_device_write_is_sync",
143  p.ext_abort_device_write_is_sync);
144  set_evs_param("core.ext_abort_so_read_is_sync",
145  p.ext_abort_so_read_is_sync);
146  set_evs_param("core.ext_abort_so_write_is_sync",
147  p.ext_abort_so_write_is_sync);
148  set_evs_param("core.gicv3.cpuintf-mmap-access-level",
149  p.gicv3_cpuintf_mmap_access_level);
150  set_evs_param("core.has_peripheral_port", p.has_peripheral_port);
151  set_evs_param("core.has_statistical_profiling",
152  p.has_statistical_profiling);
153  set_evs_param("core.icache-hit_latency", p.icache_hit_latency);
154  set_evs_param("core.icache-maintenance_latency",
155  p.icache_maintenance_latency);
156  set_evs_param("core.icache-miss_latency", p.icache_miss_latency);
157  set_evs_param("core.icache-prefetch_enabled",
158  p.icache_prefetch_enabled);
159  set_evs_param("core.icache-read_access_latency",
160  p.icache_read_access_latency);
161  set_evs_param("core.icache-read_latency", p.icache_read_latency);
162  set_evs_param("core.icache-state_modelled", p.icache_state_modelled);
163  set_evs_param("core.l3cache-hit_latency", p.l3cache_hit_latency);
164  set_evs_param("core.l3cache-maintenance_latency",
165  p.l3cache_maintenance_latency);
166  set_evs_param("core.l3cache-miss_latency", p.l3cache_miss_latency);
167  set_evs_param("core.l3cache-read_access_latency",
168  p.l3cache_read_access_latency);
169  set_evs_param("core.l3cache-read_latency", p.l3cache_read_latency);
170  set_evs_param("core.l3cache-size", p.l3cache_size);
171  set_evs_param("core.l3cache-snoop_data_transfer_latency",
172  p.l3cache_snoop_data_transfer_latency);
173  set_evs_param("core.l3cache-snoop_issue_latency",
174  p.l3cache_snoop_issue_latency);
175  set_evs_param("core.l3cache-write_access_latency",
176  p.l3cache_write_access_latency);
177  set_evs_param("core.l3cache-write_latency", p.l3cache_write_latency);
178  set_evs_param("core.pchannel_treat_simreset_as_poreset",
179  p.pchannel_treat_simreset_as_poreset);
180  set_evs_param("core.periph_address_end", p.periph_address_end);
181  set_evs_param("core.periph_address_start", p.periph_address_start);
182  set_evs_param("core.ptw_latency", p.ptw_latency);
183  set_evs_param("core.tlb_latency", p.tlb_latency);
184  set_evs_param("core.treat-dcache-cmos-to-pou-as-nop",
185  p.treat_dcache_cmos_to_pou_as_nop);
186  set_evs_param("core.walk_cache_latency", p.walk_cache_latency);
187 }
188 
189 Port &
190 CortexA76Cluster::getPort(const std::string &if_name, PortID idx)
191 {
192  if (if_name == "amba") {
193  return evs->gem5_getPort(if_name, idx);
194  } else {
195  return SimObject::getPort(if_name, idx);
196  }
197 }
198 
199 } // namespace FastModel
BaseCPU::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Definition: base.cc:406
SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:162
cortex_a76.hh
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:749
gem5_to_tlm.hh
base_gic.hh
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:243
FastModel::CortexA76::setCluster
void setCluster(CortexA76Cluster *_cluster, int _num)
Definition: cortex_a76.cc:49
Iris::BaseCpuEvs::setSysCounterFrq
virtual void setSysCounterFrq(uint64_t sys_counter_frq)=0
Iris::BaseCPU::evs_base_cpu
Iris::BaseCpuEvs * evs_base_cpu
Definition: cpu.hh:93
cpu.hh
FastModel::CortexA76::cluster
CortexA76Cluster * cluster
Definition: cortex_a76.hh:57
FastModel::CortexA76::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: cortex_a76.cc:40
sc_core::sc_module::gem5_getPort
virtual ::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:120
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:269
FastModel::CortexA76::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:95
core.hh
FastModel::CortexA76::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:103
ArmISA::e
Bitfield< 9 > e
Definition: miscregs_types.hh:61
FastModel::CortexA76::num
int num
Definition: cortex_a76.hh:58
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
FastModel
Definition: amba_from_tlm_bridge.cc:32
FastModel::CortexA76Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:87
FastModel::CortexA76Cluster
Definition: cortex_a76.hh:77
FastModel::CortexA76Cluster::getEvs
sc_core::sc_module * getEvs() const
Definition: cortex_a76.hh:93
logging.hh
FastModel::CortexA76Cluster::CortexA76Cluster
CortexA76Cluster(const Params &p)
Definition: cortex_a76.cc:103
SimObject::params
const Params & params() const
Definition: sim_object.hh:168
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
FastModel::CortexA76Cluster::evs
sc_core::sc_module * evs
Definition: cortex_a76.hh:81
FastModel::CortexA76Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:190
Iris::BaseCpuEvs
Definition: cpu.hh:42
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:141
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