base.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2011-2013, 2017, 2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_BASE_HH__
#define __CPU_BASE_HH__
 
#include <vector>
 
// Before we do anything else, check if this build is the NULL ISA,
// and if so stop here
#include "config/the_isa.hh"
#if THE_ISA == NULL_ISA
#error Including BaseCPU in a system without CPU support
#else
#include "arch/generic/interrupts.hh"
#include "base/statistics.hh"
#include "mem/port_proxy.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/insttracer.hh"
#include "sim/probe/pmu.hh"
#include "sim/probe/probe.hh"
#include "sim/system.hh"
#include "debug/Mwait.hh"
 
class BaseCPU;
struct BaseCPUParams;
class CheckerCPU;
class ThreadContext;
 
struct AddressMonitor
{
    AddressMonitor();
    bool doMonitor(PacketPtr pkt);
 
    bool armed;
    Addr vAddr;
    Addr pAddr;
    uint64_t val;
    bool waiting;   // 0=normal, 1=mwaiting
    bool gotWakeup;
};
 
class CPUProgressEvent : public Event
{
  protected:
    Tick _interval;
    Counter lastNumInst;
    BaseCPU *cpu;
    bool _repeatEvent;
 
  public:
    CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
 
    void process();
 
    void interval(Tick ival) { _interval = ival; }
    Tick interval() { return _interval; }
 
    void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 
    virtual const char *description() const;
};
 
class BaseCPU : public ClockedObject
{
  protected:
 
    Tick instCnt;
 
    // every cpu has an id, put it in the base cpu
    // Set at initialization, only time a cpuId might change is during a
    // takeover (which should be done from within the BaseCPU anyway,
    // therefore no setCpuId() method is provided
    int _cpuId;
 
    const uint32_t _socketId;
 
    RequestorID _instRequestorId;
 
    RequestorID _dataRequestorId;
 
    uint32_t _taskId;
 
    uint32_t _pid;
 
    bool _switchedOut;
 
    const unsigned int _cacheLineSize;
 
    struct GlobalStats : public Stats::Group {
        GlobalStats(::Stats::Group *parent);
 
        ::Stats::Value simInsts;
        ::Stats::Value simOps;
 
        ::Stats::Formula hostInstRate;
        ::Stats::Formula hostOpRate;
    };
 
    static std::unique_ptr<GlobalStats> globalStats;
 
  public:
 
    virtual Port &getDataPort() = 0;
 
    virtual PortProxy::SendFunctionalFunc
    getSendFunctional()
    {
        auto port = dynamic_cast<RequestPort *>(&getDataPort());
        assert(port);
        return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
    }
 
    virtual Port &getInstPort() = 0;
 
    int cpuId() const { return _cpuId; }
 
    uint32_t socketId() const { return _socketId; }
 
    RequestorID dataRequestorId() const { return _dataRequestorId; }
    RequestorID instRequestorId() const { return _instRequestorId; }
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
 
    uint32_t taskId() const { return _taskId; }
    void taskId(uint32_t id) { _taskId = id; }
 
    uint32_t getPid() const { return _pid; }
    void setPid(uint32_t pid) { _pid = pid; }
 
    inline void workItemBegin() { baseStats.numWorkItemsStarted++; }
    inline void workItemEnd() { baseStats.numWorkItemsCompleted++; }
    // @todo remove me after debugging with legion done
    Tick instCount() { return instCnt; }
 
  protected:
    std::vector<BaseInterrupts*> interrupts;
 
  public:
    BaseInterrupts *
    getInterruptController(ThreadID tid)
    {
        if (interrupts.empty())
            return NULL;
 
        assert(interrupts.size() > tid);
        return interrupts[tid];
    }
 
    virtual void wakeup(ThreadID tid) = 0;
 
    void
    postInterrupt(ThreadID tid, int int_num, int index);
 
    void
    clearInterrupt(ThreadID tid, int int_num, int index)
    {
        interrupts[tid]->clear(int_num, index);
    }
 
    void
    clearInterrupts(ThreadID tid)
    {
        interrupts[tid]->clearAll();
    }
 
    bool
    checkInterrupts(ThreadID tid) const
    {
        return FullSystem && interrupts[tid]->checkInterrupts();
    }
 
  protected:
    std::vector<ThreadContext *> threadContexts;
 
    Trace::InstTracer * tracer;
 
  public:
 
 
    static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
 
    // Mask to align PCs to MachInst sized boundaries
    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 
    Trace::InstTracer * getTracer() { return tracer; }
 
    virtual void activateContext(ThreadID thread_num);
 
    virtual void suspendContext(ThreadID thread_num);
 
    virtual void haltContext(ThreadID thread_num);
 
   int findContext(ThreadContext *tc);
 
   virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 
   unsigned numContexts() {
       return static_cast<unsigned>(threadContexts.size());
   }
 
    ThreadID contextToThread(ContextID cid)
    { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
 
  public:
    PARAMS(BaseCPU);
    BaseCPU(const Params &params, bool is_checker = false);
    virtual ~BaseCPU();
 
    void init() override;
    void startup() override;
    void regStats() override;
 
    void regProbePoints() override;
 
    void registerThreadContexts();
 
    // Functions to deschedule and reschedule the events to enter the
    // power gating sleep before and after checkpoiting respectively.
    void deschedulePowerGatingEvent();
    void schedulePowerGatingEvent();
 
    virtual void switchOut();
 
    virtual void takeOverFrom(BaseCPU *cpu);
 
    void flushTLBs();
 
    bool switchedOut() const { return _switchedOut; }
 
    virtual void verifyMemoryMode() const { };
 
    ThreadID numThreads;
 
    System *system;
 
    inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 
    void serialize(CheckpointOut &cp) const override;
 
    void unserialize(CheckpointIn &cp) override;
 
    virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
 
    virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
 
    virtual Counter totalInsts() const = 0;
 
    virtual Counter totalOps() const = 0;
 
    void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
 
    uint64_t getCurrentInstCount(ThreadID tid);
 
  public:
    virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
 
   protected:
    ProbePoints::PMUUPtr pmuProbePoint(const char *name);
 
    ProbePoints::PMUUPtr ppRetiredInsts;
    ProbePoints::PMUUPtr ppRetiredInstsPC;
 
    ProbePoints::PMUUPtr ppRetiredLoads;
    ProbePoints::PMUUPtr ppRetiredStores;
 
    ProbePoints::PMUUPtr ppRetiredBranches;
 
    ProbePoints::PMUUPtr ppAllCycles;
 
    ProbePoints::PMUUPtr ppActiveCycles;
 
    ProbePointArg<bool> *ppSleeping;
    enum CPUState {
        CPU_STATE_ON,
        CPU_STATE_SLEEP,
        CPU_STATE_WAKEUP
    };
 
    Cycles previousCycle;
    CPUState previousState;
 
    inline void updateCycleCounters(CPUState state)
    {
        uint32_t delta = curCycle() - previousCycle;
 
        if (previousState == CPU_STATE_ON) {
            ppActiveCycles->notify(delta);
        }
 
        switch (state)
        {
          case CPU_STATE_WAKEUP:
            ppSleeping->notify(false);
            break;
          case CPU_STATE_SLEEP:
            ppSleeping->notify(true);
            break;
          default:
            break;
        }
 
        ppAllCycles->notify(delta);
 
        previousCycle = curCycle();
        previousState = state;
    }
 
    // Function tracing
  private:
    bool functionTracingEnabled;
    std::ostream *functionTraceStream;
    Addr currentFunctionStart;
    Addr currentFunctionEnd;
    Tick functionEntryTick;
    void enableFunctionTrace();
    void traceFunctionsInternal(Addr pc);
 
  private:
    static std::vector<BaseCPU *> cpuList;   
 
  public:
    void traceFunctions(Addr pc)
    {
        if (functionTracingEnabled)
            traceFunctionsInternal(pc);
    }
 
    static int numSimulatedCPUs() { return cpuList.size(); }
    static Counter numSimulatedInsts()
    {
        Counter total = 0;
 
        int size = cpuList.size();
        for (int i = 0; i < size; ++i)
            total += cpuList[i]->totalInsts();
 
        return total;
    }
 
    static Counter numSimulatedOps()
    {
        Counter total = 0;
 
        int size = cpuList.size();
        for (int i = 0; i < size; ++i)
            total += cpuList[i]->totalOps();
 
        return total;
    }
 
  public:
    struct BaseCPUStats : public Stats::Group
    {
        BaseCPUStats(Stats::Group *parent);
        // Number of CPU cycles simulated
        Stats::Scalar numCycles;
        Stats::Scalar numWorkItemsStarted;
        Stats::Scalar numWorkItemsCompleted;
    } baseStats;
 
  private:
    std::vector<AddressMonitor> addressMonitor;
 
  public:
    void armMonitor(ThreadID tid, Addr address);
    bool mwait(ThreadID tid, PacketPtr pkt);
    void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
    AddressMonitor *getCpuAddrMonitor(ThreadID tid)
    {
        assert(tid < numThreads);
        return &addressMonitor[tid];
    }
 
    bool waitForRemoteGDB() const;
 
    Cycles syscallRetryLatency;
 
  // Enables CPU to enter power gating on a configurable cycle count
  protected:
    void enterPwrGating();
 
    const Cycles pwrGatingLatency;
    const bool powerGatingOnIdle;
    EventFunctionWrapper enterPwrGatingEvent;
};
 
#endif // THE_ISA == NULL_ISA
 
#endif // __CPU_BASE_HH__