#include <base_dyn_inst.hh>

Inheritance diagram for BaseDynInst< Impl >:

Classes
struct	Regs
	Collect register related information into a single struct. More...

Public Types
typedef Impl::CPUType	ImplCPU

typedef ImplCPU::ImplState	ImplState

using	LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest *

using	LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator

using	SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator

typedef Impl::DynInstPtr	DynInstPtr

typedef RefCountingPtr< BaseDynInst< Impl > >	BaseDynInstPtr

typedef std::list< DynInstPtr >::iterator	ListIt

Public Member Functions
BaseCPU *	getCpuPtr ()

void	recordResult (bool f)
	Records changes to result? More...

bool	effAddrValid () const
	Is the effective virtual address valid. More...

void	effAddrValid (bool b)

bool	memOpDone () const
	Whether or not the memory operation is done. More...

void	memOpDone (bool f)

bool	notAnInst () const

void	setNotAnInst ()

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...

Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override

Fault	initiateHtmCmd (Request::Flags flags) override
	Initiate an HTM command, e.g. More...

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable) override

Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

bool	translationStarted () const
	True if the DTB address translation has started. More...

void	translationStarted (bool f)

bool	translationCompleted () const
	True if the DTB address translation has completed. More...

void	translationCompleted (bool f)

bool	possibleLoadViolation () const
	True if this address was found to match a previous load and they issued out of order. More...

void	possibleLoadViolation (bool f)

bool	hitExternalSnoop () const
	True if the address hit a external snoop while sitting in the LSQ. More...

void	hitExternalSnoop (bool f)

bool	isTranslationDelayed () const
	Returns true if the DTB address translation is being delayed due to a hw page table walk. More...

void	renameDestReg (int idx, PhysRegIdPtr renamed_dest, PhysRegIdPtr previous_rename)
	Renames a destination register to a physical register. More...

void	renameSrcReg (int idx, PhysRegIdPtr renamed_src)
	Renames a source logical register to the physical register which has/will produce that logical register's result. More...

	BaseDynInst (const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu)
	BaseDynInst constructor given a binary instruction. More...

	BaseDynInst (const StaticInstPtr &staticInst, const StaticInstPtr &macroop)
	BaseDynInst constructor given a StaticInst pointer. More...

	~BaseDynInst ()
	BaseDynInst destructor. More...

void	dump ()
	Dumps out contents of this BaseDynInst. More...

void	dump (std::string &outstring)
	Dumps out contents of this BaseDynInst into given string. More...

int	cpuId () const
	Read this CPU's ID. More...

uint32_t	socketId () const
	Read this CPU's Socket ID. More...

RequestorID	requestorId () const
	Read this CPU's data requestor ID. More...

ContextID	contextId () const
	Read this context's system-wide ID. More...

Fault	getFault () const
	Returns the fault type. More...

Fault &	getFault ()
	TODO: This I added for the LSQRequest side to be able to modify the fault. More...

bool	doneTargCalc ()
	Checks whether or not this instruction has had its branch target calculated yet. More...

void	setPredTarg (const TheISA::PCState &_predPC)
	Set the predicted target of this current instruction. More...

const TheISA::PCState &	readPredTarg ()

Addr	predInstAddr ()
	Returns the predicted PC immediately after the branch. More...

Addr	predNextInstAddr ()
	Returns the predicted PC two instructions after the branch. More...

Addr	predMicroPC ()
	Returns the predicted micro PC after the branch. More...

bool	readPredTaken ()
	Returns whether the instruction was predicted taken or not. More...

void	setPredTaken (bool predicted_taken)

bool	mispredicted ()
	Returns whether the instruction mispredicted. More...

bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isVector () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isFullMemBarrier () const

bool	isReadBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isUnverifiable () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isHtmStart () const

bool	isHtmStop () const

bool	isHtmCancel () const

bool	isHtmCmd () const

uint64_t	getHtmTransactionUid () const override

uint64_t	newHtmTransactionUid () const override

bool	inHtmTransactionalState () const override

uint64_t	getHtmTransactionalDepth () const override

void	setHtmTransactionalState (uint64_t htm_uid, uint64_t htm_depth)

void	clearHtmTransactionalState ()

void	setSerializeBefore ()
	Temporarily sets this instruction as a serialize before instruction. More...

void	clearSerializeBefore ()
	Clears the serializeBefore part of this instruction. More...

bool	isTempSerializeBefore ()
	Checks if this serializeBefore is only temporarily set. More...

void	setSerializeAfter ()
	Temporarily sets this instruction as a serialize after instruction. More...

void	clearSerializeAfter ()
	Clears the serializeAfter part of this instruction. More...

bool	isTempSerializeAfter ()
	Checks if this serializeAfter is only temporarily set. More...

void	setSerializeHandled ()
	Sets the serialization part of this instruction as handled. More...

bool	isSerializeHandled ()
	Checks if the serialization part of this instruction has been handled. More...

OpClass	opClass () const
	Returns the opclass of this instruction. More...

TheISA::PCState	branchTarget () const
	Returns the branch target address. More...

size_t	numSrcRegs () const
	Returns the number of source registers. More...

size_t	numDestRegs () const
	Returns the number of destination registers. More...

int8_t	numFPDestRegs () const

int8_t	numIntDestRegs () const

int8_t	numCCDestRegs () const

int8_t	numVecDestRegs () const

int8_t	numVecElemDestRegs () const

int8_t	numVecPredDestRegs () const

const RegId &	destRegIdx (int i) const
	Returns the logical register index of the i'th destination register. More...

const RegId &	srcRegIdx (int i) const
	Returns the logical register index of the i'th source register. More...

uint8_t	resultSize ()
	Return the size of the instResult queue. More...

InstResult	popResult (InstResult dflt=InstResult())
	Pops a result off the instResult queue. More...

void	setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
	Records an integer register being set to a value. More...

void	setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
	Records a CC register being set to a value. More...

void	setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
	Record a vector register being set to a value. More...

void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
	Records an fp register being set to an integer value. More...

void	setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
	Record a vector register being set to a value. More...

void	setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
	Record a vector register being set to a value. More...

void	markSrcRegReady ()
	Records that one of the source registers is ready. More...

void	markSrcRegReady (RegIndex src_idx)
	Marks a specific register as ready. More...

void	setCompleted ()
	Sets this instruction as completed. More...

bool	isCompleted () const
	Returns whether or not this instruction is completed. More...

void	setResultReady ()
	Marks the result as ready. More...

bool	isResultReady () const
	Returns whether or not the result is ready. More...

void	setCanIssue ()
	Sets this instruction as ready to issue. More...

bool	readyToIssue () const
	Returns whether or not this instruction is ready to issue. More...

void	clearCanIssue ()
	Clears this instruction being able to issue. More...

void	setIssued ()
	Sets this instruction as issued from the IQ. More...

bool	isIssued () const
	Returns whether or not this instruction has issued. More...

void	clearIssued ()
	Clears this instruction as being issued. More...

void	setExecuted ()
	Sets this instruction as executed. More...

bool	isExecuted () const
	Returns whether or not this instruction has executed. More...

void	setCanCommit ()
	Sets this instruction as ready to commit. More...

void	clearCanCommit ()
	Clears this instruction as being ready to commit. More...

bool	readyToCommit () const
	Returns whether or not this instruction is ready to commit. More...

void	setAtCommit ()

bool	isAtCommit ()

void	setCommitted ()
	Sets this instruction as committed. More...

bool	isCommitted () const
	Returns whether or not this instruction is committed. More...

void	setSquashed ()
	Sets this instruction as squashed. More...

bool	isSquashed () const
	Returns whether or not this instruction is squashed. More...

void	setInIQ ()
	Sets this instruction as a entry the IQ. More...

void	clearInIQ ()
	Sets this instruction as a entry the IQ. More...

bool	isInIQ () const
	Returns whether or not this instruction has issued. More...

void	setSquashedInIQ ()
	Sets this instruction as squashed in the IQ. More...

bool	isSquashedInIQ () const
	Returns whether or not this instruction is squashed in the IQ. More...

void	setInLSQ ()
	Sets this instruction as a entry the LSQ. More...

void	removeInLSQ ()
	Sets this instruction as a entry the LSQ. More...

bool	isInLSQ () const
	Returns whether or not this instruction is in the LSQ. More...

void	setSquashedInLSQ ()
	Sets this instruction as squashed in the LSQ. More...

bool	isSquashedInLSQ () const
	Returns whether or not this instruction is squashed in the LSQ. More...

void	setInROB ()
	Sets this instruction as a entry the ROB. More...

void	clearInROB ()
	Sets this instruction as a entry the ROB. More...

bool	isInROB () const
	Returns whether or not this instruction is in the ROB. More...

void	setSquashedInROB ()
	Sets this instruction as squashed in the ROB. More...

bool	isSquashedInROB () const
	Returns whether or not this instruction is squashed in the ROB. More...

bool	isPinnedRegsRenamed () const
	Returns whether pinned registers are renamed. More...

void	setPinnedRegsRenamed ()
	Sets the destination registers as renamed. More...

bool	isPinnedRegsWritten () const
	Returns whether destination registers are written. More...

void	setPinnedRegsWritten ()
	Sets destination registers as written. More...

bool	isPinnedRegsSquashDone () const
	Return whether dest registers' pinning status updated after squash. More...

void	setPinnedRegsSquashDone ()
	Sets dest registers' status updated after squash. More...

TheISA::PCState	pcState () const override
	Read the PC state of this instruction. More...

void	pcState (const TheISA::PCState &val) override
	Set the PC state of this instruction. More...

Addr	instAddr () const
	Read the PC of this instruction. More...

Addr	nextInstAddr () const
	Read the PC of the next instruction. More...

Addr	microPC () const
	Read the micro PC of this instruction. More...

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

void	setTid (ThreadID tid)
	Sets the thread id. More...

void	setThreadState (ImplState *state)
	Sets the pointer to the thread state. More...

ThreadContext *	tcBase () const override
	Returns the thread context. More...

bool	eaSrcsReady () const
	Returns whether or not the eff. More...

bool	strictlyOrdered () const
	Is this instruction's memory access strictly ordered? More...

void	strictlyOrdered (bool so)

bool	hasRequest () const
	Has this instruction generated a memory request. More...

void	setRequest ()
	Assert this instruction has generated a memory request. More...

ListIt &	getInstListIt ()
	Returns iterator to this instruction in the list of all insts. More...

void	setInstListIt (ListIt _instListIt)
	Sets iterator for this instruction in the list of all insts. More...

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...

void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures. More...

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override


template<typename T >
void	setScalarResult (T &&t)
	Pushes a result onto the instResult queue. More...

template<typename T >
void	setVecResult (T &&t)
	Full vector result. More...

template<typename T >
void	setVecElemResult (T &&t)
	Vector element result. More...

template<typename T >
void	setVecPredResult (T &&t)
	Predicate result. More...

Public Member Functions inherited from ExecContext
virtual RegVal	readIntRegOperand (const StaticInst *si, int idx)=0
	Reads an integer register. More...

virtual RegVal	readFloatRegOperandBits (const StaticInst *si, int idx)=0
	Reads a floating point register in its binary format, instead of by value. More...

virtual const TheISA::VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const =0
	Vector Register Interfaces. More...

virtual TheISA::VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx)=0
	Gets destination vector register operand for modification. More...

virtual ConstVecLane8	readVec8BitLaneOperand (const StaticInst *si, int idx) const =0
	Vector Register Lane Interfaces. More...

virtual ConstVecLane16	readVec16BitLaneOperand (const StaticInst *si, int idx) const =0
	Reads source vector 16bit operand. More...

virtual ConstVecLane32	readVec32BitLaneOperand (const StaticInst *si, int idx) const =0
	Reads source vector 32bit operand. More...

virtual ConstVecLane64	readVec64BitLaneOperand (const StaticInst *si, int idx) const =0
	Reads source vector 64bit operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val)=0
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val)=0

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val)=0

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val)=0

virtual TheISA::VecElem	readVecElemOperand (const StaticInst *si, int idx) const =0
	Vector Elem Interfaces. More...

virtual const TheISA::VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const =0
	Predicate registers interface. More...

virtual TheISA::VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx)=0
	Gets destination predicate register operand for modification. More...

virtual RegVal	readCCRegOperand (const StaticInst *si, int idx)=0

virtual RegVal	readMiscRegOperand (const StaticInst *si, int idx)=0

virtual void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val)=0

virtual RegVal	readMiscReg (int misc_reg)=0
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

virtual void	setMiscReg (int misc_reg, RegVal val)=0
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Perform an atomic memory read operation. More...

virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Initiate a timing memory read operation. More...

virtual Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable)=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

virtual Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

Public Member Functions inherited from RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...

void	incref () const
	Increment the reference count. More...

void	decref () const
	Decrement the reference count and destroy the object if all references are gone. More...

Public Attributes
InstSeqNum	seqNum
	The sequence number of the instruction. More...

const StaticInstPtr	staticInst
	The StaticInst used by this BaseDynInst. More...

ImplCPU *	cpu
	Pointer to the Impl's CPU object. More...

ImplState *	thread
	Pointer to the thread state. More...

Fault	fault
	The kind of fault this instruction has generated. More...

Trace::InstRecord *	traceData
	InstRecord that tracks this instructions. More...

Regs	regs

ThreadID	threadNumber
	The thread this instruction is from. More...

ListIt	instListIt
	Iterator pointing to this BaseDynInst in the list of all insts. More...

TheISA::PCState	predPC
	Predicted PC state after this instruction. More...

const StaticInstPtr	macroop
	The Macroop if one exists. More...

uint8_t	readyRegs
	How many source registers are ready. More...

Addr	effAddr
	The effective virtual address (lds & stores only). More...

Addr	physEffAddr
	The effective physical address. More...

unsigned	memReqFlags
	The memory request flags (from translation). More...

unsigned	effSize
	The size of the request. More...

uint8_t *	memData
	Pointer to the data for the memory access. More...

ssize_t	lqIdx
	Load queue index. More...

LQIterator	lqIt

ssize_t	sqIdx
	Store queue index. More...

SQIterator	sqIt

LSQRequestPtr	savedReq
	Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk). More...

RequestPtr	reqToVerify

Protected Types
enum	Status { IqEntry, RobEntry, LsqEntry, Completed, ResultReady, CanIssue, Issued, Executed, CanCommit, AtCommit, Committed, Squashed, SquashedInIQ, SquashedInLSQ, SquashedInROB, PinnedRegsRenamed, PinnedRegsWritten, PinnedRegsSquashDone, RecoverInst, BlockingInst, ThreadsyncWait, SerializeBefore, SerializeAfter, SerializeHandled, NumStatus }

enum	Flags { NotAnInst, TranslationStarted, TranslationCompleted, PossibleLoadViolation, HitExternalSnoop, EffAddrValid, RecordResult, Predicate, MemAccPredicate, PredTaken, IsStrictlyOrdered, ReqMade, MemOpDone, HtmFromTransaction, MaxFlags }

Protected Attributes
std::queue< InstResult >	instResult
	The result of the instruction; assumes an instruction can have many destination registers. More...

TheISA::PCState	pc
	PC state for this instruction. More...

Private Member Functions
void	initVars ()
	Function to initialize variables in the constructors. More...

Private Attributes
std::bitset< MaxFlags >	instFlags

std::bitset< NumStatus >	status
	The status of this BaseDynInst. More...

uint64_t	htmUid

uint64_t	htmDepth

Detailed Description

template<class Impl>
class BaseDynInst< Impl >

Definition at line 77 of file base_dyn_inst.hh.

Member Typedef Documentation

◆ BaseDynInstPtr

template<class Impl >

typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInst< Impl >::BaseDynInstPtr

Definition at line 90 of file base_dyn_inst.hh.

◆ DynInstPtr

template<class Impl >

typedef Impl::DynInstPtr BaseDynInst< Impl >::DynInstPtr

Definition at line 89 of file base_dyn_inst.hh.

◆ ImplCPU

template<class Impl >

typedef Impl::CPUType BaseDynInst< Impl >::ImplCPU

Definition at line 81 of file base_dyn_inst.hh.

◆ ImplState

template<class Impl >

typedef ImplCPU::ImplState BaseDynInst< Impl >::ImplState

Definition at line 82 of file base_dyn_inst.hh.

◆ ListIt

template<class Impl >

typedef std::list<DynInstPtr>::iterator BaseDynInst< Impl >::ListIt

Definition at line 93 of file base_dyn_inst.hh.

◆ LQIterator

template<class Impl >

using BaseDynInst< Impl >::LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator

Definition at line 85 of file base_dyn_inst.hh.

◆ LSQRequestPtr

template<class Impl >

using BaseDynInst< Impl >::LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*

Definition at line 84 of file base_dyn_inst.hh.

◆ SQIterator

template<class Impl >

using BaseDynInst< Impl >::SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator

Definition at line 86 of file base_dyn_inst.hh.

Member Enumeration Documentation

◆ Flags

template<class Impl >

enum BaseDynInst::Flags

protected

Enumerator
NotAnInst
TranslationStarted
TranslationCompleted
PossibleLoadViolation
HitExternalSnoop
EffAddrValid
RecordResult
Predicate
MemAccPredicate
PredTaken
IsStrictlyOrdered
ReqMade
MemOpDone
HtmFromTransaction
MaxFlags

Definition at line 125 of file base_dyn_inst.hh.

◆ Status

template<class Impl >

enum BaseDynInst::Status

protected

Enumerator
IqEntry
RobEntry	Instruction is in the IQ.
LsqEntry	Instruction is in the ROB.
Completed	Instruction is in the LSQ.
ResultReady	Instruction has completed.
CanIssue	Instruction has its result.
Issued	Instruction can issue and execute.
Executed	Instruction has issued.
CanCommit	Instruction has executed.
AtCommit	Instruction can commit.
Committed	Instruction has reached commit.
Squashed	Instruction has committed.
SquashedInIQ	Instruction is squashed.
SquashedInLSQ	Instruction is squashed in the IQ.
SquashedInROB	Instruction is squashed in the LSQ.
PinnedRegsRenamed	Instruction is squashed in the ROB.
PinnedRegsWritten	Pinned registers are renamed.
PinnedRegsSquashDone	Pinned registers are written back.
RecoverInst	Regs pinning status updated after squash.
BlockingInst	Is a recover instruction.
ThreadsyncWait	Is a blocking instruction.
SerializeBefore	Is a thread synchronization instruction.
SerializeAfter	Needs to serialize on instructions ahead of it.
SerializeHandled	Needs to serialize instructions behind it.
NumStatus	Serialization has been handled.

Definition at line 96 of file base_dyn_inst.hh.

Constructor & Destructor Documentation

◆ BaseDynInst() [1/2]

template<class Impl >

BaseDynInst< Impl >::BaseDynInst	(	const StaticInstPtr &	staticInst,
		const StaticInstPtr &	macroop,
		TheISA::PCState	pc,
		TheISA::PCState	predPC,
		InstSeqNum	seq_num,
		ImplCPU *	cpu
	)

BaseDynInst constructor given a binary instruction.

Parameters

staticInst	A StaticInstPtr to the underlying instruction.
pc	The PC state for the instruction.
predPC	The predicted next PC state for the instruction.
seq_num	The sequence number of the instruction.
cpu	Pointer to the instruction's CPU.

Definition at line 60 of file base_dyn_inst_impl.hh.

References BaseDynInst< Impl >::initVars(), BaseDynInst< Impl >::pc, BaseDynInst< Impl >::predPC, and BaseDynInst< Impl >::seqNum.

◆ BaseDynInst() [2/2]

template<class Impl >

BaseDynInst< Impl >::BaseDynInst	(	const StaticInstPtr &	staticInst,
		const StaticInstPtr &	macroop
	)

BaseDynInst constructor given a StaticInst pointer.

Parameters

_staticInst The StaticInst for this BaseDynInst.

Definition at line 82 of file base_dyn_inst_impl.hh.

References BaseDynInst< Impl >::initVars(), and BaseDynInst< Impl >::seqNum.

◆ ~BaseDynInst()

template<class Impl >

BaseDynInst< Impl >::~BaseDynInst

BaseDynInst destructor.

Definition at line 144 of file base_dyn_inst_impl.hh.

References DPRINTF, and NoFault.

Member Function Documentation

◆ armMonitor()

template<class Impl >

void BaseDynInst< Impl >::armMonitor ( Addr address )

inlineoverridevirtual

Implements ExecContext.

Definition at line 1113 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

◆ branchTarget()

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::branchTarget ( ) const

inline

Returns the branch target address.

Definition at line 732 of file base_dyn_inst.hh.

References StaticInst::branchTarget(), BaseDynInst< Impl >::pc, and BaseDynInst< Impl >::staticInst.

◆ clearCanCommit()

template<class Impl >

void BaseDynInst< Impl >::clearCanCommit ( )

inline

Clears this instruction as being ready to commit.

Definition at line 919 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanCommit, and BaseDynInst< Impl >::status.

◆ clearCanIssue()

template<class Impl >

void BaseDynInst< Impl >::clearCanIssue ( )

inline

Clears this instruction being able to issue.

Definition at line 898 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanIssue, and BaseDynInst< Impl >::status.

◆ clearHtmTransactionalState()

template<class Impl >

void BaseDynInst< Impl >::clearHtmTransactionalState ( )

inline

Definition at line 687 of file base_dyn_inst.hh.

References DPRINTF, BaseDynInst< Impl >::getHtmTransactionUid(), BaseDynInst< Impl >::htmDepth, BaseDynInst< Impl >::HtmFromTransaction, BaseDynInst< Impl >::htmUid, BaseDynInst< Impl >::inHtmTransactionalState(), and BaseDynInst< Impl >::instFlags.

◆ clearInIQ()

template<class Impl >

void BaseDynInst< Impl >::clearInIQ ( )

inline

Sets this instruction as a entry the IQ.

Definition at line 946 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::IqEntry, and BaseDynInst< Impl >::status.

◆ clearInROB()

template<class Impl >

void BaseDynInst< Impl >::clearInROB ( )

inline

Sets this instruction as a entry the ROB.

Definition at line 982 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::RobEntry, and BaseDynInst< Impl >::status.

◆ clearIssued()

template<class Impl >

void BaseDynInst< Impl >::clearIssued ( )

inline

Clears this instruction as being issued.

Definition at line 907 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Issued, and BaseDynInst< Impl >::status.

◆ clearSerializeAfter()

template<class Impl >

void BaseDynInst< Impl >::clearSerializeAfter ( )

inline

Clears the serializeAfter part of this instruction.

Definition at line 713 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeAfter, and BaseDynInst< Impl >::status.

◆ clearSerializeBefore()

template<class Impl >

void BaseDynInst< Impl >::clearSerializeBefore ( )

inline

Clears the serializeBefore part of this instruction.

Definition at line 704 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeBefore, and BaseDynInst< Impl >::status.

◆ contextId()

template<class Impl >

ContextID BaseDynInst< Impl >::contextId ( ) const

inline

Read this context's system-wide ID.

Definition at line 550 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

◆ cpuId()

template<class Impl >

int BaseDynInst< Impl >::cpuId ( ) const

inline

Read this CPU's ID.

Definition at line 541 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

◆ demapPage()

template<class Impl >

void BaseDynInst< Impl >::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 424 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and MipsISA::vaddr.

◆ destRegIdx()

template<class Impl >

const RegId& BaseDynInst< Impl >::destRegIdx ( int i ) const

inline

Returns the logical register index of the i'th destination register.

Definition at line 759 of file base_dyn_inst.hh.

References StaticInst::destRegIdx(), ArmISA::i, and BaseDynInst< Impl >::staticInst.

◆ doneTargCalc()

template<class Impl >

bool BaseDynInst< Impl >::doneTargCalc ( )

inline

Checks whether or not this instruction has had its branch target calculated yet.

For now it is not utilized and is hacked to be always false.

Todo:: : Actually use this instruction.

Definition at line 563 of file base_dyn_inst.hh.

◆ dump() [1/2]

template<class Impl >

void BaseDynInst< Impl >::dump

Dumps out contents of this BaseDynInst.

Definition at line 187 of file base_dyn_inst_impl.hh.

References cprintf(), and MipsISA::pc.

◆ dump() [2/2]

template<class Impl >

void BaseDynInst< Impl >::dump ( std::string & outstring )

Dumps out contents of this BaseDynInst into given string.

Definition at line 196 of file base_dyn_inst_impl.hh.

References MipsISA::pc, and ArmISA::s.

◆ eaSrcsReady()

template<class Impl >

bool BaseDynInst< Impl >::eaSrcsReady

Returns whether or not the eff.

addr. source registers are ready.

Definition at line 226 of file base_dyn_inst_impl.hh.

References ArmISA::i.

◆ effAddrValid() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::effAddrValid ( ) const

inline

Is the effective virtual address valid.

Definition at line 406 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::EffAddrValid, and BaseDynInst< Impl >::instFlags.

◆ effAddrValid() [2/2]

template<class Impl >

void BaseDynInst< Impl >::effAddrValid ( bool b )

inline

Definition at line 407 of file base_dyn_inst.hh.

References ArmISA::b, BaseDynInst< Impl >::EffAddrValid, and BaseDynInst< Impl >::instFlags.

◆ getAddrMonitor()

template<class Impl >

AddressMonitor* BaseDynInst< Impl >::getAddrMonitor ( )

inlineoverridevirtual

Implements ExecContext.

Definition at line 1128 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

◆ getCpuPtr()

template<class Impl >

BaseCPU* BaseDynInst< Impl >::getCpuPtr ( )

inline

Definition at line 153 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

◆ getFault() [1/2]

template<class Impl >

Fault& BaseDynInst< Impl >::getFault ( )

inline

TODO: This I added for the LSQRequest side to be able to modify the fault.

There should be a better mechanism in place.

Definition at line 556 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::fault.

◆ getFault() [2/2]

template<class Impl >

Fault BaseDynInst< Impl >::getFault ( ) const

inline

Returns the fault type.

Definition at line 553 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::fault.

◆ getHtmTransactionalDepth()

template<class Impl >

uint64_t BaseDynInst< Impl >::getHtmTransactionalDepth ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 670 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::htmDepth, and BaseDynInst< Impl >::inHtmTransactionalState().

◆ getHtmTransactionUid()

template<class Impl >

uint64_t BaseDynInst< Impl >::getHtmTransactionUid ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 650 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::HtmFromTransaction, BaseDynInst< Impl >::htmUid, and BaseDynInst< Impl >::instFlags.

Referenced by BaseDynInst< Impl >::clearHtmTransactionalState().

◆ getInstListIt()

template<class Impl >

ListIt& BaseDynInst< Impl >::getInstListIt ( )

inline

Returns iterator to this instruction in the list of all insts.

Definition at line 1090 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instListIt.

◆ hasRequest()

template<class Impl >

bool BaseDynInst< Impl >::hasRequest ( ) const

inline

Has this instruction generated a memory request.

Definition at line 1085 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::ReqMade.

◆ hitExternalSnoop() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::hitExternalSnoop ( ) const

inline

True if the address hit a external snoop while sitting in the LSQ.

If this is true and a older instruction sees it, this instruction must reexecute

Definition at line 469 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::HitExternalSnoop, and BaseDynInst< Impl >::instFlags.

◆ hitExternalSnoop() [2/2]

template<class Impl >

void BaseDynInst< Impl >::hitExternalSnoop ( bool f )

inline

Definition at line 470 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::HitExternalSnoop, and BaseDynInst< Impl >::instFlags.

◆ inHtmTransactionalState()

template<class Impl >

bool BaseDynInst< Impl >::inHtmTransactionalState ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 664 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::HtmFromTransaction, and BaseDynInst< Impl >::instFlags.

Referenced by BaseDynInst< Impl >::clearHtmTransactionalState(), and BaseDynInst< Impl >::getHtmTransactionalDepth().

◆ initiateHtmCmd()

template<class Impl >

Fault BaseDynInst< Impl >::initiateHtmCmd ( Request::Flags flags )

overridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements ExecContext.

Definition at line 1149 of file base_dyn_inst.hh.

◆ initiateMemAMO()

template<class Impl >

Fault BaseDynInst< Impl >::initiateMemAMO	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

override

Definition at line 1171 of file base_dyn_inst.hh.

References X86ISA::addr.

◆ initiateMemRead()

template<class Impl >

Fault BaseDynInst< Impl >::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

override

Definition at line 1136 of file base_dyn_inst.hh.

References X86ISA::addr.

◆ initVars()

template<class Impl >

void BaseDynInst< Impl >::initVars

private

Function to initialize variables in the constructors.

Definition at line 94 of file base_dyn_inst_impl.hh.

References DPRINTF, NoFault, and ArmISA::status.

Referenced by BaseDynInst< Impl >::BaseDynInst().

◆ instAddr()

template<class Impl >

Addr BaseDynInst< Impl >::instAddr ( ) const

inline

Read the PC of this instruction.

Definition at line 1035 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

◆ isAtCommit()

template<class Impl >

bool BaseDynInst< Impl >::isAtCommit ( )

inline

Definition at line 926 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::AtCommit, and BaseDynInst< Impl >::status.

◆ isAtomic()

template<class Impl >

bool BaseDynInst< Impl >::isAtomic ( ) const

inline

Definition at line 604 of file base_dyn_inst.hh.

References StaticInst::isAtomic(), and BaseDynInst< Impl >::staticInst.

◆ isCall()

template<class Impl >

bool BaseDynInst< Impl >::isCall ( ) const

inline

Definition at line 613 of file base_dyn_inst.hh.

References StaticInst::isCall(), and BaseDynInst< Impl >::staticInst.

◆ isCommitted()

template<class Impl >

bool BaseDynInst< Impl >::isCommitted ( ) const

inline

Returns whether or not this instruction is committed.

Definition at line 932 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Committed, and BaseDynInst< Impl >::status.

◆ isCompleted()

template<class Impl >

bool BaseDynInst< Impl >::isCompleted ( ) const

inline

Returns whether or not this instruction is completed.

Definition at line 883 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Completed, and BaseDynInst< Impl >::status.

◆ isCondCtrl()

template<class Impl >

bool BaseDynInst< Impl >::isCondCtrl ( ) const

inline

Definition at line 617 of file base_dyn_inst.hh.

References StaticInst::isCondCtrl(), and BaseDynInst< Impl >::staticInst.

◆ isControl()

template<class Impl >

bool BaseDynInst< Impl >::isControl ( ) const

inline

Definition at line 612 of file base_dyn_inst.hh.

References StaticInst::isControl(), and BaseDynInst< Impl >::staticInst.

◆ isDataPrefetch()

template<class Impl >

bool BaseDynInst< Impl >::isDataPrefetch ( ) const

inline

Definition at line 608 of file base_dyn_inst.hh.

References StaticInst::isDataPrefetch(), and BaseDynInst< Impl >::staticInst.

◆ isDelayedCommit()

template<class Impl >

bool BaseDynInst< Impl >::isDelayedCommit ( ) const

inline

Definition at line 640 of file base_dyn_inst.hh.

References StaticInst::isDelayedCommit(), and BaseDynInst< Impl >::staticInst.

◆ isDirectCtrl()

template<class Impl >

bool BaseDynInst< Impl >::isDirectCtrl ( ) const

inline

Definition at line 615 of file base_dyn_inst.hh.

References StaticInst::isDirectCtrl(), and BaseDynInst< Impl >::staticInst.

◆ isExecuted()

template<class Impl >

bool BaseDynInst< Impl >::isExecuted ( ) const

inline

Returns whether or not this instruction has executed.

Definition at line 913 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Executed, and BaseDynInst< Impl >::status.

◆ isFirstMicroop()

template<class Impl >

bool BaseDynInst< Impl >::isFirstMicroop ( ) const

inline

Definition at line 642 of file base_dyn_inst.hh.

References StaticInst::isFirstMicroop(), and BaseDynInst< Impl >::staticInst.

◆ isFloating()

template<class Impl >

bool BaseDynInst< Impl >::isFloating ( ) const

inline

Definition at line 610 of file base_dyn_inst.hh.

References StaticInst::isFloating(), and BaseDynInst< Impl >::staticInst.

◆ isFullMemBarrier()

template<class Impl >

bool BaseDynInst< Impl >::isFullMemBarrier ( ) const

inline

Definition at line 631 of file base_dyn_inst.hh.

References StaticInst::isFullMemBarrier(), and BaseDynInst< Impl >::staticInst.

◆ isHtmCancel()

template<class Impl >

bool BaseDynInst< Impl >::isHtmCancel ( ) const

inline

Definition at line 646 of file base_dyn_inst.hh.

References StaticInst::isHtmCancel(), and BaseDynInst< Impl >::staticInst.

◆ isHtmCmd()

template<class Impl >

bool BaseDynInst< Impl >::isHtmCmd ( ) const

inline

Definition at line 647 of file base_dyn_inst.hh.

References StaticInst::isHtmCmd(), and BaseDynInst< Impl >::staticInst.

◆ isHtmStart()

template<class Impl >

bool BaseDynInst< Impl >::isHtmStart ( ) const

inline

Definition at line 644 of file base_dyn_inst.hh.

References StaticInst::isHtmStart(), and BaseDynInst< Impl >::staticInst.

◆ isHtmStop()

template<class Impl >

bool BaseDynInst< Impl >::isHtmStop ( ) const

inline

Definition at line 645 of file base_dyn_inst.hh.

References StaticInst::isHtmStop(), and BaseDynInst< Impl >::staticInst.

◆ isIndirectCtrl()

template<class Impl >

bool BaseDynInst< Impl >::isIndirectCtrl ( ) const

inline

Definition at line 616 of file base_dyn_inst.hh.

References StaticInst::isIndirectCtrl(), and BaseDynInst< Impl >::staticInst.

◆ isInIQ()

template<class Impl >

bool BaseDynInst< Impl >::isInIQ ( ) const

inline

Returns whether or not this instruction has issued.

Definition at line 949 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::IqEntry, and BaseDynInst< Impl >::status.

◆ isInLSQ()

template<class Impl >

bool BaseDynInst< Impl >::isInLSQ ( ) const

inline

Returns whether or not this instruction is in the LSQ.

Definition at line 967 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::LsqEntry, and BaseDynInst< Impl >::status.

◆ isInROB()

template<class Impl >

bool BaseDynInst< Impl >::isInROB ( ) const

inline

Returns whether or not this instruction is in the ROB.

Definition at line 985 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::RobEntry, and BaseDynInst< Impl >::status.

◆ isInstPrefetch()

template<class Impl >

bool BaseDynInst< Impl >::isInstPrefetch ( ) const

inline

Definition at line 607 of file base_dyn_inst.hh.

References StaticInst::isInstPrefetch(), and BaseDynInst< Impl >::staticInst.

◆ isInteger()

template<class Impl >

bool BaseDynInst< Impl >::isInteger ( ) const

inline

Definition at line 609 of file base_dyn_inst.hh.

References StaticInst::isInteger(), and BaseDynInst< Impl >::staticInst.

◆ isIssued()

template<class Impl >

bool BaseDynInst< Impl >::isIssued ( ) const

inline

Returns whether or not this instruction has issued.

Definition at line 904 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Issued, and BaseDynInst< Impl >::status.

◆ isLastMicroop()

template<class Impl >

bool BaseDynInst< Impl >::isLastMicroop ( ) const

inline

Definition at line 641 of file base_dyn_inst.hh.

References StaticInst::isLastMicroop(), and BaseDynInst< Impl >::staticInst.

◆ isLoad()

template<class Impl >

bool BaseDynInst< Impl >::isLoad ( ) const

inline

Definition at line 602 of file base_dyn_inst.hh.

References StaticInst::isLoad(), and BaseDynInst< Impl >::staticInst.

◆ isMacroop()

template<class Impl >

bool BaseDynInst< Impl >::isMacroop ( ) const

inline

Definition at line 638 of file base_dyn_inst.hh.

References StaticInst::isMacroop(), and BaseDynInst< Impl >::staticInst.

◆ isMemRef()

template<class Impl >

bool BaseDynInst< Impl >::isMemRef ( ) const

inline

Definition at line 601 of file base_dyn_inst.hh.

References StaticInst::isMemRef(), and BaseDynInst< Impl >::staticInst.

◆ isMicroop()

template<class Impl >

bool BaseDynInst< Impl >::isMicroop ( ) const

inline

Definition at line 639 of file base_dyn_inst.hh.

References StaticInst::isMicroop(), and BaseDynInst< Impl >::staticInst.

◆ isNonSpeculative()

template<class Impl >

bool BaseDynInst< Impl >::isNonSpeculative ( ) const

inline

Definition at line 634 of file base_dyn_inst.hh.

References StaticInst::isNonSpeculative(), and BaseDynInst< Impl >::staticInst.

◆ isNop()

template<class Impl >

bool BaseDynInst< Impl >::isNop ( ) const

inline

Definition at line 600 of file base_dyn_inst.hh.

References StaticInst::isNop(), and BaseDynInst< Impl >::staticInst.

◆ isPinnedRegsRenamed()

template<class Impl >

bool BaseDynInst< Impl >::isPinnedRegsRenamed ( ) const

inline

Returns whether pinned registers are renamed.

Definition at line 994 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::PinnedRegsRenamed, and BaseDynInst< Impl >::status.

◆ isPinnedRegsSquashDone()

template<class Impl >

bool BaseDynInst< Impl >::isPinnedRegsSquashDone ( ) const

inline

Return whether dest registers' pinning status updated after squash.

Definition at line 1019 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::PinnedRegsSquashDone, and BaseDynInst< Impl >::status.

◆ isPinnedRegsWritten()

template<class Impl >

bool BaseDynInst< Impl >::isPinnedRegsWritten ( ) const

inline

Returns whether destination registers are written.

Definition at line 1006 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::PinnedRegsWritten, and BaseDynInst< Impl >::status.

◆ isQuiesce()

template<class Impl >

bool BaseDynInst< Impl >::isQuiesce ( ) const

inline

Definition at line 635 of file base_dyn_inst.hh.

References StaticInst::isQuiesce(), and BaseDynInst< Impl >::staticInst.

◆ isReadBarrier()

template<class Impl >

bool BaseDynInst< Impl >::isReadBarrier ( ) const

inline

Definition at line 632 of file base_dyn_inst.hh.

References StaticInst::isReadBarrier(), and BaseDynInst< Impl >::staticInst.

◆ isResultReady()

template<class Impl >

bool BaseDynInst< Impl >::isResultReady ( ) const

inline

Returns whether or not the result is ready.

Definition at line 889 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::ResultReady, and BaseDynInst< Impl >::status.

◆ isReturn()

template<class Impl >

bool BaseDynInst< Impl >::isReturn ( ) const

inline

Definition at line 614 of file base_dyn_inst.hh.

References StaticInst::isReturn(), and BaseDynInst< Impl >::staticInst.

◆ isSerializeAfter()

template<class Impl >

bool BaseDynInst< Impl >::isSerializeAfter ( ) const

inline

Definition at line 626 of file base_dyn_inst.hh.

References StaticInst::isSerializeAfter(), BaseDynInst< Impl >::SerializeAfter, BaseDynInst< Impl >::staticInst, and BaseDynInst< Impl >::status.

◆ isSerializeBefore()

template<class Impl >

bool BaseDynInst< Impl >::isSerializeBefore ( ) const

inline

Definition at line 621 of file base_dyn_inst.hh.

References StaticInst::isSerializeBefore(), BaseDynInst< Impl >::SerializeBefore, BaseDynInst< Impl >::staticInst, and BaseDynInst< Impl >::status.

◆ isSerializeHandled()

template<class Impl >

bool BaseDynInst< Impl >::isSerializeHandled ( )

inline

Checks if the serialization part of this instruction has been handled.

This does not apply to the temporary serializing state; it only applies to this instruction's own permanent serializing state.

Definition at line 726 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeHandled, and BaseDynInst< Impl >::status.

◆ isSerializing()

template<class Impl >

bool BaseDynInst< Impl >::isSerializing ( ) const

inline

Definition at line 619 of file base_dyn_inst.hh.

References StaticInst::isSerializing(), and BaseDynInst< Impl >::staticInst.

◆ isSquashAfter()

template<class Impl >

bool BaseDynInst< Impl >::isSquashAfter ( ) const

inline

Definition at line 630 of file base_dyn_inst.hh.

References StaticInst::isSquashAfter(), and BaseDynInst< Impl >::staticInst.

◆ isSquashed()

template<class Impl >

bool BaseDynInst< Impl >::isSquashed ( ) const

inline

Returns whether or not this instruction is squashed.

Definition at line 938 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Squashed, and BaseDynInst< Impl >::status.

◆ isSquashedInIQ()

template<class Impl >

bool BaseDynInst< Impl >::isSquashedInIQ ( ) const

inline

Returns whether or not this instruction is squashed in the IQ.

Definition at line 955 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInIQ, and BaseDynInst< Impl >::status.

◆ isSquashedInLSQ()

template<class Impl >

bool BaseDynInst< Impl >::isSquashedInLSQ ( ) const

inline

Returns whether or not this instruction is squashed in the LSQ.

Definition at line 973 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInLSQ, and BaseDynInst< Impl >::status.

◆ isSquashedInROB()

template<class Impl >

bool BaseDynInst< Impl >::isSquashedInROB ( ) const

inline

Returns whether or not this instruction is squashed in the ROB.

Definition at line 991 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInROB, and BaseDynInst< Impl >::status.

◆ isStore()

template<class Impl >

bool BaseDynInst< Impl >::isStore ( ) const

inline

Definition at line 603 of file base_dyn_inst.hh.

References StaticInst::isStore(), and BaseDynInst< Impl >::staticInst.

◆ isStoreConditional()

template<class Impl >

bool BaseDynInst< Impl >::isStoreConditional ( ) const

inline

Definition at line 605 of file base_dyn_inst.hh.

References StaticInst::isStoreConditional(), and BaseDynInst< Impl >::staticInst.

◆ isSyscall()

template<class Impl >

bool BaseDynInst< Impl >::isSyscall ( ) const

inline

Definition at line 637 of file base_dyn_inst.hh.

References StaticInst::isSyscall(), and BaseDynInst< Impl >::staticInst.

◆ isTempSerializeAfter()

template<class Impl >

bool BaseDynInst< Impl >::isTempSerializeAfter ( )

inline

Checks if this serializeAfter is only temporarily set.

Definition at line 716 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeAfter, and BaseDynInst< Impl >::status.

◆ isTempSerializeBefore()

template<class Impl >

bool BaseDynInst< Impl >::isTempSerializeBefore ( )

inline

Checks if this serializeBefore is only temporarily set.

Definition at line 707 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeBefore, and BaseDynInst< Impl >::status.

◆ isTranslationDelayed()

template<class Impl >

bool BaseDynInst< Impl >::isTranslationDelayed ( ) const

inline

Returns true if the DTB address translation is being delayed due to a hw page table walk.

Definition at line 477 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::translationCompleted(), and BaseDynInst< Impl >::translationStarted().

◆ isUncondCtrl()

template<class Impl >

bool BaseDynInst< Impl >::isUncondCtrl ( ) const

inline

Definition at line 618 of file base_dyn_inst.hh.

References StaticInst::isUncondCtrl(), and BaseDynInst< Impl >::staticInst.

◆ isUnverifiable()

template<class Impl >

bool BaseDynInst< Impl >::isUnverifiable ( ) const

inline

Definition at line 636 of file base_dyn_inst.hh.

References StaticInst::isUnverifiable(), and BaseDynInst< Impl >::staticInst.

◆ isVector()

template<class Impl >

bool BaseDynInst< Impl >::isVector ( ) const

inline

Definition at line 611 of file base_dyn_inst.hh.

References StaticInst::isVector(), and BaseDynInst< Impl >::staticInst.

◆ isWriteBarrier()

template<class Impl >

bool BaseDynInst< Impl >::isWriteBarrier ( ) const

inline

Definition at line 633 of file base_dyn_inst.hh.

References StaticInst::isWriteBarrier(), and BaseDynInst< Impl >::staticInst.

◆ markSrcRegReady() [1/2]

template<class Impl >

void BaseDynInst< Impl >::markSrcRegReady

Records that one of the source registers is ready.

Definition at line 207 of file base_dyn_inst_impl.hh.

References DPRINTF.

◆ markSrcRegReady() [2/2]

template<class Impl >

void BaseDynInst< Impl >::markSrcRegReady ( RegIndex src_idx )

Marks a specific register as ready.

Definition at line 218 of file base_dyn_inst_impl.hh.

◆ memOpDone() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::memOpDone ( ) const

inline

Whether or not the memory operation is done.

Definition at line 410 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::MemOpDone.

◆ memOpDone() [2/2]

template<class Impl >

void BaseDynInst< Impl >::memOpDone ( bool f )

inline

Definition at line 411 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::MemOpDone.

◆ microPC()

template<class Impl >

Addr BaseDynInst< Impl >::microPC ( ) const

inline

Read the micro PC of this instruction.

Definition at line 1041 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

◆ mispredicted()

template<class Impl >

bool BaseDynInst< Impl >::mispredicted ( )

inline

Returns whether the instruction mispredicted.

Definition at line 590 of file base_dyn_inst.hh.

References ArmISA::advancePC(), BaseDynInst< Impl >::pc, BaseDynInst< Impl >::predPC, and BaseDynInst< Impl >::staticInst.

◆ mwait()

template<class Impl >

bool BaseDynInst< Impl >::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements ExecContext.

Definition at line 1118 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

◆ mwaitAtomic()

template<class Impl >

void BaseDynInst< Impl >::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements ExecContext.

Definition at line 1123 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

◆ newHtmTransactionUid()

template<class Impl >

uint64_t BaseDynInst< Impl >::newHtmTransactionUid ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 657 of file base_dyn_inst.hh.

References panic.

◆ nextInstAddr()

template<class Impl >

Addr BaseDynInst< Impl >::nextInstAddr ( ) const

inline

Read the PC of the next instruction.

Definition at line 1038 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

◆ notAnInst()

template<class Impl >

bool BaseDynInst< Impl >::notAnInst ( ) const

inline

Definition at line 413 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::NotAnInst.

◆ numCCDestRegs()

template<class Impl >

int8_t BaseDynInst< Impl >::numCCDestRegs ( ) const

inline

Definition at line 745 of file base_dyn_inst.hh.

References StaticInst::numCCDestRegs(), and BaseDynInst< Impl >::staticInst.

◆ numDestRegs()

template<class Impl >

size_t BaseDynInst< Impl >::numDestRegs ( ) const

inline

Returns the number of destination registers.

Definition at line 739 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Regs::numDests(), and BaseDynInst< Impl >::regs.

Referenced by BaseO3DynInst< Impl >::forwardOldRegs().

◆ numFPDestRegs()

template<class Impl >

int8_t BaseDynInst< Impl >::numFPDestRegs ( ) const

inline

Definition at line 743 of file base_dyn_inst.hh.

References StaticInst::numFPDestRegs(), and BaseDynInst< Impl >::staticInst.

◆ numIntDestRegs()

template<class Impl >

int8_t BaseDynInst< Impl >::numIntDestRegs ( ) const

inline

Definition at line 744 of file base_dyn_inst.hh.

References StaticInst::numIntDestRegs(), and BaseDynInst< Impl >::staticInst.

◆ numSrcRegs()

template<class Impl >

size_t BaseDynInst< Impl >::numSrcRegs ( ) const

inline

Returns the number of source registers.

Definition at line 736 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Regs::numSrcs(), and BaseDynInst< Impl >::regs.

◆ numVecDestRegs()

template<class Impl >

int8_t BaseDynInst< Impl >::numVecDestRegs ( ) const

inline

Definition at line 746 of file base_dyn_inst.hh.

References StaticInst::numVecDestRegs(), and BaseDynInst< Impl >::staticInst.

◆ numVecElemDestRegs()

template<class Impl >

int8_t BaseDynInst< Impl >::numVecElemDestRegs ( ) const

inline

Definition at line 748 of file base_dyn_inst.hh.

References StaticInst::numVecElemDestRegs(), and BaseDynInst< Impl >::staticInst.

◆ numVecPredDestRegs()

template<class Impl >

int8_t BaseDynInst< Impl >::numVecPredDestRegs ( ) const

inline

Definition at line 753 of file base_dyn_inst.hh.

References StaticInst::numVecPredDestRegs(), and BaseDynInst< Impl >::staticInst.

◆ opClass()

template<class Impl >

OpClass BaseDynInst< Impl >::opClass ( ) const

inline

Returns the opclass of this instruction.

Definition at line 729 of file base_dyn_inst.hh.

References StaticInst::opClass(), and BaseDynInst< Impl >::staticInst.

◆ pcState() [1/2]

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::pcState ( ) const

inlineoverridevirtual

Read the PC state of this instruction.

Implements ExecContext.

Definition at line 1029 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

◆ pcState() [2/2]

template<class Impl >

void BaseDynInst< Impl >::pcState ( const TheISA::PCState & val )

inlineoverridevirtual

Set the PC state of this instruction.

Implements ExecContext.

Definition at line 1032 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc, and X86ISA::val.

◆ popResult()

template<class Impl >

InstResult BaseDynInst< Impl >::popResult ( InstResult dflt = InstResult() )

inline

Pops a result off the instResult queue.

If the result stack is empty, return the default value.

Definition at line 771 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instResult, and ArmISA::t.

◆ possibleLoadViolation() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::possibleLoadViolation ( ) const

inline

True if this address was found to match a previous load and they issued out of order.

If that happend, then it's only a problem if an incoming snoop invalidate modifies the line, in which case we need to squash. If nothing modified the line the order doesn't matter.

Definition at line 455 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PossibleLoadViolation.

◆ possibleLoadViolation() [2/2]

template<class Impl >

void BaseDynInst< Impl >::possibleLoadViolation ( bool f )

inline

Definition at line 460 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PossibleLoadViolation.

◆ predInstAddr()

template<class Impl >

Addr BaseDynInst< Impl >::predInstAddr ( )

inline

Returns the predicted PC immediately after the branch.

Definition at line 571 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

◆ predMicroPC()

template<class Impl >

Addr BaseDynInst< Impl >::predMicroPC ( )

inline

Returns the predicted micro PC after the branch.

Definition at line 577 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

◆ predNextInstAddr()

template<class Impl >

Addr BaseDynInst< Impl >::predNextInstAddr ( )

inline

Returns the predicted PC two instructions after the branch.

Definition at line 574 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

◆ readMemAccPredicate()

template<class Impl >

bool BaseDynInst< Impl >::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 1056 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::MemAccPredicate.

◆ readPredicate()

template<class Impl >

bool BaseDynInst< Impl >::readPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 1043 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::Predicate.

◆ readPredTaken()

template<class Impl >

bool BaseDynInst< Impl >::readPredTaken ( )

inline

Returns whether the instruction was predicted taken or not.

Definition at line 580 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PredTaken.

◆ readPredTarg()

template<class Impl >

const TheISA::PCState& BaseDynInst< Impl >::readPredTarg ( )

inline

Definition at line 568 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

◆ readStCondFailures()

template<class Impl >

unsigned int BaseDynInst< Impl >::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 1098 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

◆ readyToCommit()

template<class Impl >

bool BaseDynInst< Impl >::readyToCommit ( ) const

inline

Returns whether or not this instruction is ready to commit.

Definition at line 922 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanCommit, and BaseDynInst< Impl >::status.

◆ readyToIssue()

template<class Impl >

bool BaseDynInst< Impl >::readyToIssue ( ) const

inline

Returns whether or not this instruction is ready to issue.

Definition at line 895 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanIssue, and BaseDynInst< Impl >::status.

◆ recordResult()

template<class Impl >

void BaseDynInst< Impl >::recordResult ( bool f )

inline

Records changes to result?

Definition at line 403 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::RecordResult.

◆ removeInLSQ()

template<class Impl >

void BaseDynInst< Impl >::removeInLSQ ( )

inline

Sets this instruction as a entry the LSQ.

Definition at line 964 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::LsqEntry, and BaseDynInst< Impl >::status.

◆ renameDestReg()

template<class Impl >

void BaseDynInst< Impl >::renameDestReg	(	int	idx,
		PhysRegIdPtr	renamed_dest,
		PhysRegIdPtr	previous_rename
	)

inline

Renames a destination register to a physical register.

Also records the previous physical register that the logical register mapped to.

Definition at line 491 of file base_dyn_inst.hh.

References PhysRegId::isPinned(), BaseDynInst< Impl >::Regs::prevDestIdx(), BaseDynInst< Impl >::regs, BaseDynInst< Impl >::Regs::renamedDestIdx(), and BaseDynInst< Impl >::setPinnedRegsRenamed().

◆ renameSrcReg()

template<class Impl >

void BaseDynInst< Impl >::renameSrcReg	(	int	idx,
		PhysRegIdPtr	renamed_src
	)

inline

Renames a source logical register to the physical register which has/will produce that logical register's result.

Todo:: : add in whether or not the source register is ready.

Definition at line 505 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::regs, and BaseDynInst< Impl >::Regs::renamedSrcIdx().

◆ requestorId()

template<class Impl >

RequestorID BaseDynInst< Impl >::requestorId ( ) const

inline

Read this CPU's data requestor ID.

Definition at line 547 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

◆ resultSize()

template<class Impl >

uint8_t BaseDynInst< Impl >::resultSize ( )

inline

Return the size of the instResult queue.

Definition at line 765 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instResult.

◆ setAtCommit()

template<class Impl >

void BaseDynInst< Impl >::setAtCommit ( )

inline

Definition at line 924 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::AtCommit, and BaseDynInst< Impl >::status.

◆ setCanCommit()

template<class Impl >

void BaseDynInst< Impl >::setCanCommit ( )

inline

Sets this instruction as ready to commit.

Definition at line 916 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanCommit, and BaseDynInst< Impl >::status.

◆ setCanIssue()

template<class Impl >

void BaseDynInst< Impl >::setCanIssue ( )

inline

Sets this instruction as ready to issue.

Definition at line 892 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanIssue, and BaseDynInst< Impl >::status.

◆ setCCRegOperand()

template<class Impl >

void BaseDynInst< Impl >::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Records a CC register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 837 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::setScalarResult(), and X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setCCRegOperand().

◆ setCommitted()

template<class Impl >

void BaseDynInst< Impl >::setCommitted ( )

inline

Sets this instruction as committed.

Definition at line 929 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Committed, and BaseDynInst< Impl >::status.

◆ setCompleted()

template<class Impl >

void BaseDynInst< Impl >::setCompleted ( )

inline

Sets this instruction as completed.

Definition at line 880 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Completed, and BaseDynInst< Impl >::status.

◆ setExecuted()

template<class Impl >

void BaseDynInst< Impl >::setExecuted ( )

inline

Sets this instruction as executed.

Definition at line 910 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Executed, and BaseDynInst< Impl >::status.

◆ setFloatRegOperandBits()

template<class Impl >

void BaseDynInst< Impl >::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Records an fp register being set to an integer value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 852 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::setScalarResult(), and X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setFloatRegOperandBits().

◆ setHtmTransactionalState()

template<class Impl >

void BaseDynInst< Impl >::setHtmTransactionalState	(	uint64_t	htm_uid,
		uint64_t	htm_depth
	)

inline

Definition at line 679 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::htmDepth, BaseDynInst< Impl >::HtmFromTransaction, BaseDynInst< Impl >::htmUid, and BaseDynInst< Impl >::instFlags.

◆ setInIQ()

template<class Impl >

void BaseDynInst< Impl >::setInIQ ( )

inline

Sets this instruction as a entry the IQ.

Definition at line 943 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::IqEntry, and BaseDynInst< Impl >::status.

◆ setInLSQ()

template<class Impl >

void BaseDynInst< Impl >::setInLSQ ( )

inline

Sets this instruction as a entry the LSQ.

Definition at line 961 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::LsqEntry, and BaseDynInst< Impl >::status.

◆ setInROB()

template<class Impl >

void BaseDynInst< Impl >::setInROB ( )

inline

Sets this instruction as a entry the ROB.

Definition at line 979 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::RobEntry, and BaseDynInst< Impl >::status.

◆ setInstListIt()

template<class Impl >

void BaseDynInst< Impl >::setInstListIt ( ListIt _instListIt )

inline

Sets iterator for this instruction in the list of all insts.

Definition at line 1093 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instListIt.

◆ setIntRegOperand()

template<class Impl >

void BaseDynInst< Impl >::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Records an integer register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 830 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::setScalarResult(), and X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setIntRegOperand().

◆ setIssued()

template<class Impl >

void BaseDynInst< Impl >::setIssued ( )

inline

Sets this instruction as issued from the IQ.

Definition at line 901 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Issued, and BaseDynInst< Impl >::status.

◆ setMemAccPredicate()

template<class Impl >

void BaseDynInst< Impl >::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 1062 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::MemAccPredicate, and X86ISA::val.

◆ setNotAnInst()

template<class Impl >

void BaseDynInst< Impl >::setNotAnInst ( )

inline

Definition at line 414 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::NotAnInst.

◆ setPinnedRegsRenamed()

template<class Impl >

void BaseDynInst< Impl >::setPinnedRegsRenamed ( )

inline

Sets the destination registers as renamed.

Definition at line 998 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::PinnedRegsRenamed, BaseDynInst< Impl >::PinnedRegsSquashDone, BaseDynInst< Impl >::PinnedRegsWritten, and BaseDynInst< Impl >::status.

Referenced by BaseDynInst< Impl >::renameDestReg().

◆ setPinnedRegsSquashDone()

template<class Impl >

void BaseDynInst< Impl >::setPinnedRegsSquashDone ( )

inline

Sets dest registers' status updated after squash.

Definition at line 1023 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::PinnedRegsSquashDone, and BaseDynInst< Impl >::status.

◆ setPinnedRegsWritten()

template<class Impl >

void BaseDynInst< Impl >::setPinnedRegsWritten ( )

inline

Sets destination registers as written.

Definition at line 1010 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::PinnedRegsRenamed, BaseDynInst< Impl >::PinnedRegsSquashDone, BaseDynInst< Impl >::PinnedRegsWritten, and BaseDynInst< Impl >::status.

◆ setPredicate()

template<class Impl >

void BaseDynInst< Impl >::setPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 1046 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::Predicate, Trace::InstRecord::setPredicate(), BaseDynInst< Impl >::traceData, and X86ISA::val.

◆ setPredTaken()

template<class Impl >

void BaseDynInst< Impl >::setPredTaken ( bool predicted_taken )

inline

Definition at line 583 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PredTaken.

◆ setPredTarg()

template<class Impl >

void BaseDynInst< Impl >::setPredTarg ( const TheISA::PCState & _predPC )

inline

Set the predicted target of this current instruction.

Definition at line 566 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

◆ setRequest()

template<class Impl >

void BaseDynInst< Impl >::setRequest ( )

inline

Assert this instruction has generated a memory request.

Definition at line 1087 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::ReqMade.

◆ setResultReady()

template<class Impl >

void BaseDynInst< Impl >::setResultReady ( )

inline

Marks the result as ready.

Definition at line 886 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::ResultReady, and BaseDynInst< Impl >::status.

◆ setScalarResult()

template<class Impl >

template<typename T >

void BaseDynInst< Impl >::setScalarResult ( T && t )

inline

Pushes a result onto the instResult queue.

Scalar result.

Definition at line 786 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::instResult, BaseDynInst< Impl >::RecordResult, InstResult::Scalar, and ArmISA::t.

Referenced by BaseDynInst< Impl >::setCCRegOperand(), BaseDynInst< Impl >::setFloatRegOperandBits(), and BaseDynInst< Impl >::setIntRegOperand().

◆ setSerializeAfter()

template<class Impl >

void BaseDynInst< Impl >::setSerializeAfter ( )

inline

Temporarily sets this instruction as a serialize after instruction.

Definition at line 710 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeAfter, and BaseDynInst< Impl >::status.

◆ setSerializeBefore()

template<class Impl >

void BaseDynInst< Impl >::setSerializeBefore ( )

inline

Temporarily sets this instruction as a serialize before instruction.

Definition at line 701 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeBefore, and BaseDynInst< Impl >::status.

◆ setSerializeHandled()

template<class Impl >

void BaseDynInst< Impl >::setSerializeHandled ( )

inline

Sets the serialization part of this instruction as handled.

Definition at line 719 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeHandled, and BaseDynInst< Impl >::status.

◆ setSquashed()

template<class Impl >

void BaseDynInst< Impl >::setSquashed

Sets this instruction as squashed.

Definition at line 244 of file base_dyn_inst_impl.hh.

References PhysRegId::incrNumPinnedWrites(), PhysRegId::incrNumPinnedWritesToComplete(), PhysRegId::isPinned(), and ArmISA::status.

◆ setSquashedInIQ()

template<class Impl >

void BaseDynInst< Impl >::setSquashedInIQ ( )

inline

Sets this instruction as squashed in the IQ.

Definition at line 952 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Squashed, BaseDynInst< Impl >::SquashedInIQ, and BaseDynInst< Impl >::status.

◆ setSquashedInLSQ()

template<class Impl >

void BaseDynInst< Impl >::setSquashedInLSQ ( )

inline

Sets this instruction as squashed in the LSQ.

Definition at line 970 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Squashed, BaseDynInst< Impl >::SquashedInLSQ, and BaseDynInst< Impl >::status.

◆ setSquashedInROB()

template<class Impl >

void BaseDynInst< Impl >::setSquashedInROB ( )

inline

Sets this instruction as squashed in the ROB.

Definition at line 988 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInROB, and BaseDynInst< Impl >::status.

◆ setStCondFailures()

template<class Impl >

void BaseDynInst< Impl >::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 1105 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

◆ setThreadState()

template<class Impl >

void BaseDynInst< Impl >::setThreadState ( ImplState * state )

inline

Sets the pointer to the thread state.

Definition at line 1071 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

◆ setTid()

template<class Impl >

void BaseDynInst< Impl >::setTid ( ThreadID tid )

inline

Sets the thread id.

Definition at line 1068 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::threadNumber.

◆ setVecElemOperand()

template<class Impl >

void BaseDynInst< Impl >::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecElem	val
	)

inlineoverridevirtual

Record a vector register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 859 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::setVecElemResult(), and X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setVecElemOperand().

◆ setVecElemResult()

template<class Impl >

template<typename T >

void BaseDynInst< Impl >::setVecElemResult ( T && t )

inline

Vector element result.

Definition at line 808 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::instResult, BaseDynInst< Impl >::RecordResult, ArmISA::t, and InstResult::VecElem.

Referenced by BaseDynInst< Impl >::setVecElemOperand().

◆ setVecPredRegOperand()

template<class Impl >

void BaseDynInst< Impl >::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecPredRegContainer &	val
	)

inlineoverridevirtual

Record a vector register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 867 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::setVecPredResult(), and X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setVecPredRegOperand().

◆ setVecPredResult()

template<class Impl >

template<typename T >

void BaseDynInst< Impl >::setVecPredResult ( T && t )

inline

Predicate result.

Definition at line 819 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::instResult, BaseDynInst< Impl >::RecordResult, ArmISA::t, and InstResult::VecPredReg.

Referenced by BaseDynInst< Impl >::setVecPredRegOperand().

◆ setVecRegOperand()

template<class Impl >

void BaseDynInst< Impl >::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const TheISA::VecRegContainer &	val
	)

inlineoverridevirtual

Record a vector register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 844 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::setVecResult(), and X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setVecRegOperand().

◆ setVecResult()

template<class Impl >

template<typename T >

void BaseDynInst< Impl >::setVecResult ( T && t )

inline

Full vector result.

Definition at line 797 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::instResult, BaseDynInst< Impl >::RecordResult, ArmISA::t, and InstResult::VecReg.

Referenced by BaseDynInst< Impl >::setVecRegOperand().

◆ socketId()

template<class Impl >

uint32_t BaseDynInst< Impl >::socketId ( ) const

inline

Read this CPU's Socket ID.

Definition at line 544 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

◆ srcRegIdx()

template<class Impl >

const RegId& BaseDynInst< Impl >::srcRegIdx ( int i ) const

inline

Returns the logical register index of the i'th source register.

Definition at line 762 of file base_dyn_inst.hh.

References ArmISA::i, StaticInst::srcRegIdx(), and BaseDynInst< Impl >::staticInst.

◆ strictlyOrdered() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::strictlyOrdered ( ) const

inline

Is this instruction's memory access strictly ordered?

Definition at line 1081 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::IsStrictlyOrdered.

◆ strictlyOrdered() [2/2]

template<class Impl >

void BaseDynInst< Impl >::strictlyOrdered ( bool so )

inline

Definition at line 1082 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::IsStrictlyOrdered, and PowerISA::so.

◆ tcBase()

template<class Impl >

ThreadContext* BaseDynInst< Impl >::tcBase ( ) const

inlineoverridevirtual

Returns the thread context.

Implements ExecContext.

Definition at line 1074 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

◆ translationCompleted() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::translationCompleted ( ) const

inline

True if the DTB address translation has completed.

Definition at line 446 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationCompleted.

Referenced by BaseDynInst< Impl >::isTranslationDelayed().

◆ translationCompleted() [2/2]

template<class Impl >

void BaseDynInst< Impl >::translationCompleted ( bool f )

inline

Definition at line 447 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationCompleted.

◆ translationStarted() [1/2]

template<class Impl >

bool BaseDynInst< Impl >::translationStarted ( ) const

inline

True if the DTB address translation has started.

Definition at line 442 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationStarted.

Referenced by BaseDynInst< Impl >::isTranslationDelayed().

◆ translationStarted() [2/2]

template<class Impl >

void BaseDynInst< Impl >::translationStarted ( bool f )

inline

Definition at line 443 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationStarted.

◆ writeMem()

template<class Impl >

Fault BaseDynInst< Impl >::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable
	)

override

Definition at line 1158 of file base_dyn_inst.hh.

References X86ISA::addr, and data.

Member Data Documentation

◆ cpu

template<class Impl >

ImplCPU* BaseDynInst< Impl >::cpu

Pointer to the Impl's CPU object.

Definition at line 151 of file base_dyn_inst.hh.

◆ effAddr

template<class Impl >

Addr BaseDynInst< Impl >::effAddr

The effective virtual address (lds & stores only).

Definition at line 362 of file base_dyn_inst.hh.

◆ effSize

template<class Impl >

unsigned BaseDynInst< Impl >::effSize

The size of the request.

Definition at line 371 of file base_dyn_inst.hh.

◆ fault

template<class Impl >

Fault BaseDynInst< Impl >::fault

The kind of fault this instruction has generated.

Definition at line 159 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::getFault().

◆ htmDepth

template<class Impl >

uint64_t BaseDynInst< Impl >::htmDepth

private

Definition at line 399 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::clearHtmTransactionalState(), BaseDynInst< Impl >::getHtmTransactionalDepth(), and BaseDynInst< Impl >::setHtmTransactionalState().

◆ htmUid

template<class Impl >

uint64_t BaseDynInst< Impl >::htmUid

private

Definition at line 398 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::clearHtmTransactionalState(), BaseDynInst< Impl >::getHtmTransactionUid(), and BaseDynInst< Impl >::setHtmTransactionalState().

◆ instFlags

template<class Impl >

std::bitset<MaxFlags> BaseDynInst< Impl >::instFlags

private

Definition at line 175 of file base_dyn_inst.hh.

◆ instListIt

template<class Impl >

ListIt BaseDynInst< Impl >::instListIt

Iterator pointing to this BaseDynInst in the list of all insts.

Definition at line 347 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::getInstListIt(), and BaseDynInst< Impl >::setInstListIt().

◆ instResult

template<class Impl >

std::queue<InstResult> BaseDynInst< Impl >::instResult

protected

The result of the instruction; assumes an instruction can have many destination registers.

Definition at line 168 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::popResult(), BaseDynInst< Impl >::resultSize(), BaseDynInst< Impl >::setScalarResult(), BaseDynInst< Impl >::setVecElemResult(), BaseDynInst< Impl >::setVecPredResult(), and BaseDynInst< Impl >::setVecResult().

◆ lqIdx

template<class Impl >

ssize_t BaseDynInst< Impl >::lqIdx

Load queue index.

Definition at line 377 of file base_dyn_inst.hh.

◆ lqIt

template<class Impl >

LQIterator BaseDynInst< Impl >::lqIt

Definition at line 378 of file base_dyn_inst.hh.

◆ macroop

template<class Impl >

const StaticInstPtr BaseDynInst< Impl >::macroop

The Macroop if one exists.

Definition at line 354 of file base_dyn_inst.hh.

◆ memData

template<class Impl >

uint8_t* BaseDynInst< Impl >::memData

Pointer to the data for the memory access.

Definition at line 374 of file base_dyn_inst.hh.

◆ memReqFlags

template<class Impl >

unsigned BaseDynInst< Impl >::memReqFlags

The memory request flags (from translation).

Definition at line 368 of file base_dyn_inst.hh.

◆ pc

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::pc

protected

PC state for this instruction.

Definition at line 171 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::BaseDynInst(), BaseDynInst< Impl >::branchTarget(), BaseDynInst< Impl >::instAddr(), BaseDynInst< Impl >::microPC(), BaseDynInst< Impl >::mispredicted(), BaseDynInst< Impl >::nextInstAddr(), and BaseDynInst< Impl >::pcState().

◆ physEffAddr

template<class Impl >

Addr BaseDynInst< Impl >::physEffAddr

The effective physical address.

Definition at line 365 of file base_dyn_inst.hh.

◆ predPC

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::predPC

Predicted PC state after this instruction.

Definition at line 351 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::BaseDynInst(), BaseDynInst< Impl >::mispredicted(), BaseDynInst< Impl >::predInstAddr(), BaseDynInst< Impl >::predMicroPC(), BaseDynInst< Impl >::predNextInstAddr(), BaseDynInst< Impl >::readPredTarg(), and BaseDynInst< Impl >::setPredTarg().

◆ readyRegs

template<class Impl >

uint8_t BaseDynInst< Impl >::readyRegs

How many source registers are ready.

Definition at line 357 of file base_dyn_inst.hh.

◆ regs

template<class Impl >

Regs BaseDynInst< Impl >::regs

Definition at line 341 of file base_dyn_inst.hh.

◆ reqToVerify

template<class Impl >

RequestPtr BaseDynInst< Impl >::reqToVerify

Definition at line 394 of file base_dyn_inst.hh.

◆ savedReq

template<class Impl >

LSQRequestPtr BaseDynInst< Impl >::savedReq

Saved memory request (needed when the DTB address translation is delayed due to a hw page table walk).

Definition at line 390 of file base_dyn_inst.hh.

◆ seqNum

template<class Impl >

InstSeqNum BaseDynInst< Impl >::seqNum

The sequence number of the instruction.

Definition at line 145 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::BaseDynInst().

◆ sqIdx

template<class Impl >

ssize_t BaseDynInst< Impl >::sqIdx

Store queue index.

Definition at line 381 of file base_dyn_inst.hh.

◆ sqIt

template<class Impl >

SQIterator BaseDynInst< Impl >::sqIt

Definition at line 382 of file base_dyn_inst.hh.

◆ staticInst

template<class Impl >

const StaticInstPtr BaseDynInst< Impl >::staticInst

The StaticInst used by this BaseDynInst.

Definition at line 148 of file base_dyn_inst.hh.

◆ status

template<class Impl >

std::bitset<NumStatus> BaseDynInst< Impl >::status

private

The status of this BaseDynInst.

Several bits can be set.

Definition at line 178 of file base_dyn_inst.hh.

◆ thread

template<class Impl >

ImplState* BaseDynInst< Impl >::thread

Pointer to the thread state.

Definition at line 156 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::contextId(), BaseDynInst< Impl >::readStCondFailures(), BaseDynInst< Impl >::setStCondFailures(), BaseDynInst< Impl >::setThreadState(), BaseDynInst< Impl >::tcBase(), and BaseO3DynInst< Impl >::updateMiscRegs().

◆ threadNumber

template<class Impl >

ThreadID BaseDynInst< Impl >::threadNumber

The thread this instruction is from.

Definition at line 344 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::armMonitor(), BaseDynInst< Impl >::getAddrMonitor(), BaseDynInst< Impl >::mwait(), BaseDynInst< Impl >::mwaitAtomic(), BaseO3DynInst< Impl >::readMiscReg(), and BaseDynInst< Impl >::setTid().

◆ traceData

template<class Impl >

Trace::InstRecord* BaseDynInst< Impl >::traceData

InstRecord that tracks this instructions.

Definition at line 162 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::setPredicate().

The documentation for this class was generated from the following files:

cpu/base_dyn_inst.hh
cpu/base_dyn_inst_impl.hh

Classes

Public Types

Public Member Functions

Public Attributes

Protected Types

Protected Attributes

Private Member Functions

Private Attributes

Detailed Description

template<class Impl> class BaseDynInst< Impl >

Member Typedef Documentation

◆ BaseDynInstPtr

◆ DynInstPtr

◆ ImplCPU

◆ ImplState

◆ ListIt

◆ LQIterator

◆ LSQRequestPtr

◆ SQIterator

Member Enumeration Documentation

◆ Flags

◆ Status

Constructor & Destructor Documentation

◆ BaseDynInst() [1/2]

◆ BaseDynInst() [2/2]

◆ ~BaseDynInst()

Member Function Documentation

◆ armMonitor()

◆ branchTarget()

◆ clearCanCommit()

◆ clearCanIssue()

◆ clearHtmTransactionalState()

◆ clearInIQ()

◆ clearInROB()

◆ clearIssued()

◆ clearSerializeAfter()

◆ clearSerializeBefore()

◆ contextId()

◆ cpuId()

◆ demapPage()

◆ destRegIdx()

◆ doneTargCalc()

◆ dump() [1/2]

◆ dump() [2/2]

◆ eaSrcsReady()

◆ effAddrValid() [1/2]

◆ effAddrValid() [2/2]

◆ getAddrMonitor()

◆ getCpuPtr()

◆ getFault() [1/2]

◆ getFault() [2/2]

◆ getHtmTransactionalDepth()

◆ getHtmTransactionUid()

◆ getInstListIt()

◆ hasRequest()

◆ hitExternalSnoop() [1/2]

◆ hitExternalSnoop() [2/2]

◆ inHtmTransactionalState()

◆ initiateHtmCmd()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ initVars()

◆ instAddr()

◆ isAtCommit()

◆ isAtomic()

◆ isCall()

◆ isCommitted()

◆ isCompleted()

◆ isCondCtrl()

◆ isControl()

◆ isDataPrefetch()

◆ isDelayedCommit()

◆ isDirectCtrl()

◆ isExecuted()

◆ isFirstMicroop()

◆ isFloating()

◆ isFullMemBarrier()

◆ isHtmCancel()

◆ isHtmCmd()

◆ isHtmStart()

template<class Impl>
class BaseDynInst< Impl >