Classes
class	AddressErrorFault

class	AddressFault

class	BreakpointFault

class	CoprocessorUnusableFault

struct	CoreSpecific

class	Decoder

class	DspStateDisabledFault

class	EmuLinux

class	IntegerOverflowFault

class	InterruptFault

class	Interrupts

class	ISA

class	MachineCheckFault

class	MipsFault

class	MipsFaultBase

class	MMU

class	NonMaskableInterrupt

struct	PTE

class	RemoteGDB

class	ReservedInstructionFault

class	ResetFault

class	SEWorkload

class	SoftResetFault

class	StackTrace

class	SystemCallFault

class	ThreadFault

class	TLB

struct	TlbEntry

class	TlbFault

class	TlbInvalidFault

class	TlbModifiedFault

class	TlbRefillFault

class	TrapFault

Typedefs
typedef MipsFaultBase::FaultVals	FaultVals

typedef Addr	FaultVect

using	VecElem = ::DummyVecElem

using	VecReg = ::DummyVecReg

using	ConstVecReg = ::DummyConstVecReg

using	VecRegContainer = ::DummyVecRegContainer

using	VecPredReg = ::DummyVecPredReg

using	ConstVecPredReg = ::DummyConstVecPredReg

using	VecPredRegContainer = ::DummyVecPredRegContainer

typedef uint32_t	MachInst

typedef uint64_t	ExtMachInst

typedef GenericISA::DelaySlotPCState< MachInst >	PCState

Enumerations
enum	{ SIMD_FMT_L, SIMD_FMT_W, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_NUM_FMTS }

enum	{ DSP_POS, DSP_SCOUNT, DSP_C, DSP_OUFLAG, DSP_CCOND, DSP_EFI, DSP_NUM_FIELDS }

enum	{ CMP_EQ, CMP_LT, CMP_LE }

enum	{ MODE_L, MODE_R, MODE_LA, MODE_RA, MODE_X }

enum	{ UNSIGNED, SIGNED }

enum	{ NOSATURATE, SATURATE }

enum	{ NOROUND, ROUND }

enum	ExcCode { ExcCodeDummy = 0, ExcCodeInt = 0, ExcCodeMod = 1, ExcCodeTlbL = 2, ExcCodeTlbS = 3, ExcCodeAdEL = 4, ExcCodeAdES = 5, ExcCodeIBE = 6, ExcCodeDBE = 7, ExcCodeSys = 8, ExcCodeBp = 9, ExcCodeRI = 10, ExcCodeCpU = 11, ExcCodeOv = 12, ExcCodeTr = 13, ExcCodeC2E = 18, ExcCodeMDMX = 22, ExcCodeWatch = 23, ExcCodeMCheck = 24, ExcCodeThread = 25, ExcCodeCacheErr = 30 }

enum	InterruptLevels { INTLEVEL_SOFTWARE_MIN = 4, INTLEVEL_SOFTWARE_MAX = 19, INTLEVEL_EXTERNAL_MIN = 20, INTLEVEL_EXTERNAL_MAX = 34, INTLEVEL_IRQ0 = 20, INTLEVEL_IRQ1 = 21, INTINDEX_ETHERNET = 0, INTINDEX_SCSI = 1, INTLEVEL_IRQ2 = 22, INTLEVEL_IRQ3 = 23, INTLEVEL_SERIAL = 33, NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }

enum	FPControlRegNums { FLOATREG_FIR = NumFloatArchRegs, FLOATREG_FCCR, FLOATREG_FEXR, FLOATREG_FENR, FLOATREG_FCSR }

enum	FCSRBits { Inexact = 1, Underflow, Overflow, DivideByZero, Invalid, Unimplemented }

enum	FCSRFields { Flag_Field = 1, Enable_Field = 6, Cause_Field = 11 }

enum	MiscIntRegNums { INTREG_LO = NumIntArchRegs, INTREG_DSP_LO0 = INTREG_LO, INTREG_HI, INTREG_DSP_HI0 = INTREG_HI, INTREG_DSP_ACX0, INTREG_DSP_LO1, INTREG_DSP_HI1, INTREG_DSP_ACX1, INTREG_DSP_LO2, INTREG_DSP_HI2, INTREG_DSP_ACX2, INTREG_DSP_LO3, INTREG_DSP_HI3, INTREG_DSP_ACX3, INTREG_DSP_CONTROL }

enum	MiscRegIndex { MISCREG_INDEX = 0, MISCREG_MVP_CONTROL, MISCREG_MVP_CONF0, MISCREG_MVP_CONF1, MISCREG_CP0_RANDOM = 8, MISCREG_VPE_CONTROL, MISCREG_VPE_CONF0, MISCREG_VPE_CONF1, MISCREG_YQMASK, MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, MISCREG_VPE_OPT, MISCREG_ENTRYLO0 = 16, MISCREG_TC_STATUS, MISCREG_TC_BIND, MISCREG_TC_RESTART, MISCREG_TC_HALT, MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, MISCREG_TC_SCHEFBACK, MISCREG_ENTRYLO1 = 24, MISCREG_CONTEXT = 32, MISCREG_CONTEXT_CONFIG, MISCREG_PAGEMASK = 40, MISCREG_PAGEGRAIN = 41, MISCREG_WIRED = 48, MISCREG_SRS_CONF0, MISCREG_SRS_CONF1, MISCREG_SRS_CONF2, MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, MISCREG_HWRENA = 56, MISCREG_BADVADDR = 64, MISCREG_COUNT = 72, MISCREG_ENTRYHI = 80, MISCREG_COMPARE = 88, MISCREG_STATUS = 96, MISCREG_INTCTL, MISCREG_SRSCTL, MISCREG_SRSMAP, MISCREG_CAUSE = 104, MISCREG_EPC = 112, MISCREG_PRID = 120, MISCREG_EBASE, MISCREG_CONFIG = 128, MISCREG_CONFIG1, MISCREG_CONFIG2, MISCREG_CONFIG3, MISCREG_CONFIG4, MISCREG_CONFIG5, MISCREG_CONFIG6, MISCREG_CONFIG7, MISCREG_LLADDR = 136, MISCREG_WATCHLO0 = 144, MISCREG_WATCHLO1, MISCREG_WATCHLO2, MISCREG_WATCHLO3, MISCREG_WATCHLO4, MISCREG_WATCHLO5, MISCREG_WATCHLO6, MISCREG_WATCHLO7, MISCREG_WATCHHI0 = 152, MISCREG_WATCHHI1, MISCREG_WATCHHI2, MISCREG_WATCHHI3, MISCREG_WATCHHI4, MISCREG_WATCHHI5, MISCREG_WATCHHI6, MISCREG_WATCHHI7, MISCREG_XCCONTEXT64 = 160, MISCREG_DEBUG = 184, MISCREG_TRACE_CONTROL1, MISCREG_TRACE_CONTROL2, MISCREG_USER_TRACE_DATA, MISCREG_TRACE_BPC, MISCREG_DEPC = 192, MISCREG_PERFCNT0 = 200, MISCREG_PERFCNT1, MISCREG_PERFCNT2, MISCREG_PERFCNT3, MISCREG_PERFCNT4, MISCREG_PERFCNT5, MISCREG_PERFCNT6, MISCREG_PERFCNT7, MISCREG_ERRCTL = 208, MISCREG_CACHEERR0 = 216, MISCREG_CACHEERR1, MISCREG_CACHEERR2, MISCREG_CACHEERR3, MISCREG_TAGLO0 = 224, MISCREG_DATALO1, MISCREG_TAGLO2, MISCREG_DATALO3, MISCREG_TAGLO4, MISCREG_DATALO5, MISCREG_TAGLO6, MISCREG_DATALO7, MISCREG_TAGHI0 = 232, MISCREG_DATAHI1, MISCREG_TAGHI2, MISCREG_DATAHI3, MISCREG_TAGHI4, MISCREG_DATAHI5, MISCREG_TAGHI6, MISCREG_DATAHI7, MISCREG_ERROR_EPC = 240, MISCREG_DESAVE = 248, MISCREG_LLFLAG = 257, MISCREG_TP_VALUE, MISCREG_NUMREGS }

enum	ConvertType { SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE, DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE, LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE, WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE }

enum	RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }

Functions
int32_t	bitrev (int32_t value)

uint64_t	dspSaturate (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)

uint64_t	checkOverflow (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)

uint64_t	signExtend (uint64_t value, int32_t signpos)

uint64_t	addHalfLsb (uint64_t value, int32_t lsbpos)

int32_t	dspAbs (int32_t a, int32_t fmt, uint32_t *dspctl)

int32_t	dspAdd (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)

int32_t	dspAddh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)

int32_t	dspSub (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)

int32_t	dspSubh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)

int32_t	dspShll (int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)

int32_t	dspShrl (int32_t a, uint32_t sa, int32_t fmt, int32_t sign)

int32_t	dspShra (int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)

int32_t	dspMul (int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)

int32_t	dspMulq (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)

int32_t	dspMuleu (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)

int32_t	dspMuleq (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)

int64_t	dspDpaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)

int64_t	dspDpsq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)

int64_t	dspDpa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)

int64_t	dspDps (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)

int64_t	dspMaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)

int64_t	dspMulsa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)

int64_t	dspMulsaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)

void	dspCmp (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)

int32_t	dspCmpg (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)

int32_t	dspCmpgd (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)

int32_t	dspPrece (int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)

int32_t	dspPrecrqu (int32_t a, int32_t b, uint32_t *dspctl)

int32_t	dspPrecrq (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)

int32_t	dspPrecrSra (int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)

int32_t	dspPick (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)

int32_t	dspPack (int32_t a, int32_t b, int32_t fmt)

int32_t	dspExtr (int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)

int32_t	dspExtp (int64_t dspac, int32_t size, uint32_t *dspctl)

int32_t	dspExtpd (int64_t dspac, int32_t size, uint32_t *dspctl)

void	simdPack (uint64_t values_ptr, int32_t reg, int32_t fmt)

void	simdUnpack (int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)

void	writeDSPControl (uint32_t *dspctl, uint32_t value, uint32_t mask)

uint32_t	readDSPControl (uint32_t *dspctl, uint32_t mask)

	BitUnion32 (DebugReg) Bitfield< 31 > dbd

	SubBitUnion (ejtagVer, 17, 15) Bitfield< 17 > ejtagVer2

	EndSubBitUnion (ejtagVer) Bitfield< 14

	EndBitUnion (DebugReg) BitUnion32(TraceControlReg) Bitfield< 31 > ts

	EndBitUnion (TraceControlReg) BitUnion32(TraceControl2Reg) Bitfield< 29 > cpuidv

	EndBitUnion (TraceControl2Reg) BitUnion32(TraceBPCReg) Bitfield< 31 > mb

	EndBitUnion (TraceBPCReg) BitUnion32(TraceBPC2Reg) Bitfield< 17

	EndBitUnion (TraceBPC2Reg) BitUnion32(Debug2Reg) Bitfield< 3 > prm

static uint8_t	getCauseIP (ThreadContext *tc)

static void	setCauseIP (ThreadContext *tc, uint8_t val)

static SyscallReturn	unameFunc (SyscallDesc desc, ThreadContext tc, VPtr< Linux::utsname > name)
	Target uname() handler. More...

static SyscallReturn	sys_getsysinfoFunc (SyscallDesc desc, ThreadContext tc, unsigned op, unsigned bufPtr, unsigned nbytes)
	Target sys_getsysyinfo() handler. More...

static SyscallReturn	sys_setsysinfoFunc (SyscallDesc desc, ThreadContext tc, unsigned op, VPtr<> bufPtr, unsigned nbytes)
	Target sys_setsysinfo() handler. More...

static SyscallReturn	setThreadAreaFunc (SyscallDesc desc, ThreadContext tc, VPtr<> addr)

template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)

template<class XC >
void	handleLockedRead (XC *xc, const RequestPtr &req)

template<class XC >
void	handleLockedSnoopHit (XC *xc)

template<class XC >
bool	handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)

template<class XC >
void	globalClearExclusive (XC *xc)

static RegVal	readRegOtherThread (ThreadContext *tc, const RegId &reg, ThreadID tid=InvalidThreadID)

static void	setRegOtherThread (ThreadContext *tc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)

static RegVal	readRegOtherThread (ExecContext *xc, const RegId &reg, ThreadID tid=InvalidThreadID)

static void	setRegOtherThread (ExecContext *xc, const RegId &reg, RegVal val, ThreadID tid=InvalidThreadID)

template<class TC >
unsigned	getVirtProcNum (TC *tc)

template<class TC >
unsigned	getTargetThread (TC *tc)

template<class TC >
void	haltThread (TC *tc)

template<class TC >
void	restoreThread (TC *tc)

template<class TC >
void	forkThread (TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)

template<class TC >
int	yieldThread (TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)

template<class TC >
void	updateStatusView (TC *tc)

template<class TC >
void	updateTCStatusView (TC *tc)

	BitUnion32 (MVPControlReg) Bitfield< 3 > cpa

	EndBitUnion (MVPControlReg) BitUnion32(MVPConf0Reg) Bitfield< 31 > m

	EndBitUnion (MVPConf0Reg) BitUnion32(VPEControlReg) Bitfield< 21 > ysi

	EndBitUnion (VPEControlReg) BitUnion32(VPEConf0Reg) Bitfield< 31 > m

	EndBitUnion (VPEConf0Reg) BitUnion32(TCBindReg) Bitfield< 28

	EndBitUnion (TCBindReg) BitUnion32(TCStatusReg) Bitfield< 31

	EndBitUnion (TCStatusReg) BitUnion32(TCHaltReg) Bitfield< 0 > h

	BitUnion32 (IndexReg) Bitfield< 31 > p

	EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30

	EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63

	EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63

	EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28

	EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31

	EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30

	EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31

	EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63

	EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu

	EndSubBitUnion (cu) Bitfield< 27 > rp

	SubBitUnion (im, 15, 8) Bitfield< 15 > im7

	EndSubBitUnion (im) Bitfield< 7 > kx

	EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31

	EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29

	EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31

	EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd

	SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7

	EndSubBitUnion (ip)

	EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31

	EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29

	EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m

	EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m

	EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m

	EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m

	EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63

	EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m

	EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m

	EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er

	EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31

uint64_t	fpConvert (ConvertType cvt_type, double fp_val)

double	roundFP (double val, int digits)

double	truncFP (double val)

bool	getCondCode (uint32_t fcsr, int cc_idx)

uint32_t	genCCVector (uint32_t fcsr, int cc_num, uint32_t cc_val)

uint32_t	genInvalidVector (uint32_t fcsr_bits)

bool	isNan (void *val_ptr, int size)

bool	isQnan (void *val_ptr, int size)

bool	isSnan (void *val_ptr, int size)

void	copyRegs (ThreadContext src, ThreadContext dest)

void	copyMiscRegs (ThreadContext src, ThreadContext dest)

PCState	buildRetPC (const PCState &curPC, const PCState &callPC)

Addr	TruncPage (Addr addr)

Addr	RoundPage (Addr addr)

void	advancePC (PCState &pc, const StaticInstPtr &inst)

Variables
const uint32_t	DSP_CTL_POS [DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }

const uint32_t	DSP_CTL_MASK [DSP_NUM_FIELDS]

const uint32_t	SIMD_MAX_VALS = 4

const uint32_t	SIMD_NVALS [SIMD_NUM_FMTS] = { 1, 1, 2, 4 }

const uint32_t	SIMD_NBITS [SIMD_NUM_FMTS] = { 64, 32, 16, 8 }

const uint32_t	SIMD_LOG2N [SIMD_NUM_FMTS] = { 6, 5, 4, 3 }

const uint64_t	FIXED_L_SMAX = ULL(0x7fffffffffffffff)

const uint64_t	FIXED_W_SMAX = ULL(0x000000007fffffff)

const uint64_t	FIXED_H_SMAX = ULL(0x0000000000007fff)

const uint64_t	FIXED_B_SMAX = ULL(0x000000000000007f)

const uint64_t	FIXED_L_UMAX = ULL(0xffffffffffffffff)

const uint64_t	FIXED_W_UMAX = ULL(0x00000000ffffffff)

const uint64_t	FIXED_H_UMAX = ULL(0x000000000000ffff)

const uint64_t	FIXED_B_UMAX = ULL(0x00000000000000ff)

const uint64_t	FIXED_SMAX [SIMD_NUM_FMTS]

const uint64_t	FIXED_UMAX [SIMD_NUM_FMTS]

const uint64_t	FIXED_L_SMIN = ULL(0x8000000000000000)

const uint64_t	FIXED_W_SMIN = ULL(0xffffffff80000000)

const uint64_t	FIXED_H_SMIN = ULL(0xffffffffffff8000)

const uint64_t	FIXED_B_SMIN = ULL(0xffffffffffffff80)

const uint64_t	FIXED_L_UMIN = ULL(0x0000000000000000)

const uint64_t	FIXED_W_UMIN = ULL(0x0000000000000000)

const uint64_t	FIXED_H_UMIN = ULL(0x0000000000000000)

const uint64_t	FIXED_B_UMIN = ULL(0x0000000000000000)

const uint64_t	FIXED_SMIN [SIMD_NUM_FMTS]

const uint64_t	FIXED_UMIN [SIMD_NUM_FMTS]

Bitfield< 30 >	dm

Bitfield< 29 >	nodcr

Bitfield< 28 >	lsnm

Bitfield< 27 >	doze

Bitfield< 26 >	halt

Bitfield< 25 >	conutdm

Bitfield< 24 >	ibusep

Bitfield< 23 >	mcheckep

Bitfield< 22 >	cacheep

Bitfield< 21 >	dbusep

Bitfield< 20, 19 >	iexi

Bitfield< 19 >	ddbsImpr

Bitfield< 18 >	ddblImpr

Bitfield< 16 >	ejtagVer1

Bitfield< 15 >	ejtagVer0

	dexcCode

Bitfield< 9 >	nosst

Bitfield< 8 >	sst

Bitfield< 7 >	offline

Bitfield< 6 >	dibimpr

Bitfield< 5 >	dint

Bitfield< 4 >	dib

Bitfield< 3 >	ddbs

Bitfield< 2 >	ddbl

Bitfield< 1 >	dbp

Bitfield< 0 >	dss

Bitfield< 30 >	ut

Bitfield< 27 >	tb

Bitfield< 26 >	io

Bitfield< 25 >	d

Bitfield< 24 >	e

Bitfield< 23 >	k

Bitfield< 22 >	s

Bitfield< 21 >	u

Bitfield< 20, 13 >	asidM

Bitfield< 12, 5 >	asid

Bitfield< 4 >	g

Bitfield< 3 >	tfcr

Bitfield< 2 >	tlsm

Bitfield< 1 >	tim

Bitfield< 0 >	on

Bitfield< 28, 21 >	cpuid

Bitfield< 20 >	tcv

Bitfield< 19, 12 >	tcnum

Bitfield< 11, 7 >	mode

Bitfield< 6, 5 >	validModes

Bitfield< 4 >	tbi

Bitfield< 3 >	tbu

Bitfield< 2, 0 >	syp

Bitfield< 27 >	ate

Bitfield< 26, 24 >	bpc8

Bitfield< 23, 21 >	bpc7

Bitfield< 20, 18 >	bpc6

Bitfield< 17, 15 >	bpc5

Bitfield< 14, 12 >	bpc4

Bitfield< 11, 9 >	bpc3

Bitfield< 8, 6 >	bpc2

Bitfield< 5, 3 >	bpc1

Bitfield< 2, 0 >	bpc0

	bpc14

Bitfield< 14, 12 >	bpc13

Bitfield< 11, 9 >	bpc12

Bitfield< 8, 6 >	bpc11

Bitfield< 5, 3 >	bpc10

Bitfield< 2, 0 >	bpc9

Bitfield< 2 >	dq

Bitfield< 1 >	tup

Bitfield< 0 >	paco

const ByteOrder	GuestByteOrder = ByteOrder::little

const Addr	PageShift = 13

const Addr	PageBytes = ULL(1) << PageShift

Bitfield< 2 >	stlb

Bitfield< 1 >	vpc

Bitfield< 0 >	evp

Bitfield< 29 >	tlbs

Bitfield< 28 >	gs

Bitfield< 27 >	pcp

Bitfield< 25, 16 >	ptlbe

Bitfield< 15 >	tca

Bitfield< 13, 10 >	pvpe

Bitfield< 7, 0 >	ptc

Bitfield< 18, 16 >	excpt

Bitfield< 15 >	te

Bitfield< 7, 0 >	targTC

Bitfield< 28, 21 >	xtc

Bitfield< 19 >	tcs

Bitfield< 18 >	scs

Bitfield< 17 >	dcs

Bitfield< 16 >	ics

Bitfield< 1 >	mvp

Bitfield< 0 >	vpa

	curTC

Bitfield< 20, 18 >	a0

Bitfield< 17 >	tbe

Bitfield< 3, 0 >	curVPE

	tcu

Bitfield< 27 >	tmx

Bitfield< 24, 23 >	rnst

Bitfield< 21 >	tds

Bitfield< 20 >	dt

Bitfield< 19, 16 >	impl

Bitfield< 15 >	da

Bitfield< 13 >	a

Bitfield< 12, 11 >	tksu

Bitfield< 10 >	ixmt

Bitfield< 30, 0 >	index

	random

	fill

Bitfield< 29, 6 >	pfn

Bitfield< 5, 3 >	c

Bitfield< 1 >	v

	pteBase

Bitfield< 22, 4 >	badVPN2

	mask

Bitfield< 12, 11 >	maskx

	aseUp

Bitfield< 29 >	elpa

Bitfield< 28 >	esp

Bitfield< 12, 8 >	aseDn

	wired

	r

Bitfield< 39, 13 >	vpn2

Bitfield< 12, 11 >	vpn2x

Bitfield< 31 >	cu3

Bitfield< 30 >	cu2

Bitfield< 29 >	cu1

Bitfield< 28 >	cu0

Bitfield< 26 >	fr

Bitfield< 25 >	re

Bitfield< 24 >	mx

Bitfield< 23 >	px

Bitfield< 22 >	bev

Bitfield< 21 >	ts

Bitfield< 20 >	sr

Bitfield< 19 >	nmi

Bitfield< 15, 10 >	ipl

Bitfield< 14 >	im6

Bitfield< 13 >	im5

Bitfield< 12 >	im4

Bitfield< 11 >	im3

Bitfield< 10 >	im2

Bitfield< 9 >	im1

Bitfield< 8 >	im0

Bitfield< 6 >	sx

Bitfield< 5 >	ux

Bitfield< 4, 3 >	ksu

Bitfield< 4 >	um

Bitfield< 3 >	r0

Bitfield< 2 >	erl

Bitfield< 1 >	exl

Bitfield< 0 >	ie

	ipti

Bitfield< 28, 26 >	ippci

Bitfield< 9, 5 >	vs

	hss

Bitfield< 21, 18 >	eicss

Bitfield< 15, 12 >	ess

Bitfield< 9, 6 >	pss

Bitfield< 3, 0 >	css

	ssv7

Bitfield< 27, 24 >	ssv6

Bitfield< 23, 20 >	ssv5

Bitfield< 19, 16 >	ssv4

Bitfield< 15, 12 >	ssv3

Bitfield< 11, 8 >	ssv2

Bitfield< 7, 4 >	ssv1

Bitfield< 3, 0 >	ssv0

Bitfield< 30 >	ti

Bitfield< 29, 28 >	ce

Bitfield< 27 >	dc

Bitfield< 26 >	pci

Bitfield< 23 >	iv

Bitfield< 22 >	wp

Bitfield< 15, 10 >	ripl

Bitfield< 14 >	ip6

Bitfield< 13 >	ip5

Bitfield< 12 >	ip4

Bitfield< 11 >	ip3

Bitfield< 10 >	ip2

Bitfield< 9 >	ip1

Bitfield< 8 >	ip0

Bitfield< 6, 2 >	excCode

	coOp

Bitfield< 23, 16 >	coId

Bitfield< 15, 8 >	procId

Bitfield< 7, 0 >	rev

	exceptionBase

Bitfield< 9, 9 >	cpuNum

Bitfield< 30, 28 >	k23

Bitfield< 27, 25 >	ku

Bitfield< 15 >	be

Bitfield< 14, 13 >	at

Bitfield< 12, 10 >	ar

Bitfield< 9, 7 >	mt

Bitfield< 3 >	vi

Bitfield< 2, 0 >	k0

Bitfield< 30, 25 >	mmuSize

Bitfield< 24, 22 >	is

Bitfield< 21, 19 >	il

Bitfield< 18, 16 >	ia

Bitfield< 15, 13 >	ds

Bitfield< 12, 10 >	dl

Bitfield< 6 >	c2

Bitfield< 5 >	md

Bitfield< 4 >	pc

Bitfield< 3 >	wr

Bitfield< 2 >	ca

Bitfield< 1 >	ep

Bitfield< 0 >	fp

Bitfield< 30, 28 >	tu

Bitfield< 23, 20 >	tl

Bitfield< 19, 16 >	ta

Bitfield< 15, 12 >	su

Bitfield< 11, 8 >	ss

Bitfield< 7, 4 >	sl

Bitfield< 3, 0 >	sa

Bitfield< 10 >	dspp

Bitfield< 7 >	lpa

Bitfield< 6 >	veic

Bitfield< 5 >	vint

Bitfield< 4 >	sp

Bitfield< 1 >	sm

	vaddr

Bitfield< 2 >	i

Bitfield< 0 >	w

Bitfield< 10, 5 >	event

Bitfield< 30 >	ec

Bitfield< 29 >	ed

Bitfield< 28 >	et

Bitfield< 27 >	es

Bitfield< 26 >	ee

Bitfield< 25 >	eb

	pTagLo

Bitfield< 7, 6 >	pState

Bitfield< 5 >	l

Bitfield< 0 >	p

const int	NumIntArchRegs = 32

const int	NumIntSpecialRegs = 9

const int	NumFloatArchRegs = 32

const int	NumFloatSpecialRegs = 5

const int	MaxShadowRegSets = 16

const int	NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

const int	NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

const int	NumVecRegs = 1

const int	NumVecPredRegs = 1

const int	NumCCRegs = 0

const uint32_t	MIPS32_QNAN = 0x7fbfffff

const uint64_t	MIPS64_QNAN = ULL(0x7ff7ffffffffffff)

const int	ZeroReg = 0

const int	SyscallSuccessReg = 7

const int	FirstArgumentReg = 4

const int	ReturnValueReg = 2

const int	StackPointerReg = 29

const int	SyscallPseudoReturnReg = 3

const int	NumMiscRegs = MISCREG_NUMREGS

constexpr unsigned	NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

constexpr size_t	VecRegSizeBytes = ::DummyVecRegSizeBytes

constexpr size_t	VecPredRegSizeBits = ::DummyVecPredRegSizeBits

constexpr bool	VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

Typedef Documentation

◆ ConstVecPredReg

using MipsISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 281 of file registers.hh.

◆ ConstVecReg

using MipsISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 274 of file registers.hh.

◆ ExtMachInst

typedef uint64_t MipsISA::ExtMachInst

Definition at line 39 of file types.hh.

◆ FaultVals

typedef MipsFaultBase::FaultVals MipsISA::FaultVals

Definition at line 43 of file faults.cc.

◆ FaultVect

typedef Addr MipsISA::FaultVect

Definition at line 42 of file faults.hh.

◆ MachInst

typedef uint32_t MipsISA::MachInst

Definition at line 38 of file types.hh.

◆ PCState

typedef GenericISA::DelaySlotPCState<MachInst> MipsISA::PCState

Definition at line 41 of file types.hh.

◆ VecElem

using MipsISA::VecElem = typedef ::DummyVecElem

Definition at line 272 of file registers.hh.

◆ VecPredReg

using MipsISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 280 of file registers.hh.

◆ VecPredRegContainer

using MipsISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 282 of file registers.hh.

◆ VecReg

using MipsISA::VecReg = typedef ::DummyVecReg

Definition at line 273 of file registers.hh.

◆ VecRegContainer

using MipsISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 275 of file registers.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
UNSIGNED
SIGNED

Definition at line 78 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
NOSATURATE
SATURATE

Definition at line 79 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
NOROUND
ROUND

Definition at line 80 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
SIMD_FMT_L
SIMD_FMT_W
SIMD_FMT_PH
SIMD_FMT_QB
SIMD_NUM_FMTS

Definition at line 42 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
DSP_POS
DSP_SCOUNT
DSP_C
DSP_OUFLAG
DSP_CCOND
DSP_EFI
DSP_NUM_FIELDS

Definition at line 51 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
CMP_EQ
CMP_LT
CMP_LE

Definition at line 62 of file dsp.hh.

◆ anonymous enum

anonymous enum

Enumerator
MODE_L
MODE_R
MODE_LA
MODE_RA
MODE_X

Definition at line 69 of file dsp.hh.

◆ ConvertType

enum MipsISA::ConvertType

Enumerator
SINGLE_TO_DOUBLE
SINGLE_TO_WORD
SINGLE_TO_LONG
DOUBLE_TO_SINGLE
DOUBLE_TO_WORD
DOUBLE_TO_LONG
LONG_TO_SINGLE
LONG_TO_DOUBLE
LONG_TO_WORD
LONG_TO_PS
WORD_TO_SINGLE
WORD_TO_DOUBLE
WORD_TO_LONG
WORD_TO_PS
PL_TO_SINGLE
PU_TO_SINGLE

Definition at line 44 of file types.hh.

◆ ExcCode

enum MipsISA::ExcCode

Enumerator
ExcCodeDummy
ExcCodeInt
ExcCodeMod
ExcCodeTlbL
ExcCodeTlbS
ExcCodeAdEL
ExcCodeAdES
ExcCodeIBE
ExcCodeDBE
ExcCodeSys
ExcCodeBp
ExcCodeRI
ExcCodeCpU
ExcCodeOv
ExcCodeTr
ExcCodeC2E
ExcCodeMDMX
ExcCodeWatch
ExcCodeMCheck
ExcCodeThread
ExcCodeCacheErr

Definition at line 44 of file faults.hh.

◆ FCSRBits

enum MipsISA::FCSRBits

Enumerator
Inexact
Underflow
Overflow
DivideByZero
Invalid
Unimplemented

Definition at line 69 of file registers.hh.

◆ FCSRFields

enum MipsISA::FCSRFields

Enumerator
Flag_Field
Enable_Field
Cause_Field

Definition at line 78 of file registers.hh.

◆ FPControlRegNums

enum MipsISA::FPControlRegNums

Enumerator
FLOATREG_FIR
FLOATREG_FCCR
FLOATREG_FEXR
FLOATREG_FENR
FLOATREG_FCSR

Definition at line 61 of file registers.hh.

◆ InterruptLevels

enum MipsISA::InterruptLevels

Enumerator
INTLEVEL_SOFTWARE_MIN
INTLEVEL_SOFTWARE_MAX
INTLEVEL_EXTERNAL_MIN
INTLEVEL_EXTERNAL_MAX
INTLEVEL_IRQ0
INTLEVEL_IRQ1
INTINDEX_ETHERNET
INTINDEX_SCSI
INTLEVEL_IRQ2
INTLEVEL_IRQ3
INTLEVEL_SERIAL
NumInterruptLevels

Definition at line 40 of file interrupts.cc.

◆ MiscIntRegNums

enum MipsISA::MiscIntRegNums

Enumerator
INTREG_LO
INTREG_DSP_LO0
INTREG_HI
INTREG_DSP_HI0
INTREG_DSP_ACX0
INTREG_DSP_LO1
INTREG_DSP_HI1
INTREG_DSP_ACX1
INTREG_DSP_LO2
INTREG_DSP_HI2
INTREG_DSP_ACX2
INTREG_DSP_LO3
INTREG_DSP_HI3
INTREG_DSP_ACX3
INTREG_DSP_CONTROL

Definition at line 84 of file registers.hh.

◆ MiscRegIndex

enum MipsISA::MiscRegIndex

Enumerator
MISCREG_INDEX
MISCREG_MVP_CONTROL
MISCREG_MVP_CONF0
MISCREG_MVP_CONF1
MISCREG_CP0_RANDOM
MISCREG_VPE_CONTROL
MISCREG_VPE_CONF0
MISCREG_VPE_CONF1
MISCREG_YQMASK
MISCREG_VPE_SCHEDULE
MISCREG_VPE_SCHEFBACK
MISCREG_VPE_OPT
MISCREG_ENTRYLO0
MISCREG_TC_STATUS
MISCREG_TC_BIND
MISCREG_TC_RESTART
MISCREG_TC_HALT
MISCREG_TC_CONTEXT
MISCREG_TC_SCHEDULE
MISCREG_TC_SCHEFBACK
MISCREG_ENTRYLO1
MISCREG_CONTEXT
MISCREG_CONTEXT_CONFIG
MISCREG_PAGEMASK
MISCREG_PAGEGRAIN
MISCREG_WIRED
MISCREG_SRS_CONF0
MISCREG_SRS_CONF1
MISCREG_SRS_CONF2
MISCREG_SRS_CONF3
MISCREG_SRS_CONF4
MISCREG_HWRENA
MISCREG_BADVADDR
MISCREG_COUNT
MISCREG_ENTRYHI
MISCREG_COMPARE
MISCREG_STATUS
MISCREG_INTCTL
MISCREG_SRSCTL
MISCREG_SRSMAP
MISCREG_CAUSE
MISCREG_EPC
MISCREG_PRID
MISCREG_EBASE
MISCREG_CONFIG
MISCREG_CONFIG1
MISCREG_CONFIG2
MISCREG_CONFIG3
MISCREG_CONFIG4
MISCREG_CONFIG5
MISCREG_CONFIG6
MISCREG_CONFIG7
MISCREG_LLADDR
MISCREG_WATCHLO0
MISCREG_WATCHLO1
MISCREG_WATCHLO2
MISCREG_WATCHLO3
MISCREG_WATCHLO4
MISCREG_WATCHLO5
MISCREG_WATCHLO6
MISCREG_WATCHLO7
MISCREG_WATCHHI0
MISCREG_WATCHHI1
MISCREG_WATCHHI2
MISCREG_WATCHHI3
MISCREG_WATCHHI4
MISCREG_WATCHHI5
MISCREG_WATCHHI6
MISCREG_WATCHHI7
MISCREG_XCCONTEXT64
MISCREG_DEBUG
MISCREG_TRACE_CONTROL1
MISCREG_TRACE_CONTROL2
MISCREG_USER_TRACE_DATA
MISCREG_TRACE_BPC
MISCREG_DEPC
MISCREG_PERFCNT0
MISCREG_PERFCNT1
MISCREG_PERFCNT2
MISCREG_PERFCNT3
MISCREG_PERFCNT4
MISCREG_PERFCNT5
MISCREG_PERFCNT6
MISCREG_PERFCNT7
MISCREG_ERRCTL
MISCREG_CACHEERR0
MISCREG_CACHEERR1
MISCREG_CACHEERR2
MISCREG_CACHEERR3
MISCREG_TAGLO0
MISCREG_DATALO1
MISCREG_TAGLO2
MISCREG_DATALO3
MISCREG_TAGLO4
MISCREG_DATALO5
MISCREG_TAGLO6
MISCREG_DATALO7
MISCREG_TAGHI0
MISCREG_DATAHI1
MISCREG_TAGHI2
MISCREG_DATAHI3
MISCREG_TAGHI4
MISCREG_DATAHI5
MISCREG_TAGHI6
MISCREG_DATAHI7
MISCREG_ERROR_EPC
MISCREG_DESAVE
MISCREG_LLFLAG
MISCREG_TP_VALUE
MISCREG_NUMREGS

Definition at line 119 of file registers.hh.

◆ RoundMode

enum MipsISA::RoundMode

Enumerator
RND_ZERO
RND_DOWN
RND_UP
RND_NEAREST

Definition at line 68 of file types.hh.

Function Documentation

◆ addHalfLsb()

uint64_t MipsISA::addHalfLsb	(	uint64_t	value,
		int32_t	lsbpos
	)

Definition at line 126 of file dsp.cc.

References ULL.

Referenced by dspAddh(), dspExtr(), dspMulq(), dspPrecrq(), dspPrecrSra(), dspShra(), and dspSubh().

◆ advancePC()

void MipsISA::advancePC	(	PCState &	pc,
		const StaticInstPtr &	inst
	)

inline

Definition at line 88 of file utility.hh.

References pc.

◆ bitrev()

int32_t MipsISA::bitrev ( int32_t value )

Definition at line 40 of file dsp.cc.

References i, and ArmISA::shift.

◆ BitUnion32() [1/3]

MipsISA::BitUnion32 ( DebugReg )

◆ BitUnion32() [2/3]

MipsISA::BitUnion32 ( IndexReg )

◆ BitUnion32() [3/3]

MipsISA::BitUnion32 ( MVPControlReg )

◆ buildRetPC()

PCState MipsISA::buildRetPC	(	const PCState &	curPC,
		const PCState &	callPC
	)

inline

Definition at line 44 of file utility.hh.

References GenericISA::DelaySlotPCState< MachInst >::advance(), GenericISA::SimplePCState< MachInst >::npc(), and GenericISA::SimplePCState< MachInst >::pc().

◆ checkOverflow()

uint64_t MipsISA::checkOverflow	(	uint64_t	value,
		int32_t	fmt,
		int32_t	sign,
		uint32_t *	overflow
	)

Definition at line 88 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, sc_dt::overflow(), SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspExtr(), dspMul(), dspShll(), and dspSub().

◆ copyMiscRegs()

void MipsISA::copyMiscRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 231 of file utility.cc.

References panic.

◆ copyRegs()

void MipsISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 209 of file utility.cc.

References i, NumCCRegs, NumFloatRegs, NumIntRegs, NumMiscRegs, ThreadContext::pcState(), ThreadContext::readFloatRegFlat(), ThreadContext::readIntRegFlat(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setFloatRegFlat(), ThreadContext::setIntRegFlat(), and ThreadContext::setMiscRegNoEffect().

◆ dspAbs()

int32_t MipsISA::dspAbs	(	int32_t	a,
		int32_t	fmt,
		uint32_t *	dspctl
	)

Definition at line 132 of file dsp.cc.

References a, DSP_CTL_POS, DSP_OUFLAG, FIXED_SMAX, FIXED_SMIN, i, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspAdd()

int32_t MipsISA::dspAdd	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	sign,
		uint32_t *	dspctl
	)

Definition at line 163 of file dsp.cc.

References a, ArmISA::b, checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspAddh()

int32_t MipsISA::dspAddh	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	round,
		int32_t	sign
	)

Definition at line 195 of file dsp.cc.

References a, addHalfLsb(), ArmISA::b, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspCmp()

void MipsISA::dspCmp	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	sign,
		int32_t	op,
		uint32_t *	dspctl
	)

Definition at line 768 of file dsp.cc.

References a, ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, DSP_CCOND, DSP_CTL_POS, i, X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, simdUnpack(), and writeDSPControl().

◆ dspCmpg()

int32_t MipsISA::dspCmpg	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	sign,
		int32_t	op
	)

Definition at line 801 of file dsp.cc.

References a, ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, i, X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspCmpgd()

int32_t MipsISA::dspCmpgd	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	sign,
		int32_t	op,
		uint32_t *	dspctl
	)

Definition at line 833 of file dsp.cc.

References a, ArmISA::b, CMP_EQ, CMP_LE, CMP_LT, DSP_CCOND, DSP_CTL_POS, i, X86ISA::op, SIMD_MAX_VALS, SIMD_NVALS, simdUnpack(), and writeDSPControl().

◆ dspDpa()

int64_t MipsISA::dspDpa	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		int32_t	sign,
		int32_t	mode
	)

Definition at line 625 of file dsp.cc.

References a, ArmISA::b, i, mode, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpaq()

int64_t MipsISA::dspDpaq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	infmt,
		int32_t	outfmt,
		int32_t	postsat,
		int32_t	mode,
		uint32_t *	dspctl
	)

Definition at line 491 of file dsp.cc.

References a, X86ISA::ac, ArmISA::b, bits(), dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, insertBits(), mode, MODE_X, SIGNED, SIMD_FMT_L, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDps()

int64_t MipsISA::dspDps	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		int32_t	sign,
		int32_t	mode
	)

Definition at line 653 of file dsp.cc.

References a, ArmISA::b, i, mode, MODE_L, MODE_R, MODE_X, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspDpsq()

int64_t MipsISA::dspDpsq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	infmt,
		int32_t	outfmt,
		int32_t	postsat,
		int32_t	mode,
		uint32_t *	dspctl
	)

Definition at line 558 of file dsp.cc.

References a, X86ISA::ac, ArmISA::b, bits(), dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, insertBits(), mode, MODE_X, SIGNED, SIMD_FMT_L, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspExtp()

int32_t MipsISA::dspExtp	(	int64_t	dspac,
		int32_t	size,
		uint32_t *	dspctl
	)

Definition at line 1081 of file dsp.cc.

References bits(), and insertBits().

◆ dspExtpd()

int32_t MipsISA::dspExtpd	(	int64_t	dspac,
		int32_t	size,
		uint32_t *	dspctl
	)

Definition at line 1101 of file dsp.cc.

References bits(), and insertBits().

◆ dspExtr()

int32_t MipsISA::dspExtr	(	int64_t	dspac,
		int32_t	fmt,
		int32_t	sa,
		int32_t	round,
		int32_t	saturate,
		uint32_t *	dspctl
	)

Definition at line 1038 of file dsp.cc.

References addHalfLsb(), bits(), checkOverflow(), dspSaturate(), FIXED_SMAX, insertBits(), sa, SIGNED, and SIMD_FMT_L.

◆ dspMaq()

int64_t MipsISA::dspMaq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		int32_t	mode,
		int32_t	saturate,
		uint32_t *	dspctl
	)

Definition at line 681 of file dsp.cc.

References a, X86ISA::ac, ArmISA::b, dspSaturate(), FIXED_SMAX, FIXED_SMIN, i, insertBits(), mode, MODE_L, MODE_R, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspMul()

int32_t MipsISA::dspMul	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		uint32_t *	dspctl
	)

Definition at line 388 of file dsp.cc.

References a, ArmISA::b, checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMuleq()

int32_t MipsISA::dspMuleq	(	int32_t	a,
		int32_t	b,
		int32_t	mode,
		uint32_t *	dspctl
	)

Definition at line 454 of file dsp.cc.

References a, ArmISA::b, DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, mode, MODE_L, MODE_R, SIGNED, SIMD_FMT_PH, SIMD_FMT_W, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMuleu()

int32_t MipsISA::dspMuleu	(	int32_t	a,
		int32_t	b,
		int32_t	mode,
		uint32_t *	dspctl
	)

Definition at line 420 of file dsp.cc.

References a, ArmISA::b, DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, mode, MODE_L, MODE_R, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), UNSIGNED, and writeDSPControl().

◆ dspMulq()

int32_t MipsISA::dspMulq	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	round,
		uint32_t *	dspctl
	)

Definition at line 347 of file dsp.cc.

References a, addHalfLsb(), ArmISA::b, DSP_CTL_POS, DSP_OUFLAG, FIXED_SMAX, FIXED_SMIN, i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspMulsa()

int64_t MipsISA::dspMulsa	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt
	)

Definition at line 725 of file dsp.cc.

References a, ArmISA::b, SIGNED, SIMD_MAX_VALS, and simdUnpack().

◆ dspMulsaq()

int64_t MipsISA::dspMulsaq	(	int64_t	dspac,
		int32_t	a,
		int32_t	b,
		int32_t	ac,
		int32_t	fmt,
		uint32_t *	dspctl
	)

Definition at line 739 of file dsp.cc.

References a, X86ISA::ac, ArmISA::b, FIXED_SMAX, FIXED_SMIN, i, insertBits(), SIGNED, SIMD_MAX_VALS, SIMD_NVALS, and simdUnpack().

◆ dspPack()

int32_t MipsISA::dspPack	(	int32_t	a,
		int32_t	b,
		int32_t	fmt
	)

Definition at line 1019 of file dsp.cc.

References a, ArmISA::b, SIMD_MAX_VALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPick()

int32_t MipsISA::dspPick	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		uint32_t *	dspctl
	)

Definition at line 994 of file dsp.cc.

References a, ArmISA::b, bits(), DSP_CCOND, DSP_CTL_POS, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrece()

int32_t MipsISA::dspPrece	(	int32_t	a,
		int32_t	infmt,
		int32_t	insign,
		int32_t	outfmt,
		int32_t	outsign,
		int32_t	mode
	)

Definition at line 870 of file dsp.cc.

References a, i, mode, MODE_L, MODE_LA, MODE_R, MODE_RA, sa, SIGNED, SIMD_MAX_VALS, SIMD_NBITS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrq()

int32_t MipsISA::dspPrecrq	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		uint32_t *	dspctl
	)

Definition at line 941 of file dsp.cc.

References a, addHalfLsb(), ArmISA::b, dspSaturate(), insertBits(), SIGNED, SIMD_MAX_VALS, simdPack(), and simdUnpack().

◆ dspPrecrqu()

int32_t MipsISA::dspPrecrqu	(	int32_t	a,
		int32_t	b,
		uint32_t *	dspctl
	)

Definition at line 912 of file dsp.cc.

References a, ArmISA::b, dspSaturate(), i, insertBits(), SIGNED, SIMD_FMT_PH, SIMD_FMT_QB, SIMD_MAX_VALS, SIMD_NBITS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspPrecrSra()

int32_t MipsISA::dspPrecrSra	(	int32_t	a,
		int32_t	b,
		int32_t	sa,
		int32_t	fmt,
		int32_t	round
	)

Definition at line 966 of file dsp.cc.

References a, addHalfLsb(), ArmISA::b, i, sa, SIGNED, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspSaturate()

uint64_t MipsISA::dspSaturate	(	uint64_t	value,
		int32_t	fmt,
		int32_t	sign,
		uint32_t *	overflow
	)

Definition at line 58 of file dsp.cc.

References FIXED_SMAX, FIXED_SMIN, FIXED_UMAX, FIXED_UMIN, sc_dt::overflow(), SIGNED, and UNSIGNED.

Referenced by dspAdd(), dspDpaq(), dspDpsq(), dspExtr(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspPrecrq(), dspPrecrqu(), dspShll(), and dspSub().

◆ dspShll()

int32_t MipsISA::dspShll	(	int32_t	a,
		uint32_t	sa,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	sign,
		uint32_t *	dspctl
	)

Definition at line 275 of file dsp.cc.

References a, bits(), checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, sa, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspShra()

int32_t MipsISA::dspShra	(	int32_t	a,
		uint32_t	sa,
		int32_t	fmt,
		int32_t	round,
		int32_t	sign,
		uint32_t *	dspctl
	)

Definition at line 323 of file dsp.cc.

References a, addHalfLsb(), bits(), i, sa, SIGNED, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ dspShrl()

int32_t MipsISA::dspShrl	(	int32_t	a,
		uint32_t	sa,
		int32_t	fmt,
		int32_t	sign
	)

Definition at line 304 of file dsp.cc.

References a, bits(), i, sa, SIMD_LOG2N, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and UNSIGNED.

◆ dspSub()

int32_t MipsISA::dspSub	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	saturate,
		int32_t	sign,
		uint32_t *	dspctl
	)

Definition at line 219 of file dsp.cc.

References a, ArmISA::b, checkOverflow(), DSP_CTL_POS, DSP_OUFLAG, dspSaturate(), i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), simdUnpack(), and writeDSPControl().

◆ dspSubh()

int32_t MipsISA::dspSubh	(	int32_t	a,
		int32_t	b,
		int32_t	fmt,
		int32_t	round,
		int32_t	sign
	)

Definition at line 250 of file dsp.cc.

References a, addHalfLsb(), ArmISA::b, i, SIMD_MAX_VALS, SIMD_NVALS, simdPack(), and simdUnpack().

◆ EndBitUnion() [1/35]

MipsISA::EndBitUnion ( CacheErrReg )

◆ EndBitUnion() [2/35]

MipsISA::EndBitUnion ( CauseReg )

◆ EndBitUnion() [3/35]

MipsISA::EndBitUnion ( Config1Reg )

◆ EndBitUnion() [4/35]

MipsISA::EndBitUnion ( Config2Reg )

◆ EndBitUnion() [5/35]

MipsISA::EndBitUnion ( Config3Reg )

◆ EndBitUnion() [6/35]

MipsISA::EndBitUnion ( ConfigReg )

◆ EndBitUnion() [7/35]

MipsISA::EndBitUnion ( ContextReg )

◆ EndBitUnion() [8/35]

MipsISA::EndBitUnion ( DebugReg )

◆ EndBitUnion() [9/35]

MipsISA::EndBitUnion ( EBaseReg )

◆ EndBitUnion() [10/35]

MipsISA::EndBitUnion ( EntryHiReg )

◆ EndBitUnion() [11/35]

MipsISA::EndBitUnion ( EntryLoReg )

◆ EndBitUnion() [12/35]

MipsISA::EndBitUnion ( HWREnaReg )

◆ EndBitUnion() [13/35]

MipsISA::EndBitUnion ( IndexReg )

◆ EndBitUnion() [14/35]

MipsISA::EndBitUnion ( IntCtlReg )

◆ EndBitUnion() [15/35]

MipsISA::EndBitUnion ( MVPConf0Reg )

◆ EndBitUnion() [16/35]

MipsISA::EndBitUnion ( MVPControlReg )

◆ EndBitUnion() [17/35]

MipsISA::EndBitUnion ( PageGrainReg )

◆ EndBitUnion() [18/35]

MipsISA::EndBitUnion ( PageMaskReg )

◆ EndBitUnion() [19/35]

MipsISA::EndBitUnion ( PerfCntCtlReg )

◆ EndBitUnion() [20/35]

MipsISA::EndBitUnion ( PRIdReg )

◆ EndBitUnion() [21/35]

MipsISA::EndBitUnion ( RandomReg )

◆ EndBitUnion() [22/35]

MipsISA::EndBitUnion ( SRSCtlReg )

◆ EndBitUnion() [23/35]

MipsISA::EndBitUnion ( SRSMapReg )

◆ EndBitUnion() [24/35]

MipsISA::EndBitUnion ( StatusReg )

◆ EndBitUnion() [25/35]

MipsISA::EndBitUnion ( TCBindReg )

◆ EndBitUnion() [26/35]

MipsISA::EndBitUnion ( TCStatusReg )

◆ EndBitUnion() [27/35]

MipsISA::EndBitUnion ( TraceBPC2Reg )

◆ EndBitUnion() [28/35]

MipsISA::EndBitUnion ( TraceBPCReg )

◆ EndBitUnion() [29/35]

MipsISA::EndBitUnion ( TraceControl2Reg )

◆ EndBitUnion() [30/35]

MipsISA::EndBitUnion ( TraceControlReg )

◆ EndBitUnion() [31/35]

MipsISA::EndBitUnion ( VPEConf0Reg )

◆ EndBitUnion() [32/35]

MipsISA::EndBitUnion ( VPEControlReg )

◆ EndBitUnion() [33/35]

MipsISA::EndBitUnion ( WatchHiReg )

◆ EndBitUnion() [34/35]

MipsISA::EndBitUnion ( WatchLoReg )

◆ EndBitUnion() [35/35]

MipsISA::EndBitUnion ( WiredReg )

◆ EndSubBitUnion() [1/4]

MipsISA::EndSubBitUnion ( cu )

◆ EndSubBitUnion() [2/4]

MipsISA::EndSubBitUnion ( ejtagVer )

◆ EndSubBitUnion() [3/4]

MipsISA::EndSubBitUnion ( im )

◆ EndSubBitUnion() [4/4]

MipsISA::EndSubBitUnion ( ip )

◆ forkThread()

template<class TC >

void MipsISA::forkThread	(	TC *	tc,
		Fault &	fault,
		int	Rd_bits,
		int	Rs,
		int	Rt
	)

Definition at line 169 of file mt.hh.

References IntRegClass, MISCREG_MVP_CONF0, MISCREG_STATUS, MISCREG_TC_BIND, MISCREG_TC_HALT, MISCREG_TC_RESTART, MISCREG_TC_STATUS, MISCREG_VPE_CONTROL, MiscRegClass, readRegOtherThread(), setRegOtherThread(), and ArmISA::status.

◆ fpConvert()

uint64_t MipsISA::fpConvert	(	ConvertType	cvt_type,
		double	fp_val
	)

Definition at line 46 of file utility.cc.

References panic, SINGLE_TO_DOUBLE, SINGLE_TO_WORD, WORD_TO_DOUBLE, and WORD_TO_SINGLE.

◆ genCCVector()

uint32_t MipsISA::genCCVector	(	uint32_t	fcsr,
		int	cc_num,
		uint32_t	cc_val
	)

Definition at line 116 of file utility.cc.

References bits().

◆ genInvalidVector()

uint32_t MipsISA::genInvalidVector ( uint32_t fcsr_bits )

Definition at line 128 of file utility.cc.

References Cause_Field, Flag_Field, and Invalid.

◆ getCauseIP()

static uint8_t MipsISA::getCauseIP ( ThreadContext * tc )

inlinestatic

Definition at line 61 of file interrupts.cc.

References MISCREG_CAUSE, and ThreadContext::readMiscRegNoEffect().

Referenced by MipsISA::Interrupts::clear(), MipsISA::Interrupts::interruptsPending(), and MipsISA::Interrupts::post().

◆ getCondCode()

bool MipsISA::getCondCode	(	uint32_t	fcsr,
		int	cc_idx
	)

Definition at line 108 of file utility.cc.

References ArmISA::shift.

◆ getTargetThread()

template<class TC >

unsigned MipsISA::getTargetThread ( TC * tc )

inline

Definition at line 125 of file mt.hh.

References MISCREG_VPE_CONTROL.

◆ getVirtProcNum()

template<class TC >

unsigned MipsISA::getVirtProcNum ( TC * tc )

inline

Definition at line 117 of file mt.hh.

References MISCREG_TC_BIND.

◆ globalClearExclusive()

template<class XC >

void MipsISA::globalClearExclusive ( XC * xc )

inline

Definition at line 143 of file locked_mem.hh.

◆ haltThread()

template<class TC >

void MipsISA::haltThread ( TC * tc )

inline

Definition at line 133 of file mt.hh.

References curTick(), MISCREG_TC_RESTART, pc, and warn.

Referenced by MipsISA::ISA::updateCPU().

◆ handleLockedRead()

template<class XC >

void MipsISA::handleLockedRead	(	XC *	xc,
		const RequestPtr &	req
	)

inline

Definition at line 77 of file locked_mem.hh.

References DPRINTF, MISCREG_LLADDR, and MISCREG_LLFLAG.

◆ handleLockedSnoop()

template<class XC >

void MipsISA::handleLockedSnoop	(	XC *	xc,
		PacketPtr	pkt,
		Addr	cacheBlockMask
	)

inline

Definition at line 62 of file locked_mem.hh.

References Packet::getAddr(), MISCREG_LLADDR, and MISCREG_LLFLAG.

◆ handleLockedSnoopHit()

template<class XC >

void MipsISA::handleLockedSnoopHit ( XC * xc )

inline

Definition at line 88 of file locked_mem.hh.

◆ handleLockedWrite()

template<class XC >

bool MipsISA::handleLockedWrite	(	XC *	xc,
		const RequestPtr &	req,
		Addr	cacheBlockMask
	)

inline

Definition at line 94 of file locked_mem.hh.

References curTick(), DPRINTF, MISCREG_LLADDR, MISCREG_LLFLAG, and warn.

◆ isNan()

bool MipsISA::isNan	(	void *	val_ptr,
		int	size
	)

Definition at line 142 of file utility.cc.

References bits(), and panic.

◆ isQnan()

bool MipsISA::isQnan	(	void *	val_ptr,
		int	size
	)

Definition at line 165 of file utility.cc.

References bits(), and panic.

◆ isSnan()

bool MipsISA::isSnan	(	void *	val_ptr,
		int	size
	)

Definition at line 187 of file utility.cc.

References bits(), and panic.

◆ readDSPControl()

uint32_t MipsISA::readDSPControl	(	uint32_t *	dspctl,
		uint32_t	mask
	)

Definition at line 1176 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, DSP_SCOUNT, and mask.

◆ readRegOtherThread() [1/2]

static RegVal MipsISA::readRegOtherThread	(	ExecContext *	xc,
		const RegId &	reg,
		ThreadID	tid = `InvalidThreadID`
	)

inlinestatic

Definition at line 102 of file mt.hh.

References readRegOtherThread(), X86ISA::reg, and ExecContext::tcBase().

◆ readRegOtherThread() [2/2]

static RegVal MipsISA::readRegOtherThread	(	ThreadContext *	tc,
		const RegId &	reg,
		ThreadID	tid = `InvalidThreadID`
	)

inlinestatic

Definition at line 54 of file mt.hh.

References FloatRegClass, BaseCPU::getContext(), ThreadContext::getCpuPtr(), IntRegClass, InvalidThreadID, MiscRegClass, panic, ThreadContext::readFloatReg(), ThreadContext::readIntReg(), ThreadContext::readMiscReg(), and X86ISA::reg.

Referenced by forkThread(), readRegOtherThread(), and yieldThread().

◆ restoreThread()

template<class TC >

void MipsISA::restoreThread ( TC * tc )

inline

Definition at line 152 of file mt.hh.

References curTick(), MISCREG_TC_RESTART, and warn.

Referenced by MipsISA::ISA::updateCPU().

◆ roundFP()

double MipsISA::roundFP	(	double	val,
		int	digits
	)

Definition at line 90 of file utility.cc.

References X86ISA::val.

◆ RoundPage()

Addr MipsISA::RoundPage ( Addr addr )

inline

Definition at line 79 of file utility.hh.

References X86ISA::addr, and PageBytes.

◆ setCauseIP()

static void MipsISA::setCauseIP	(	ThreadContext *	tc,
		uint8_t	val
	)

inlinestatic

Definition at line 68 of file interrupts.cc.

References MISCREG_CAUSE, ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscRegNoEffect(), and X86ISA::val.

Referenced by MipsISA::Interrupts::clear(), MipsISA::Interrupts::clearAll(), MipsISA::Interrupts::interruptsPending(), and MipsISA::Interrupts::post().

◆ setRegOtherThread() [1/2]

static void MipsISA::setRegOtherThread	(	ExecContext *	xc,
		const RegId &	reg,
		RegVal	val,
		ThreadID	tid = `InvalidThreadID`
	)

inlinestatic

Definition at line 109 of file mt.hh.

References X86ISA::reg, setRegOtherThread(), ExecContext::tcBase(), and X86ISA::val.

◆ setRegOtherThread() [2/2]

static void MipsISA::setRegOtherThread	(	ThreadContext *	tc,
		const RegId &	reg,
		RegVal	val,
		ThreadID	tid = `InvalidThreadID`
	)

inlinestatic

Definition at line 78 of file mt.hh.

References FloatRegClass, BaseCPU::getContext(), ThreadContext::getCpuPtr(), IntRegClass, InvalidThreadID, MiscRegClass, panic, X86ISA::reg, ThreadContext::setFloatReg(), ThreadContext::setIntReg(), ThreadContext::setMiscReg(), and X86ISA::val.

Referenced by forkThread(), and setRegOtherThread().

◆ setThreadAreaFunc()

static SyscallReturn MipsISA::setThreadAreaFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	addr
	)

static

Definition at line 150 of file se_workload.cc.

References X86ISA::addr, MISCREG_TP_VALUE, and ThreadContext::setMiscRegNoEffect().

◆ signExtend()

uint64_t MipsISA::signExtend	(	uint64_t	value,
		int32_t	signpos
	)

Definition at line 111 of file dsp.cc.

References SIMD_NBITS, and ULL.

Referenced by simdUnpack().

◆ simdPack()

void MipsISA::simdPack	(	uint64_t *	values_ptr,
		int32_t *	reg,
		int32_t	fmt
	)

Definition at line 1125 of file dsp.cc.

References bits(), i, X86ISA::reg, SIMD_NBITS, and SIMD_NVALS.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ simdUnpack()

void MipsISA::simdUnpack	(	int32_t	reg,
		uint64_t *	values_ptr,
		int32_t	fmt,
		int32_t	sign
	)

Definition at line 1137 of file dsp.cc.

References bits(), i, X86ISA::reg, SIGNED, signExtend(), SIMD_NBITS, SIMD_NVALS, and UNSIGNED.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ SubBitUnion() [1/3]

MipsISA::SubBitUnion	(	ejtagVer	,
		17	,
		15
	)

◆ SubBitUnion() [2/3]

MipsISA::SubBitUnion	(	im	,
		15	,
		8
	)

◆ SubBitUnion() [3/3]

MipsISA::SubBitUnion	(	ip	,
		15	,
		8
	)

◆ sys_getsysinfoFunc()

static SyscallReturn MipsISA::sys_getsysinfoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		unsigned	op,
		unsigned	bufPtr,
		unsigned	nbytes
	)

static

Target sys_getsysyinfo() handler.

Even though this call is borrowed from Tru64, the subcases that get used appear to be different in practice from those used by Tru64 processes.

Definition at line 103 of file se_workload.cc.

References X86ISA::op.

◆ sys_setsysinfoFunc()

static SyscallReturn MipsISA::sys_setsysinfoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		unsigned	op,
		VPtr<>	bufPtr,
		unsigned	nbytes
	)

static

Target sys_setsysinfo() handler.

Definition at line 126 of file se_workload.cc.

References DPRINTFR, letoh(), and X86ISA::op.

◆ truncFP()

double MipsISA::truncFP ( double val )

Definition at line 101 of file utility.cc.

References X86ISA::val.

◆ TruncPage()

Addr MipsISA::TruncPage ( Addr addr )

inline

Definition at line 73 of file utility.hh.

References X86ISA::addr, and PageBytes.

◆ unameFunc()

static SyscallReturn MipsISA::unameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< Linux::utsname >	name
	)

static

Target uname() handler.

Definition at line 86 of file se_workload.cc.

References ThreadContext::getProcessPtr(), and name().

◆ updateStatusView()

template<class TC >

void MipsISA::updateStatusView ( TC * tc )

inline

Definition at line 303 of file mt.hh.

References MISCREG_STATUS, MISCREG_TC_STATUS, and ArmISA::status.

◆ updateTCStatusView()

template<class TC >

void MipsISA::updateTCStatusView ( TC * tc )

inline

Definition at line 321 of file mt.hh.

References MISCREG_STATUS, MISCREG_TC_STATUS, and ArmISA::status.

◆ writeDSPControl()

void MipsISA::writeDSPControl	(	uint32_t *	dspctl,
		uint32_t	value,
		uint32_t	mask
	)

Definition at line 1159 of file dsp.cc.

References DSP_C, DSP_CCOND, DSP_CTL_MASK, DSP_EFI, DSP_OUFLAG, DSP_POS, DSP_SCOUNT, and mask.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspShll(), and dspSub().

◆ yieldThread()

template<class TC >

int MipsISA::yieldThread	(	TC *	tc,
		Fault &	fault,
		int	src_reg,
		uint32_t	yield_mask
	)

Definition at line 237 of file mt.hh.

References curTick(), MISCREG_MVP_CONF0, MISCREG_TC_BIND, MISCREG_TC_HALT, MISCREG_TC_STATUS, MISCREG_VPE_CONTROL, MiscRegClass, readRegOtherThread(), and warn.

Variable Documentation

◆ a

Bitfield<13> MipsISA::a

Definition at line 89 of file mt_constants.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ a0

Bitfield<20, 18> MipsISA::a0

Definition at line 76 of file mt_constants.hh.

Referenced by ArmISA::add128(), ArmISA::mul62x62(), and ArmISA::sub128().

◆ ar

Bitfield<12, 10> MipsISA::ar

Definition at line 222 of file pra_constants.hh.

◆ aseDn

Bitfield<12, 8> MipsISA::aseDn

Definition at line 80 of file pra_constants.hh.

◆ aseUp

MipsISA::aseUp

Definition at line 76 of file pra_constants.hh.

◆ asid

Bitfield< 23, 16 > MipsISA::asid

Definition at line 82 of file dt_constants.hh.

◆ asidM

Bitfield<20, 13> MipsISA::asidM

Definition at line 81 of file dt_constants.hh.

◆ at

Bitfield<14, 13> MipsISA::at

Definition at line 221 of file pra_constants.hh.

◆ ate

Bitfield<27> MipsISA::ate

Definition at line 105 of file dt_constants.hh.

◆ badVPN2

Bitfield<22, 4> MipsISA::badVPN2

Definition at line 64 of file pra_constants.hh.

◆ be

Bitfield<15> MipsISA::be

Definition at line 220 of file pra_constants.hh.

Referenced by Request::setByteEnable().

◆ bev

Bitfield<22> MipsISA::bev

Definition at line 114 of file pra_constants.hh.

◆ bpc0

Bitfield<2, 0> MipsISA::bpc0

Definition at line 114 of file dt_constants.hh.

◆ bpc1

Bitfield<5, 3> MipsISA::bpc1

Definition at line 113 of file dt_constants.hh.

◆ bpc10

Bitfield<5, 3> MipsISA::bpc10

Definition at line 122 of file dt_constants.hh.

◆ bpc11

Bitfield<8, 6> MipsISA::bpc11

Definition at line 121 of file dt_constants.hh.

◆ bpc12

Bitfield<11, 9> MipsISA::bpc12

Definition at line 120 of file dt_constants.hh.

◆ bpc13

Bitfield<14, 12> MipsISA::bpc13

Definition at line 119 of file dt_constants.hh.

◆ bpc14

MipsISA::bpc14

Definition at line 118 of file dt_constants.hh.

◆ bpc2

Bitfield<8, 6> MipsISA::bpc2

Definition at line 112 of file dt_constants.hh.

◆ bpc3

Bitfield<11, 9> MipsISA::bpc3

Definition at line 111 of file dt_constants.hh.

◆ bpc4

Bitfield<14, 12> MipsISA::bpc4

Definition at line 110 of file dt_constants.hh.

◆ bpc5

Bitfield<17, 15> MipsISA::bpc5

Definition at line 109 of file dt_constants.hh.

◆ bpc6

Bitfield<20, 18> MipsISA::bpc6

Definition at line 108 of file dt_constants.hh.

◆ bpc7

Bitfield<23, 21> MipsISA::bpc7

Definition at line 107 of file dt_constants.hh.

◆ bpc8

Bitfield<26, 24> MipsISA::bpc8

Definition at line 106 of file dt_constants.hh.

◆ bpc9

Bitfield<2, 0> MipsISA::bpc9

Definition at line 123 of file dt_constants.hh.

◆ c

Bitfield<5, 3> MipsISA::c

Definition at line 56 of file pra_constants.hh.

◆ c2

Bitfield<6> MipsISA::c2

Definition at line 238 of file pra_constants.hh.

Referenced by MultiperspectivePerceptron::MPPBranchInfo::hash2(), MemCmd::operator!=(), MemCmd::operator==(), and SC_MODULE().

◆ ca

Bitfield<2> MipsISA::ca

Definition at line 242 of file pra_constants.hh.

◆ cacheep

Bitfield<22> MipsISA::cacheep

Definition at line 48 of file dt_constants.hh.

◆ ce

Bitfield<29, 28> MipsISA::ce

Definition at line 177 of file pra_constants.hh.

◆ coId

Bitfield<23, 16> MipsISA::coId

Definition at line 202 of file pra_constants.hh.

◆ conutdm

Bitfield<25> MipsISA::conutdm

Definition at line 45 of file dt_constants.hh.

◆ coOp

MipsISA::coOp

Definition at line 201 of file pra_constants.hh.

◆ cpuid

Bitfield<28, 21> MipsISA::cpuid

Definition at line 92 of file dt_constants.hh.

Referenced by Iob::readJBus(), X86KvmCPU::setCPUID(), X86KvmCPU::updateCPUID(), PseudoInst::wakeCPU(), and Iob::writeJBus().

◆ cpuNum

Bitfield<9, 9> MipsISA::cpuNum

Definition at line 212 of file pra_constants.hh.

◆ css

Bitfield<3, 0> MipsISA::css

Definition at line 160 of file pra_constants.hh.

◆ cu0

Bitfield<28> MipsISA::cu0

Definition at line 107 of file pra_constants.hh.

◆ cu1

Bitfield<29> MipsISA::cu1

Definition at line 106 of file pra_constants.hh.

◆ cu2

Bitfield<30> MipsISA::cu2

Definition at line 105 of file pra_constants.hh.

◆ cu3

Bitfield<31> MipsISA::cu3

Definition at line 103 of file pra_constants.hh.

◆ curTC

MipsISA::curTC

Definition at line 75 of file mt_constants.hh.

◆ curVPE

Bitfield<3, 0> MipsISA::curVPE

Definition at line 78 of file mt_constants.hh.

◆ d

Bitfield< 2 > MipsISA::d

Definition at line 76 of file dt_constants.hh.

◆ da

Bitfield< 9, 7 > MipsISA::da

Definition at line 88 of file mt_constants.hh.

◆ dbp

Bitfield<1> MipsISA::dbp

Definition at line 67 of file dt_constants.hh.

◆ dbusep

Bitfield<21> MipsISA::dbusep

Definition at line 49 of file dt_constants.hh.

◆ dc

Bitfield<27> MipsISA::dc

Definition at line 178 of file pra_constants.hh.

◆ dcs

Bitfield<17> MipsISA::dcs

Definition at line 68 of file mt_constants.hh.

◆ ddbl

Bitfield<2> MipsISA::ddbl

Definition at line 66 of file dt_constants.hh.

◆ ddblImpr

Bitfield<18> MipsISA::ddblImpr

Definition at line 52 of file dt_constants.hh.

◆ ddbs

Bitfield<3> MipsISA::ddbs

Definition at line 65 of file dt_constants.hh.

◆ ddbsImpr

Bitfield<19> MipsISA::ddbsImpr

Definition at line 51 of file dt_constants.hh.

◆ dexcCode

MipsISA::dexcCode

Definition at line 58 of file dt_constants.hh.

◆ dib

Bitfield<4> MipsISA::dib

Definition at line 64 of file dt_constants.hh.

◆ dibimpr

Bitfield<6> MipsISA::dibimpr

Definition at line 62 of file dt_constants.hh.

◆ dint

Bitfield<5> MipsISA::dint

Definition at line 63 of file dt_constants.hh.

◆ dl

Bitfield<12, 10> MipsISA::dl

Definition at line 236 of file pra_constants.hh.

◆ dm

Bitfield<30> MipsISA::dm

Definition at line 40 of file dt_constants.hh.

◆ doze

Bitfield<27> MipsISA::doze

Definition at line 43 of file dt_constants.hh.

◆ dq

Bitfield<2> MipsISA::dq

Definition at line 128 of file dt_constants.hh.

Referenced by ScheduleStage::ScheduleStage().

◆ ds

Bitfield<15, 13> MipsISA::ds

Definition at line 235 of file pra_constants.hh.

Referenced by X86ISA::FsWorkload::initState(), and X86ISA::X86_64Process::initState().

◆ DSP_CTL_MASK

const uint32_t MipsISA::DSP_CTL_MASK[DSP_NUM_FIELDS]

Initial value:

=
{ 0x0000003f, 0x00001f80, 0x00002000,
  0x00ff0000, 0x0f000000, 0x00004000 }

Definition at line 84 of file dsp.hh.

Referenced by readDSPControl(), and writeDSPControl().

◆ DSP_CTL_POS

const uint32_t MipsISA::DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }

Definition at line 83 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspCmp(), dspCmpgd(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspPick(), dspShll(), and dspSub().

◆ dspp

Bitfield<10> MipsISA::dspp

Definition at line 262 of file pra_constants.hh.

◆ dss

Bitfield<0> MipsISA::dss

Definition at line 68 of file dt_constants.hh.

◆ dt

Bitfield<20> MipsISA::dt

Definition at line 86 of file mt_constants.hh.

◆ e

Bitfield< 28 > MipsISA::e

Definition at line 77 of file dt_constants.hh.

◆ eb

Bitfield<25> MipsISA::eb

Definition at line 312 of file pra_constants.hh.

◆ ec

Bitfield<30> MipsISA::ec

Definition at line 307 of file pra_constants.hh.

◆ ed

Bitfield<29> MipsISA::ed

Definition at line 308 of file pra_constants.hh.

◆ ee

Bitfield<26> MipsISA::ee

Definition at line 311 of file pra_constants.hh.

◆ eicss

Bitfield<21, 18> MipsISA::eicss

Definition at line 154 of file pra_constants.hh.

◆ ejtagVer0

Bitfield<15> MipsISA::ejtagVer0

Definition at line 56 of file dt_constants.hh.

◆ ejtagVer1

Bitfield<16> MipsISA::ejtagVer1

Definition at line 55 of file dt_constants.hh.

◆ elpa

Bitfield<29> MipsISA::elpa

Definition at line 77 of file pra_constants.hh.

◆ ep

Bitfield<1> MipsISA::ep

Definition at line 243 of file pra_constants.hh.

Referenced by SMMUProcess::scheduleWakeup(), and TesterThread::~TesterThread().

◆ erl

Bitfield<2> MipsISA::erl

Definition at line 137 of file pra_constants.hh.

◆ es

Bitfield<27> MipsISA::es

Definition at line 310 of file pra_constants.hh.

◆ esp

Bitfield<28> MipsISA::esp

Definition at line 78 of file pra_constants.hh.

◆ ess

Bitfield<15, 12> MipsISA::ess

Definition at line 156 of file pra_constants.hh.

◆ et

Bitfield<28> MipsISA::et

Definition at line 309 of file pra_constants.hh.

◆ event

Bitfield<10, 5> MipsISA::event

Definition at line 297 of file pra_constants.hh.

◆ evp

Bitfield<0> MipsISA::evp

Definition at line 42 of file mt_constants.hh.

◆ excCode

Bitfield<6, 2> MipsISA::excCode

Definition at line 196 of file pra_constants.hh.

Referenced by MipsISA::MipsFaultBase::setExceptionState(), and MipsISA::TlbFault< TlbInvalidFault >::setTlbExceptionState().

◆ exceptionBase

MipsISA::exceptionBase

Definition at line 210 of file pra_constants.hh.

◆ excpt

Bitfield<18, 16> MipsISA::excpt

Definition at line 58 of file mt_constants.hh.

◆ exl

Bitfield< 0 > MipsISA::exl

Definition at line 138 of file pra_constants.hh.

◆ fill

Bitfield< 61, 40 > MipsISA::fill

Definition at line 54 of file pra_constants.hh.

Referenced by AQLRingBuffer::AQLRingBuffer(), RiscvISA::ISA::clear(), BaseDynInst< Impl >::Regs::init(), DRAMInterface::minBankPrep(), GenericPciHost::read(), Compressor::DictionaryCompressor< uint64_t >::resetDictionary(), MSHR::TargetList::resetFlags(), HSAPacketProcessor::SignalState::resetSigVals(), and MSHR::TargetList::updateWriteFlags().

◆ FirstArgumentReg

const int MipsISA::FirstArgumentReg = 4

Definition at line 105 of file registers.hh.

Referenced by MipsProcess::argsInit().

◆ FIXED_B_SMAX

const uint64_t MipsISA::FIXED_B_SMAX = ULL(0x000000000000007f)

Definition at line 106 of file dsp.hh.

◆ FIXED_B_SMIN

const uint64_t MipsISA::FIXED_B_SMIN = ULL(0xffffffffffffff80)

Definition at line 120 of file dsp.hh.

◆ FIXED_B_UMAX

const uint64_t MipsISA::FIXED_B_UMAX = ULL(0x00000000000000ff)

Definition at line 110 of file dsp.hh.

◆ FIXED_B_UMIN

const uint64_t MipsISA::FIXED_B_UMIN = ULL(0x0000000000000000)

Definition at line 124 of file dsp.hh.

◆ FIXED_H_SMAX

const uint64_t MipsISA::FIXED_H_SMAX = ULL(0x0000000000007fff)

Definition at line 105 of file dsp.hh.

◆ FIXED_H_SMIN

const uint64_t MipsISA::FIXED_H_SMIN = ULL(0xffffffffffff8000)

Definition at line 119 of file dsp.hh.

◆ FIXED_H_UMAX

const uint64_t MipsISA::FIXED_H_UMAX = ULL(0x000000000000ffff)

Definition at line 109 of file dsp.hh.

◆ FIXED_H_UMIN

const uint64_t MipsISA::FIXED_H_UMIN = ULL(0x0000000000000000)

Definition at line 123 of file dsp.hh.

◆ FIXED_L_SMAX

const uint64_t MipsISA::FIXED_L_SMAX = ULL(0x7fffffffffffffff)

Definition at line 103 of file dsp.hh.

◆ FIXED_L_SMIN

const uint64_t MipsISA::FIXED_L_SMIN = ULL(0x8000000000000000)

Definition at line 117 of file dsp.hh.

◆ FIXED_L_UMAX

Definition at line 104 of file dsp.hh.

◆ FIXED_W_SMIN

const uint64_t MipsISA::FIXED_W_SMIN = ULL(0xffffffff80000000)

Definition at line 118 of file dsp.hh.

◆ FIXED_W_UMAX

const uint64_t MipsISA::FIXED_W_UMAX = ULL(0x00000000ffffffff)

Definition at line 108 of file dsp.hh.

◆ FIXED_W_UMIN

const uint64_t MipsISA::FIXED_W_UMIN = ULL(0x0000000000000000)

Definition at line 122 of file dsp.hh.

◆ fp

Bitfield<0> MipsISA::fp

Definition at line 244 of file pra_constants.hh.

◆ fr

Bitfield<26> MipsISA::fr

Definition at line 110 of file pra_constants.hh.

◆ g

Bitfield< 30 > MipsISA::g

Definition at line 83 of file dt_constants.hh.

Referenced by MultiperspectivePerceptronTAGE::getIndex(), MultiperspectivePerceptron::getIndex(), SparcISA::SparcStaticInst::passesFpCondition(), Stats::Group::preDumpStats(), QTIsaac< ALPHA >::randinit(), Stats::Group::regStats(), Stats::Group::resetStats(), Stats::Group::resolveStat(), QTIsaac< ALPHA >::shuffle(), TEST(), and UncontendedMutex::unlock().

◆ gs

Bitfield<28> MipsISA::gs

Definition at line 48 of file mt_constants.hh.

◆ GuestByteOrder

const ByteOrder MipsISA::GuestByteOrder = ByteOrder::little

Definition at line 39 of file isa_traits.hh.

◆ halt

Bitfield<26> MipsISA::halt

Definition at line 44 of file dt_constants.hh.

◆ hss

MipsISA::hss

Definition at line 152 of file pra_constants.hh.

◆ i

Bitfield< 2 > MipsISA::i

◆ ia

Bitfield<18, 16> MipsISA::ia

Definition at line 234 of file pra_constants.hh.

Referenced by Net::operator<<().

◆ ibusep

Bitfield<24> MipsISA::ibusep

Definition at line 46 of file dt_constants.hh.

◆ ics

Bitfield<16> MipsISA::ics

Definition at line 69 of file mt_constants.hh.

◆ ie

Bitfield< 4 > MipsISA::ie

Definition at line 139 of file pra_constants.hh.

◆ iexi

Bitfield<20, 19> MipsISA::iexi

Definition at line 50 of file dt_constants.hh.

◆ il

Bitfield<21, 19> MipsISA::il

Definition at line 233 of file pra_constants.hh.

◆ im0

Bitfield<8> MipsISA::im0

Definition at line 129 of file pra_constants.hh.

◆ im1

Bitfield<9> MipsISA::im1

Definition at line 128 of file pra_constants.hh.

◆ im2

Bitfield<10> MipsISA::im2

Definition at line 127 of file pra_constants.hh.

◆ im3

Bitfield<11> MipsISA::im3

Definition at line 126 of file pra_constants.hh.

◆ im4

Bitfield<12> MipsISA::im4

Definition at line 125 of file pra_constants.hh.

◆ im5

Bitfield<13> MipsISA::im5

Definition at line 124 of file pra_constants.hh.

◆ im6

Bitfield<14> MipsISA::im6

Definition at line 123 of file pra_constants.hh.

◆ impl

Bitfield< 4, 3 > MipsISA::impl

Definition at line 87 of file mt_constants.hh.

Referenced by ArmSemihosting::SemiCall::buildDispatcher(), and ArmSemihosting::SemiCall::wrapImpl().

◆ index

Bitfield< 22, 0 > MipsISA::index

Definition at line 44 of file pra_constants.hh.

◆ io

Bitfield<26> MipsISA::io

Definition at line 75 of file dt_constants.hh.

◆ ip0

Bitfield<8> MipsISA::ip0

Definition at line 193 of file pra_constants.hh.

◆ ip1

Bitfield<9> MipsISA::ip1

Definition at line 192 of file pra_constants.hh.

◆ ip2

Bitfield<10> MipsISA::ip2

Definition at line 191 of file pra_constants.hh.

◆ ip3

Bitfield<11> MipsISA::ip3

Definition at line 190 of file pra_constants.hh.

◆ ip4

Bitfield<12> MipsISA::ip4

Definition at line 189 of file pra_constants.hh.

◆ ip5

Bitfield<13> MipsISA::ip5

Definition at line 188 of file pra_constants.hh.

◆ ip6

Bitfield<14> MipsISA::ip6

Definition at line 187 of file pra_constants.hh.

Referenced by Net::__tu_cksum6(), Net::hsplit(), IGbE::RxDescCache::pktComplete(), and IGbE::TxDescCache::pktComplete().

◆ ipl

Bitfield<15, 10> MipsISA::ipl

Definition at line 120 of file pra_constants.hh.

◆ ippci

Bitfield<28, 26> MipsISA::ippci

Definition at line 144 of file pra_constants.hh.

◆ ipti

MipsISA::ipti

Definition at line 143 of file pra_constants.hh.

◆ is

◆ iv

Bitfield<23> MipsISA::iv

Definition at line 181 of file pra_constants.hh.

◆ ixmt

Bitfield<10> MipsISA::ixmt

Definition at line 91 of file mt_constants.hh.

◆ k

Bitfield< 1 > MipsISA::k

Definition at line 78 of file dt_constants.hh.

Referenced by MipsISA::ISA::clear(), Profiler::collateStats(), Debug::CompoundFlag::disable(), Debug::CompoundFlag::enable(), Debug::CompoundFlag::enabled(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), SparcISA::TlbMap::erase(), Gcn3ISA::Inst_VOP2__V_MADMK_F32::execute(), Gcn3ISA::Inst_VOP2__V_MADAK_F32::execute(), Topology::extend_shortest_path(), FUPool::FUPool(), sc_dt::sc_subref_r< X >::get_bit(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_subref_r< X >::get_word(), MultiperspectivePerceptron::ACYCLIC::getHash(), MultiperspectivePerceptron::MODHIST::getHash(), MultiperspectivePerceptron::RECENCY::getHash(), MultiperspectivePerceptron::PATH::getHash(), MultiperspectivePerceptron::GHISTPATH::getHash(), RubyPrefetcher::initializeStream(), GPUStaticInst::numDstVecOperands(), GPUStaticInst::numSrcVecOperands(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_subref_r< X >::set_word(), ComputeUnit::startWavefront(), CompressedTags::tagsInit(), SectorTags::tagsInit(), TEST(), and MultiperspectivePerceptron::ThreadData::ThreadData().

◆ k0

Bitfield<2, 0> MipsISA::k0

Definition at line 226 of file pra_constants.hh.

Referenced by ArmISA::addPAC(), and ArmISA::auth().

◆ k23

Bitfield<30, 28> MipsISA::k23

Definition at line 217 of file pra_constants.hh.

◆ ksu

Bitfield<4, 3> MipsISA::ksu

Definition at line 134 of file pra_constants.hh.

◆ ku

Bitfield<27, 25> MipsISA::ku

Definition at line 218 of file pra_constants.hh.

◆ l

Bitfield<5> MipsISA::l

Definition at line 320 of file pra_constants.hh.

Referenced by ProbePointArg< BaseCache::DataUpdate >::addListener(), PerfectSwitch::addOutPort(), sc_dt::sc_uint_base::check_range(), sc_dt::sc_int_base::check_range(), sc_dt::sc_unsigned::check_range(), sc_dt::sc_signed::check_range(), CacheBlk::checkWrite(), CacheBlk::clearLoadLocks(), Topology::createLinks(), sc_dt::scfx_rep::get_slice(), MultiperspectivePerceptron::RECENCYPOS::hash(), sc_core::sc_inout< sc_dt::sc_logic >::initialize(), sc_dt::sc_uint_base::invalid_range(), sc_dt::sc_int_base::invalid_range(), sc_dt::sc_unsigned::invalid_range(), sc_dt::sc_signed::invalid_range(), MemChecker::ByteTracker::lastCompletedTransaction(), Topology::makeLink(), ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo(), tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types >::nb_transport_bw(), ProbePointArg< BaseCache::DataUpdate >::notify(), operator!=(), PCEventQueue::MapCompare::operator()(), Stats::operator*(), operator+(), Stats::operator+(), operator-(), Stats::operator-(), Stats::operator/(), operator<(), operator<=(), sc_core::sc_out_resolved::operator=(), sc_core::sc_inout_resolved::operator=(), sc_core::sc_out_rv< W >::operator=(), sc_core::sc_inout_rv< W >::operator=(), sc_core::sc_signal_resolved::operator=(), sc_core::sc_signal_rv< W >::operator=(), sc_core::sc_inout< sc_dt::sc_logic >::operator=(), operator==(), operator>(), operator>=(), MathExpr::parse(), SparcISA::SparcStaticInst::passesFpCondition(), RubyPort::PioResponsePort::recvAtomic(), RubyPort::PioResponsePort::recvTimingReq(), ProbePointArg< BaseCache::DataUpdate >::removeListener(), PhysicalMemory::serialize(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_concref_r< X, Y >::set_word(), UnifiedRenameMap::switchMode(), TEST_F(), RegisterBankTest::TestReg::TestReg(), CacheBlk::trackLoadLocked(), WalkCache::WalkCacheStats::WalkCacheStats(), sc_core::sc_signal_resolved::write(), sc_core::sc_signal_rv< W >::write(), sc_core::sc_inout< sc_dt::sc_logic >::write(), CoherentXBar::~CoherentXBar(), NoncoherentXBar::~NoncoherentXBar(), and ProbeListenerObject::~ProbeListenerObject().

◆ lpa

Bitfield<7> MipsISA::lpa

Definition at line 264 of file pra_constants.hh.

◆ lsnm

Bitfield<28> MipsISA::lsnm

Definition at line 42 of file dt_constants.hh.

◆ mask

Bitfield< 11, 3 > MipsISA::mask

Definition at line 70 of file pra_constants.hh.

Referenced by MipsISA::ISA::configCP(), readDSPControl(), and writeDSPControl().

◆ maskx

Bitfield<12, 11> MipsISA::maskx

Definition at line 71 of file pra_constants.hh.

◆ MaxShadowRegSets

const int MipsISA::MaxShadowRegSets = 16

Definition at line 49 of file registers.hh.

◆ mcheckep

Bitfield<23> MipsISA::mcheckep

Definition at line 47 of file dt_constants.hh.

◆ md

Bitfield<5> MipsISA::md

Definition at line 239 of file pra_constants.hh.

◆ MIPS32_QNAN

const uint32_t MipsISA::MIPS32_QNAN = 0x7fbfffff

Definition at line 58 of file registers.hh.

◆ MIPS64_QNAN

const uint64_t MipsISA::MIPS64_QNAN = ULL(0x7ff7ffffffffffff)

Definition at line 59 of file registers.hh.

◆ mmuSize

Bitfield<30, 25> MipsISA::mmuSize

Definition at line 231 of file pra_constants.hh.

◆ mode

Bitfield<11, 7> MipsISA::mode

Definition at line 95 of file dt_constants.hh.

Referenced by dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMuleq(), dspMuleu(), dspPrece(), and MipsISA::TLB::translateTiming().

◆ mt

Bitfield< 2 > MipsISA::mt

Definition at line 223 of file pra_constants.hh.

◆ mvp

Bitfield<1> MipsISA::mvp

Definition at line 70 of file mt_constants.hh.

◆ mx

Bitfield<24> MipsISA::mx

Definition at line 112 of file pra_constants.hh.

◆ nmi

Bitfield<19> MipsISA::nmi

Definition at line 117 of file pra_constants.hh.

◆ nodcr

Bitfield<29> MipsISA::nodcr

Definition at line 41 of file dt_constants.hh.

◆ nosst

Bitfield<9> MipsISA::nosst

Definition at line 59 of file dt_constants.hh.

◆ NumCCRegs

const int MipsISA::NumCCRegs = 0

Definition at line 56 of file registers.hh.

Referenced by copyRegs().

◆ NumFloatArchRegs

const int MipsISA::NumFloatArchRegs = 32

Definition at line 46 of file registers.hh.

◆ NumFloatRegs

const int MipsISA::NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

Definition at line 51 of file registers.hh.

Referenced by copyRegs().

◆ NumFloatSpecialRegs

const int MipsISA::NumFloatSpecialRegs = 5

Definition at line 47 of file registers.hh.

◆ NumIntArchRegs

const int MipsISA::NumIntArchRegs = 32

Definition at line 44 of file registers.hh.

◆ NumIntRegs

const int MipsISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

Definition at line 50 of file registers.hh.

Referenced by copyRegs().

◆ NumIntSpecialRegs

const int MipsISA::NumIntSpecialRegs = 9

Definition at line 45 of file registers.hh.

◆ NumMiscRegs

const int MipsISA::NumMiscRegs = MISCREG_NUMREGS

Definition at line 269 of file registers.hh.

Referenced by MipsISA::ISA::clear(), copyRegs(), and MipsISA::ISA::ISA().

◆ NumVecElemPerVecReg

constexpr unsigned MipsISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

constexpr

Definition at line 276 of file registers.hh.

◆ NumVecPredRegs

const int MipsISA::NumVecPredRegs = 1

Definition at line 54 of file registers.hh.

◆ NumVecRegs

const int MipsISA::NumVecRegs = 1

Definition at line 52 of file registers.hh.

◆ offline

Bitfield<7> MipsISA::offline

Definition at line 61 of file dt_constants.hh.

◆ on

Bitfield<0> MipsISA::on

Definition at line 87 of file dt_constants.hh.

Referenced by sc_gem5::Scheduler::deschedule(), sc_core::sc_trace_delta_cycles(), and sc_gem5::TraceFile::traceDeltas().

◆ p

Bitfield<0> MipsISA::p

Definition at line 323 of file pra_constants.hh.

◆ paco

Bitfield<0> MipsISA::paco

Definition at line 130 of file dt_constants.hh.

◆ PageBytes

const Addr MipsISA::PageBytes = ULL(1) << PageShift

Definition at line 42 of file isa_traits.hh.

Referenced by MipsProcess::argsInit(), RoundPage(), and TruncPage().

◆ PageShift

const Addr MipsISA::PageShift = 13

Definition at line 41 of file isa_traits.hh.

◆ pc

Bitfield<4> MipsISA::pc

Definition at line 240 of file pra_constants.hh.

◆ pci

Bitfield<26> MipsISA::pci

Definition at line 179 of file pra_constants.hh.

◆ pcp

Bitfield<27> MipsISA::pcp

Definition at line 49 of file mt_constants.hh.

◆ pfn

Bitfield<29, 6> MipsISA::pfn

Definition at line 55 of file pra_constants.hh.

Referenced by ArmISA::TLB::insert().

◆ procId

Bitfield<15, 8> MipsISA::procId

Definition at line 203 of file pra_constants.hh.

Referenced by MipsISA::ISA::configCP().

◆ pss

Bitfield<9, 6> MipsISA::pss

Definition at line 158 of file pra_constants.hh.

◆ pState

Bitfield<7, 6> MipsISA::pState

Definition at line 319 of file pra_constants.hh.

◆ pTagLo

MipsISA::pTagLo

Definition at line 318 of file pra_constants.hh.

◆ ptc

Bitfield<7, 0> MipsISA::ptc

Definition at line 53 of file mt_constants.hh.

Referenced by X86Linux::archClone(), ArmLinux::archClone(), RiscvLinux64::archClone(), SparcLinux::archClone(), ArmLinux32::archClone(), RiscvLinux32::archClone(), and ArmLinux64::archClone().

◆ pteBase

MipsISA::pteBase

Definition at line 63 of file pra_constants.hh.

◆ ptlbe

Bitfield<25, 16> MipsISA::ptlbe

Definition at line 50 of file mt_constants.hh.

◆ pvpe

Bitfield<13, 10> MipsISA::pvpe

Definition at line 52 of file mt_constants.hh.

◆ px

Bitfield<23> MipsISA::px

Definition at line 113 of file pra_constants.hh.

Referenced by sc_dt::sc_proxy< sc_bv_base >::and_reduce(), sc_dt::sc_lv_base::clean_tail(), sc_dt::operator&=(), sc_dt::operator^=(), and sc_dt::operator|=().

◆ r

Bitfield< 1 > MipsISA::r

Definition at line 95 of file pra_constants.hh.

Referenced by __to_number(), sc_gem5::ScSignalBaseBinary::_signalReset(), ThermalModel::addReference(), ThermalModel::addResistor(), AddrRange::AddrRange(), DRAMInterface::allRanksDrained(), Set::AND(), BPredUnit::BPredUnit(), LSQ< Impl >::SplitDataRequest::buildPackets(), sc_dt::sc_uint_base::check_range(), sc_dt::sc_int_base::check_range(), sc_dt::sc_unsigned::check_range(), sc_dt::sc_signed::check_range(), ArmISA::TLB::checkPermissions64(), AddrRangeMap< AbstractMemory *, 1 >::contains(), ArmISA::decodeMrsMsrBankedIntRegIndex(), ArmISA::decodeMrsMsrBankedReg(), DirectoryMemory::DirectoryMemory(), Loader::doGzipLoad(), DRAMInterface::drainRanks(), sc_gem5::Port::finalize(), SparcISA::TlbMap::find(), AddrRangeMap< AbstractMemory *, 1 >::find(), Stats::Formula::Formula(), ArmISA::fp64_sqrt(), RubyPort::PioResponsePort::getAddrRanges(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::getBackdoor(), PhysicalMemory::getConfAddrRanges(), Sequencer::getHitTypeMachLatencyHist(), Sequencer::getMissTypeMachLatencyHist(), GPUCoalescer::getMissTypeMachLatencyHist(), ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), LSQ< Impl >::SplitDataRequest::handleLocalAccess(), LSQ< Impl >::SplitDataRequest::initiateTranslation(), BaseCache::inRange(), SparcISA::TlbMap::insert(), AddrRangeMap< AbstractMemory *, 1 >::insert(), SparcISA::TlbMap::intersect(), Set::intersectionIsEmpty(), VMA::intersects(), AddrRangeMap< AbstractMemory *, 1 >::intersects(), AddrRange::intersects(), sc_dt::sc_uint_base::invalid_range(), sc_dt::sc_int_base::invalid_range(), sc_dt::sc_unsigned::invalid_range(), sc_dt::sc_signed::invalid_range(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::invalidate_direct_mem_ptr(), sc_dt::scfx_ieee_float::is_inf(), sc_dt::scfx_ieee_float::is_nan(), QTIsaac< ALPHA >::isaac(), DRAMInterface::isBusy(), LSQ< Impl >::SplitDataRequest::isCacheBlockHit(), DirectoryMemory::isPresent(), VMA::isStrictSuperset(), VMA::isSubset(), AddrRange::isSubset(), Set::isSuperset(), lookupTraceForAddress(), sc_gem5::ScMainFiber::main(), DirectoryMemory::mapAddressToLocalIdx(), VMA::mergesWith(), AddrRange::mergesWith(), operator!=(), AddrRange::operator!=(), PCEventQueue::MapCompare::operator()(), Stats::operator*(), operator+(), Stats::operator+(), Stats::Formula::operator+=(), operator-(), Stats::operator-(), Stats::operator/(), Stats::Formula::operator/=(), operator<(), AddrRange::operator<(), operator<=(), sc_core::sc_report::operator=(), sc_core::sc_signal_resolved::operator=(), sc_core::sc_signal_rv< W >::operator=(), RefCountingPtr< MinorDynInst >::operator=(), Stats::Formula::operator=(), operator==(), AddrRange::operator==(), operator>(), operator>=(), Set::OR(), MathExpr::parse(), PersistentTable::persistentRequestLock(), PhysicalMemory::PhysicalMemory(), QTIsaac< ALPHA >::randinit(), MemBackdoor::range(), MemBackdoor::readable(), ArmISA::recipEstimate(), ArmISA::recipSqrtEstimate(), RubyPort::PioRequestPort::recvRangeChange(), BaseXBar::recvRangeChange(), RefCountingPtr< MinorDynInst >::RefCountingPtr(), sc_gem5::reportifyException(), ArmSemihosting::retOK(), QTIsaac< ALPHA >::rngstep(), SC_MODULE(), Cache::sendMSHRQueuePacket(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), ArmISA::ISA::setMiscReg(), PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), LSQUnit< Impl >::LSQEntry::setRequest(), DRAMInterface::startup(), DRAMInterface::suspend(), LSQ< Impl >::LSQRequest::taskId(), TEST(), TEST_F(), RegisterBankTest::TestReg::TestReg(), LinearSystem::toStr(), sc_dt::vec_div_small(), VMA::VMA(), and LSQ< Impl >::LSQRequest::~LSQRequest().

◆ r0

Bitfield<3> MipsISA::r0

Definition at line 136 of file pra_constants.hh.

Referenced by ArmISA::lsl128(), and ArmISA::lsr128().

◆ random

MipsISA::random

Definition at line 50 of file pra_constants.hh.

Referenced by StreamGen::create(), AddressManager::getAtomicLoc(), AddressManager::AtomicStruct::getLoadLoc(), AddressManager::AtomicStruct::getStoreLoc(), Episode::initActions(), TesterThread::issueNewEpisode(), and StatTest::run().

◆ re

Bitfield<25> MipsISA::re

Definition at line 111 of file pra_constants.hh.

◆ ReturnValueReg

const int MipsISA::ReturnValueReg = 2

Definition at line 106 of file registers.hh.

Referenced by GuestABI::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store().

◆ rev

Bitfield<7, 0> MipsISA::rev

Definition at line 204 of file pra_constants.hh.

◆ ripl

Bitfield<15, 10> MipsISA::ripl

Definition at line 184 of file pra_constants.hh.

◆ rnst

Bitfield<24, 23> MipsISA::rnst

Definition at line 84 of file mt_constants.hh.

◆ s

Bitfield< 2 > MipsISA::s

Definition at line 79 of file dt_constants.hh.

◆ sa

Bitfield<3, 0> MipsISA::sa

Definition at line 256 of file pra_constants.hh.

Referenced by dspExtr(), dspMulq(), dspPrece(), dspPrecrSra(), dspShll(), dspShra(), and dspShrl().

◆ scs

Bitfield<18> MipsISA::scs

Definition at line 67 of file mt_constants.hh.

◆ SIMD_LOG2N

const uint32_t MipsISA::SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }

Definition at line 99 of file dsp.hh.

Referenced by dspShll(), dspShra(), and dspShrl().

◆ SIMD_MAX_VALS

const uint32_t MipsISA::SIMD_MAX_VALS = 4

Definition at line 93 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsa(), dspMulsaq(), dspPack(), dspPick(), dspPrece(), dspPrecrq(), dspPrecrqu(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), and dspSubh().

◆ SIMD_NBITS

const uint32_t MipsISA::SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }

Definition at line 97 of file dsp.hh.

Referenced by dspMulq(), dspPrece(), dspPrecrqu(), signExtend(), simdPack(), and simdUnpack().

◆ SIMD_NVALS

const uint32_t MipsISA::SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }

Definition at line 95 of file dsp.hh.

Referenced by dspAbs(), dspAdd(), dspAddh(), dspCmp(), dspCmpg(), dspCmpgd(), dspDpa(), dspDpaq(), dspDps(), dspDpsq(), dspMaq(), dspMul(), dspMuleq(), dspMuleu(), dspMulq(), dspMulsaq(), dspPick(), dspPrece(), dspPrecrSra(), dspShll(), dspShra(), dspShrl(), dspSub(), dspSubh(), simdPack(), and simdUnpack().

◆ sl

Bitfield<7, 4> MipsISA::sl

Definition at line 255 of file pra_constants.hh.

◆ sm

Bitfield<1> MipsISA::sm

Definition at line 270 of file pra_constants.hh.

◆ sp

Bitfield<4> MipsISA::sp

Definition at line 267 of file pra_constants.hh.

◆ sr

Bitfield<20> MipsISA::sr

Definition at line 116 of file pra_constants.hh.

Referenced by DistIface::SyncEvent::process().

◆ ss

Bitfield<11, 8> MipsISA::ss

Definition at line 254 of file pra_constants.hh.

◆ sst

Bitfield<8> MipsISA::sst

Definition at line 60 of file dt_constants.hh.

◆ ssv0

Bitfield<3, 0> MipsISA::ssv0

Definition at line 171 of file pra_constants.hh.

◆ ssv1

Bitfield<7, 4> MipsISA::ssv1

Definition at line 170 of file pra_constants.hh.

◆ ssv2

Bitfield<11, 8> MipsISA::ssv2

Definition at line 169 of file pra_constants.hh.

◆ ssv3

Bitfield<15, 12> MipsISA::ssv3

Definition at line 168 of file pra_constants.hh.

◆ ssv4

Bitfield<19, 16> MipsISA::ssv4

Definition at line 167 of file pra_constants.hh.

◆ ssv5

Bitfield<23, 20> MipsISA::ssv5

Definition at line 166 of file pra_constants.hh.

◆ ssv6

Bitfield<27, 24> MipsISA::ssv6

Definition at line 165 of file pra_constants.hh.

◆ ssv7

MipsISA::ssv7

Definition at line 164 of file pra_constants.hh.

◆ StackPointerReg

const int MipsISA::StackPointerReg = 29

Definition at line 108 of file registers.hh.

◆ stlb

Bitfield<2> MipsISA::stlb

Definition at line 40 of file mt_constants.hh.

◆ su

Bitfield<15, 12> MipsISA::su

Definition at line 253 of file pra_constants.hh.

◆ sx

Bitfield<6> MipsISA::sx

Definition at line 132 of file pra_constants.hh.

◆ syp

Bitfield<2, 0> MipsISA::syp

Definition at line 99 of file dt_constants.hh.

◆ SyscallPseudoReturnReg

const int MipsISA::SyscallPseudoReturnReg = 3

Definition at line 110 of file registers.hh.

Referenced by GuestABI::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store().

◆ SyscallSuccessReg

const int MipsISA::SyscallSuccessReg = 7

Definition at line 104 of file registers.hh.

Referenced by GuestABI::Result< MipsISA::SEWorkload::SyscallABI, SyscallReturn >::store().

◆ ta

Bitfield<19, 16> MipsISA::ta

Definition at line 252 of file pra_constants.hh.

◆ targTC

Bitfield<7, 0> MipsISA::targTC

Definition at line 60 of file mt_constants.hh.

◆ tb

Bitfield<27> MipsISA::tb

Definition at line 74 of file dt_constants.hh.

Referenced by SC_MODULE().

◆ tbe

Bitfield<17> MipsISA::tbe

Definition at line 77 of file mt_constants.hh.

Referenced by SparcISA::TLB::translateFunctional().

◆ tbi

Bitfield<4> MipsISA::tbi

Definition at line 97 of file dt_constants.hh.

◆ tbu

Bitfield<3> MipsISA::tbu

Definition at line 98 of file dt_constants.hh.

◆ tca

Bitfield<15> MipsISA::tca

Definition at line 51 of file mt_constants.hh.

◆ tcnum

Bitfield<19, 12> MipsISA::tcnum

Definition at line 94 of file dt_constants.hh.

◆ tcs

Bitfield<19> MipsISA::tcs

Definition at line 66 of file mt_constants.hh.

◆ tcu

MipsISA::tcu

Definition at line 82 of file mt_constants.hh.

◆ tcv

Bitfield<20> MipsISA::tcv

Definition at line 93 of file dt_constants.hh.

◆ tds

Bitfield<21> MipsISA::tds

Definition at line 85 of file mt_constants.hh.

◆ te

Bitfield<15> MipsISA::te

Definition at line 59 of file mt_constants.hh.

◆ tfcr

Bitfield<3> MipsISA::tfcr

Definition at line 84 of file dt_constants.hh.

◆ ti

Bitfield<30> MipsISA::ti

Definition at line 176 of file pra_constants.hh.

Referenced by ArmISA::DumpStats::getTaskDetails(), ArmISA::DumpStats64::getTaskDetails(), and ArmISA::TLB::setTestInterface().

◆ tim

Bitfield<1> MipsISA::tim

Definition at line 86 of file dt_constants.hh.

◆ tksu

Bitfield<12, 11> MipsISA::tksu

Definition at line 90 of file mt_constants.hh.

◆ tl

Bitfield< 0 > MipsISA::tl

Definition at line 251 of file pra_constants.hh.

Referenced by SparcISA::copyMiscRegs(), SparcISA::SparcFaultBase::invoke(), SparcISA::TLB::translateData(), and SparcISA::TLB::translateInst().

◆ tlbs

Bitfield<29> MipsISA::tlbs

Definition at line 47 of file mt_constants.hh.

◆ tlsm

Bitfield<2> MipsISA::tlsm

Definition at line 85 of file dt_constants.hh.

◆ tmx

Bitfield<27> MipsISA::tmx

Definition at line 83 of file mt_constants.hh.

◆ ts

Bitfield< 27, 24 > MipsISA::ts

Definition at line 115 of file pra_constants.hh.

◆ tu

Bitfield<30, 28> MipsISA::tu

Definition at line 249 of file pra_constants.hh.

Referenced by sc_core::sc_event_queue::notify(), sc_core::sc_set_default_time_unit(), sc_core::sc_set_time_resolution(), sc_core::sc_time::sc_time(), and sc_gem5::TraceFile::set_time_unit().

◆ tup

Bitfield<1> MipsISA::tup

Definition at line 129 of file dt_constants.hh.

◆ u

Bitfield< 3 > MipsISA::u

Definition at line 80 of file dt_constants.hh.

◆ um

Bitfield<4> MipsISA::um

Definition at line 135 of file pra_constants.hh.

◆ ut

Bitfield<30> MipsISA::ut

Definition at line 73 of file dt_constants.hh.

◆ ux

Bitfield<5> MipsISA::ux

Definition at line 133 of file pra_constants.hh.

Referenced by floorLog2().

◆ v

Bitfield<1> MipsISA::v

Definition at line 58 of file pra_constants.hh.

◆ vaddr

MipsISA::vaddr

Definition at line 275 of file pra_constants.hh.

Referenced by Process::allocateMem(), Gcn3ISA::Inst_SMEM::calcAddr(), Gcn3ISA::Inst_MUBUF::calcAddr(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), Process::clone(), BaseMMU::demapPage(), SimpleThread::demapPage(), FullO3CPU< O3CPUImpl >::demapPage(), BaseDynInst< Impl >::demapPage(), Minor::ExecContext::demapPage(), CheckerCPU::demapPage(), SimpleExecContext::demapPage(), DefaultFetch< Impl >::fetchCacheLine(), FetchUnit::FetchBufDesc::fetchDone(), Process::fixupFault(), MemState::fixupFault(), ArmISA::TLB::getTE(), X86ISA::GpuTLB::handleFuncTranslationReturn(), X86ISA::GpuTLB::handleTranslationReturn(), FetchUnit::initiateFetch(), Gcn3ISA::Inst_DS::initMemRead(), initMemReqHelper(), initMemReqScalarHelper(), Gcn3ISA::Inst_DS::initMemWrite(), ArmISA::BrkPoint::isActive(), FetchUnit::FetchBufDesc::isReserved(), EmulationPageTable::isUnmapped(), EmulationPageTable::lookup(), EmulationPageTable::map(), Process::map(), MultiLevelPageTable< EntryTypes >::map(), X86ISA::LongModePTE::read(), BaseRemoteGDB::read(), PseudoInst::readfile(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), ComputeUnit::DTLBPort::recvTimingResp(), EmulationPageTable::remap(), MultiLevelPageTable< EntryTypes >::remap(), Process::replicatePage(), Request::Request(), FetchUnit::FetchBufDesc::reserveBuf(), FetchUnit::FetchBufDesc::reservedBuf(), ComputeUnit::sendRequest(), X86ISA::Walker::WalkerState::setupWalk(), ArmISA::Stage2MMU::Stage2Translation::setVirt(), LSQ< Impl >::LSQRequest::setVirt(), Request::setVirt(), X86ISA::Walker::WalkerState::stepWalk(), ArmISA::SelfDebug::testBreakPoints(), ArmISA::BrkPoint::testLinkedBk(), ArmISA::SelfDebug::testWatchPoints(), SparcISA::TlbEntry::TlbEntry(), X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), EmulationPageTable::translate(), X86ISA::GpuTLB::translate(), SparcISA::PageTableEntry::translate(), FastModel::CortexR52TC::translateAddress(), FastModel::CortexA76TC::translateAddress(), Iris::ThreadContext::translateAddress(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFs(), Iris::TLB::translateFunctional(), ArmISA::MMU::translateFunctional(), X86ISA::TLB::translateFunctional(), SparcISA::TLB::translateFunctional(), SparcISA::TLB::translateInst(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), ArmISA::TLB::translateMmuOff(), ArmISA::TLB::translateMmuOn(), HSADevice::translateOrDie(), HSAPacketProcessor::translateOrDie(), ArmISA::TLB::translateSe(), X86ISA::GpuTLB::translationReturn(), ArmISA::SelfDebug::triggerException(), ArmISA::SelfDebug::triggerWatchpointException(), EmulationPageTable::unmap(), MultiLevelPageTable< EntryTypes >::unmap(), EmulationPageTable::unserialize(), BaseRemoteGDB::write(), and PseudoInst::writefile().

◆ validModes

Bitfield<6, 5> MipsISA::validModes

Definition at line 96 of file dt_constants.hh.

◆ VecPredRegHasPackedRepr

constexpr bool MipsISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

constexpr

Definition at line 284 of file registers.hh.

◆ VecPredRegSizeBits

constexpr size_t MipsISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

constexpr

Definition at line 283 of file registers.hh.

◆ VecRegSizeBytes

constexpr size_t MipsISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

constexpr

Definition at line 277 of file registers.hh.

◆ veic

Bitfield<6> MipsISA::veic

Definition at line 265 of file pra_constants.hh.

◆ vi

Bitfield<3> MipsISA::vi

Definition at line 225 of file pra_constants.hh.

◆ vint

Bitfield<5> MipsISA::vint

Definition at line 266 of file pra_constants.hh.

◆ vpa

Bitfield<0> MipsISA::vpa

Definition at line 71 of file mt_constants.hh.

◆ vpc

Bitfield<1> MipsISA::vpc

Definition at line 41 of file mt_constants.hh.

◆ vpn2

Bitfield<39, 13> MipsISA::vpn2

Definition at line 97 of file pra_constants.hh.

◆ vpn2x

Bitfield<12, 11> MipsISA::vpn2x

Definition at line 98 of file pra_constants.hh.

◆ vs

Bitfield<9, 5> MipsISA::vs

Definition at line 146 of file pra_constants.hh.

Referenced by sc_dt::compare_unsigned(), sc_dt::operator%(), sc_dt::operator&(), sc_dt::operator+(), sc_dt::operator-(), sc_dt::operator<(), sc_dt::operator==(), sc_dt::operator^(), and sc_dt::operator|().

◆ w

Bitfield< 30 > MipsISA::w

Definition at line 278 of file pra_constants.hh.

Referenced by StaticRegisterManagerPolicy::allocateRegisters(), RegisterManager::allocateRegisters(), sc_dt::sc_bitref< X >::b_not(), sc_dt::sc_proxy< sc_bv_base >::check_bounds(), ArmISA::TLB::checkPermissions64(), ComputeUnit::deleteFromPipeMap(), ScheduleStage::deleteFromSch(), ComputeUnit::dispWorkgroup(), LocalMemPipeline::exec(), ScalarMemPipeline::exec(), GlobalMemPipeline::exec(), ComputeUnit::fillKernelState(), StaticRegisterManagerPolicy::freeRegisters(), RegisterManager::freeRegisters(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::sc_subref_r< X >::get_word(), PowerModel::getDynamicPower(), MultiperspectivePerceptron::GHISTPATH::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), PowerModel::getStaticPower(), StatisticalCorrector::gPredict(), StatisticalCorrector::gUpdate(), StatisticalCorrector::initGEHLTable(), ComputeUnit::insertInPipeMap(), sc_dt::sc_bv_base::is_01(), StaticRegisterManagerPolicy::mapSgpr(), RegisterManager::mapSgpr(), StaticRegisterManagerPolicy::mapVgpr(), RegisterManager::mapVgpr(), ScoreboardCheckStage::mapWaveToExeUnit(), ComputeUnit::mapWaveToScalarAlu(), ComputeUnit::mapWaveToScalarAluGlobalIdx(), VectorRegisterFile::operandsReady(), ScalarRegisterFile::operandsReady(), sc_dt::sc_lv_base::operator=(), sc_gem5::VcdTraceScope::output(), sc_gem5::VcdTraceValFinite< T >::output(), sc_gem5::VcdTraceValFxnum< T >::output(), sc_gem5::VcdTraceValInt< T >::output(), ScoreboardCheckStage::ready(), ComputeUnit::DataPort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), ComputeUnit::ScalarDTLBPort::recvTimingResp(), FutexMap::requeue(), SC_MODULE(), sc_dt::sc_proxy< sc_bv_base >::scan(), sc_gem5::ScEvent::schedule(), VectorRegisterFile::scheduleWriteOperands(), ScalarRegisterFile::scheduleWriteOperands(), VectorRegisterFile::scheduleWriteOperandsFromLoad(), ScalarRegisterFile::scheduleWriteOperandsFromLoad(), sc_dt::sc_bitref< X >::set_bit(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_word(), Packet::setUintX(), ComputeUnit::startWavefront(), sc_dt::sc_proxy< sc_bv_base >::to_uint64(), sc_dt::vec_mul_small_on(), sc_dt::vec_sub_on2(), VectorRegisterFile::waveExecuteInst(), ScalarRegisterFile::waveExecuteInst(), sc_gem5::ScEvent::when(), MemBackdoor::writeable(), and VGic::writeVCpu().

◆ wired

MipsISA::wired

Definition at line 86 of file pra_constants.hh.

◆ wp

Bitfield<22> MipsISA::wp

Definition at line 182 of file pra_constants.hh.

◆ wr

Bitfield<3> MipsISA::wr

Definition at line 241 of file pra_constants.hh.

Referenced by SC_MODULE().

◆ xtc

Bitfield<28, 21> MipsISA::xtc

Definition at line 65 of file mt_constants.hh.

◆ ZeroReg

const int MipsISA::ZeroReg = 0

Definition at line 103 of file registers.hh.

Classes

Typedefs

Enumerations

Functions

Variables

Typedef Documentation

◆ ConstVecPredReg

◆ ConstVecReg

◆ ExtMachInst

◆ FaultVals

◆ FaultVect

◆ MachInst

◆ PCState

◆ VecElem

◆ VecPredReg

◆ VecPredRegContainer

◆ VecReg

◆ VecRegContainer

Enumeration Type Documentation

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ anonymous enum

◆ ConvertType

◆ ExcCode

◆ FCSRBits

◆ FCSRFields

◆ FPControlRegNums

◆ InterruptLevels

◆ MiscIntRegNums

◆ MiscRegIndex

◆ RoundMode

Function Documentation

◆ addHalfLsb()

◆ advancePC()

◆ bitrev()

◆ BitUnion32() [1/3]

◆ BitUnion32() [2/3]

◆ BitUnion32() [3/3]

◆ buildRetPC()

◆ checkOverflow()

◆ copyMiscRegs()

◆ copyRegs()

◆ dspAbs()

◆ dspAdd()

◆ dspAddh()

◆ dspCmp()

◆ dspCmpg()

◆ dspCmpgd()

◆ dspDpa()

◆ dspDpaq()

◆ dspDps()

◆ dspDpsq()

◆ dspExtp()

◆ dspExtpd()

◆ dspExtr()

◆ dspMaq()

◆ dspMul()

◆ dspMuleq()

◆ dspMuleu()

◆ dspMulq()

◆ dspMulsa()

◆ dspMulsaq()

◆ dspPack()

◆ dspPick()

◆ dspPrece()

◆ dspPrecrq()

◆ dspPrecrqu()

◆ dspPrecrSra()

◆ dspSaturate()

◆ dspShll()

◆ dspShra()

◆ dspShrl()

◆ dspSub()

◆ dspSubh()

◆ EndBitUnion() [1/35]

◆ EndBitUnion() [2/35]