gem5  v21.0.1.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
registers.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved.
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are
17  * met: redistributions of source code must retain the above copyright
18  * notice, this list of conditions and the following disclaimer;
19  * redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in the
21  * documentation and/or other materials provided with the distribution;
22  * neither the name of the copyright holders nor the names of its
23  * contributors may be used to endorse or promote products derived from
24  * this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #ifndef __ARCH_X86_REGISTERS_HH__
40 #define __ARCH_X86_REGISTERS_HH__
41 
43 #include "arch/generic/vec_reg.hh"
44 #include "arch/x86/regs/int.hh"
45 #include "arch/x86/regs/ccr.hh"
46 #include "arch/x86/regs/misc.hh"
47 #include "arch/x86/x86_traits.hh"
48 
49 namespace X86ISA
50 {
51 
53 
56 const int NumCCRegs = NUM_CCREGS;
57 
58 // Each 128 bit xmm register is broken into two effective 64 bit registers.
59 // Add 8 for the indices that are mapped over the fp stack
60 const int NumFloatRegs =
62 
63 // These enumerate all the registers for dependence tracking.
65  // FP_Reg_Base must be large enough to be bigger than any integer
66  // register index which has the IntFoldBit (1 << 6) set. To be safe
67  // we just start at (1 << 7) == 128.
68  FP_Reg_Base = 128,
72 };
73 
74 const int NumVecRegs = 1; // Not applicable to x86
75  // (1 to prevent warnings)
76 const int NumVecPredRegs = 1; // Not applicable to x86
77  // (1 to prevent warnings)
78 
79 // semantically meaningful register indices
80 //There is no such register in X86
81 const int ZeroReg = NUM_INTREGS;
82 const int StackPointerReg = INTREG_RSP;
83 
84 // Not applicable to x86
91 
92 // Not applicable to x86
98 
99 } // namespace X86ISA
100 
101 #endif // __ARCH_X86_REGFILE_HH__
DummyVecRegSizeBytes
constexpr size_t DummyVecRegSizeBytes
Definition: vec_reg.hh:669
x86_traits.hh
X86ISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:55
DummyVecPredRegSizeBits
constexpr size_t DummyVecPredRegSizeBits
Definition: vec_pred_reg.hh:398
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
X86ISA::NumVecPredRegs
const int NumVecPredRegs
Definition: registers.hh:76
DummyVecPredRegHasPackedRepr
constexpr bool DummyVecPredRegHasPackedRepr
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:391
X86ISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:52
ccr.hh
X86ISA::NUM_CCREGS
@ NUM_CCREGS
Definition: ccr.hh:53
X86ISA::NumImplicitIntRegs
const int NumImplicitIntRegs
Definition: x86_traits.hh:49
X86ISA::CC_Reg_Base
@ CC_Reg_Base
Definition: registers.hh:69
X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:59
DummyVecPredReg
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, false > DummyVecPredReg
Definition: vec_pred_reg.hh:393
X86ISA::FP_Reg_Base
@ FP_Reg_Base
Definition: registers.hh:68
X86ISA::Max_Reg_Index
@ Max_Reg_Index
Definition: registers.hh:71
DummyVecRegContainer
DummyVecReg::Container DummyVecRegContainer
Definition: vec_reg.hh:668
X86ISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:89
X86ISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:398
X86ISA::Misc_Reg_Base
@ Misc_Reg_Base
Definition: registers.hh:70
VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:66
DummyConstVecReg
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, true > DummyConstVecReg
Definition: vec_reg.hh:667
X86ISA::VecRegSizeBytes
constexpr size_t VecRegSizeBytes
Definition: registers.hh:90
X86ISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:60
int.hh
DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:664
vec_pred_reg.hh
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
DummyVecReg
VecRegT< DummyVecElem, DummyNumVecElemPerVecReg, false > DummyVecReg
Definition: vec_reg.hh:666
DummyVecPredRegContainer
DummyVecPredReg::Container DummyVecPredRegContainer
Definition: vec_pred_reg.hh:397
X86ISA::DependenceTags
DependenceTags
Definition: registers.hh:64
X86ISA::ZeroReg
const int ZeroReg
Definition: registers.hh:81
X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:58
X86ISA::NumIntArchRegs
const int NumIntArchRegs
Definition: registers.hh:54
vec_reg.hh
X86ISA::VecElem
::DummyVecElem VecElem
Definition: registers.hh:85
X86ISA::VecPredRegHasPackedRepr
constexpr bool VecPredRegHasPackedRepr
Definition: registers.hh:97
X86ISA::VecPredRegSizeBits
constexpr size_t VecPredRegSizeBits
Definition: registers.hh:96
DummyConstVecPredReg
VecPredRegT< DummyVecElem, DummyNumVecElemPerVecReg, DummyVecPredRegHasPackedRepr, true > DummyConstVecPredReg
Definition: vec_pred_reg.hh:396
ArmISA::NUM_INTREGS
@ NUM_INTREGS
Definition: intregs.hh:123
DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:665
X86ISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: x86_traits.hh:47
misc.hh
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
X86ISA::NumVecRegs
const int NumVecRegs
Definition: registers.hh:74
X86ISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:82
X86ISA::NumCCRegs
const int NumCCRegs
Definition: registers.hh:56
VecRegT
Vector Register Abstraction This generic class is a view in a particularization of MVC,...
Definition: vec_reg.hh:170
X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:57

Generated on Tue Jun 22 2021 15:28:21 for gem5 by doxygen 1.8.17