- h -

• H3() : BloomFilter::H3
• half_addr() : sc_dt::scfx_mant
• half_at() : sc_dt::scfx_mant
• halt() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , sc_core::sc_module , SimpleThread , ThreadContext
• haltContext() : BaseCPU , BaseKvmCPU , BaseSimpleCPU , FullO3CPU< Impl >
• handleAllocAndUReset() : MPP_TAGE , TAGE_SC_L_TAGE , TAGE_SC_L_TAGE_64KB , TAGE_SC_L_TAGE_8KB , TAGEBase
• handleAsyncInsertions() : EventQueue
• handleAtomicReqMiss() : BaseCache , Cache , NoncoherentCache
• handleBeginReq() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• handleEndResp() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• handleEOI() : X86ISA::I8259
• handleError() : Checker< Impl > , CheckerCPU
• handleEvent() : MaltaIO::RTC , MC146818 , RiscvRTC::RTC , X86ISA::Cmos::X86RTC
• handleEvictions() : BaseCache
• handleFill() : BaseCache
• handleFunctional() : SimpleCache , SimpleMemobj
• handleFuncTranslationReturn() : X86ISA::GpuTLB
• handleInterrupt() : DefaultCommit< Impl >
• handleIOMiscReg32() : X86KvmCPU
• handleKvmExit() : BaseKvmCPU
• handleKvmExitException() : BaseKvmCPU
• handleKvmExitFailEntry() : BaseKvmCPU
• handleKvmExitHypercall() : BaseKvmCPU
• handleKvmExitIO() : BaseKvmCPU , X86KvmCPU
• handleKvmExitIRQWindowOpen() : BaseKvmCPU , X86KvmCPU
• handleKvmExitUnknown() : BaseKvmCPU
• handleLoadableSegment() : Loader::ElfObject
• handleLocalAccess() : LSQ< Impl >::LSQRequest , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest
• handleMemPacket() : ComputeUnit
• handleMemResponse() : Minor::Execute
• handleMessage() : SCMI::AgentChannel , SCMI::BaseProtocol , SCMI::Platform , SCMI::Protocol
• handlePageCrossingLookahead() : Prefetcher::SignaturePath , Prefetcher::SignaturePathV2
• handlePending() : DmaReadFifo
• handlePendingInt() : Checker< Impl >
• handleReadDMA() : HSAPacketProcessor::SignalState
• handleReadPacket() : TimingSimpleCPU
• handleRequest() : BaseMemProbe , MemFootprintProbe , MemTraceProbe , SimpleCache , SimpleMemobj , StackDistProbe
• handleResp() : DmaPort
• handleResponse() : GlobalMemPipeline , SimpleCache , SimpleMemobj
• handleRespPacket() : DmaPort
• handleSignatureTableMiss() : Prefetcher::SignaturePath , Prefetcher::SignaturePathV2
• handleSnoop() : Cache , MSHR
• handleStream() : GenericTimer
• handleTAGEUpdate() : MPP_TAGE , TAGE_SC_L_TAGE , TAGE_SC_L_TAGE_64KB , TAGE_SC_L_TAGE_8KB , TAGEBase
• handleTimingReqHit() : BaseCache , Cache
• handleTimingReqMiss() : BaseCache , Cache , NoncoherentCache
• handleTLBResponse() : Minor::Fetch1
• handleTranslationReturn() : X86ISA::GpuTLB
• handleTrap() : SparcISA::EmuLinux , SparcISA::SEWorkload
• handleUncacheableWriteResp() : BaseCache
• handleUReset() : MPP_TAGE , TAGE_SC_L_TAGE , TAGEBase
• handleWritePacket() : TimingSimpleCPU
• HardBreakpoint() : HardBreakpoint
• HardwareBreakpoint() : ArmISA::HardwareBreakpoint
• HardwareResource() : TraceCPU::ElasticDataGen::HardwareResource
• has_credit() : OutputUnit , OutVcState
• has_free_vc() : OutputUnit
• has_mm() : tlm::tlm_generic_payload
• has_value() : sc_core::sc_time_tuple
• hasAddress() : Prefetcher::PIF::CompactorEntry
• hasAtomicOpFunctor() : Request
• hasAttr() : KvmDevice
• hasBarrier() : Wavefront
• hasBeenPrefetched() : BaseCache , Prefetcher::Base
• hasBranchTarget() : StaticInst
• hasCompCompleted() : ElasticTrace
• hasContextId() : Request
• hasData() : MemCmd , Packet
• hasDestinationSgpr() : GPUDynInst
• hasDestinationVgpr() : GPUDynInst
• hasDispResources() : ComputeUnit
• hasEl0View() : GenericTimerFrame
• hasExpected() : ExpectedMap< RespType, DataType >
• hasFetchDataToProcess() : FetchUnit::FetchBufDesc
• hasFreeCCRegs() : UnifiedFreeList
• hasFreeFloatRegs() : UnifiedFreeList
• hasFreeIntRegs() : UnifiedFreeList
• hasFreeRegs() : SimpleFreeList
• hasFreeSpace() : FetchUnit::FetchBufDesc
• hasFreeVecElems() : UnifiedFreeList
• hasFreeVecPredRegs() : UnifiedFreeList
• hasFreeVecRegs() : UnifiedFreeList
• hasFromCache() : MSHR
• hash() : BloomFilter::Block , BloomFilter::Bulk , BloomFilter::H3 , BloomFilter::MultiBitSel , MultiperspectivePerceptron::GHIST , MultiperspectivePerceptron::MPPBranchInfo , MultiperspectivePerceptron::RECENCYPOS , Prefetcher::BOP , SkewedAssociative
• hash1() : MultiperspectivePerceptron::MPPBranchInfo
• hash2() : MultiperspectivePerceptron::MPPBranchInfo
• hasHostBuf() : VMA
• hashPC() : MultiperspectivePerceptron::MPPBranchInfo
• hasHtmAbortCause() : Request
• hasInstCount() : Request
• hasInstSeqNum() : Request
• hasInterrupt() : Minor::Execute
• hasKernelIRQChip() : KvmVM
• hasListeners() : ProbePointArg< Arg >
• hasLoadBarrier() : MemDepUnit< MemDepPred, Impl >
• hasLoadBeenSent() : ElasticTrace
• hasLoadCompleted() : ElasticTrace
• hasMoreActions() : Episode
• hasNext() : VirtDescriptor
• hasNonSecureAccess() : GenericTimerFrame
• hasOutstandingEvents() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• hasPacketsInMemSystem() : Minor::LSQ::LSQRequest , Minor::LSQ::SingleDataRequest , Minor::LSQ::SpecialDataRequest , Minor::LSQ::SplitDataRequest
• hasPaddr() : Request
• hasPC() : Prefetcher::Base::PrefetchInfo , Request
• hasPendingUnmaskable() : X86ISA::Interrupts
• hasPostDowngrade() : MSHR
• hasPostInvalidate() : MSHR
• hasReadableVoff() : GenericTimerFrame
• hasReadyInsts() : InstructionQueue< Impl >
• hasReceivedData() : ExpectedMap< RespType, DataType >
• hasReceivedResp() : ExpectedMap< RespType, DataType >
• hasRequest() : BaseDynInst< Impl > , LSQUnit< Impl >::LSQEntry
• hasRequestor() : QoS::MemCtrl
• hasRespData() : Packet
• hasScalarUnit() : Gcn3ISA::GPUISA
• hasSecondDword() : Gcn3ISA::Inst_MTBUF , Gcn3ISA::Inst_SOP1 , Gcn3ISA::Inst_SOP2 , Gcn3ISA::Inst_SOPC , Gcn3ISA::Inst_SOPK , Gcn3ISA::Inst_VOP1 , Gcn3ISA::Inst_VOP2 , Gcn3ISA::Inst_VOP3 , Gcn3ISA::Inst_VOP3_SDST_ENC , Gcn3ISA::Inst_VOPC
• hasSgprRawDependence() : GPUDynInst
• hasSharers() : Packet
• hasSize() : Request
• hasSourceSgpr() : GPUDynInst
• hasSourceVgpr() : GPUDynInst
• hasStalledMsg() : MessageBuffer
• hasStaticSensitivities() : sc_gem5::Process
• hasStoreBarrier() : MemDepUnit< MemDepPred, Impl >
• hasStoreCommitted() : ElasticTrace
• hasStoresToWB() : DefaultIEW< Impl > , LSQ< Impl > , LSQUnit< Impl >
• hasStreamId() : Request
• hasSubstreamId() : Request
• hasTargets() : MSHR , WriteQueueEntry
• hasTLS() : Loader::ElfObject , Loader::ObjectFile
• hasTwoVDD() : DRAMPower
• hasVaddr() : Request
• hasVgprRawDependence() : GPUDynInst
• hasVirtualTimer() : GenericTimerFrame
• haveAsserted() : Gicv3
• haveCrypto() : ArmSystem
• haveEL() : ArmSystem , Gicv3CPUInterface
• haveGICv3CpuIfc() : ArmISA::ISA
• haveLargeAsid64() : ArmISA::TableWalker , ArmSystem
• haveLPAE() : ArmISA::TableWalker , ArmSystem
• haveLSE() : ArmSystem
• havePAN() : ArmSystem
• havePending() : MSHRQueue
• havePendingInterrupts() : Gicv3CPUInterface
• havePosted() : IntrControl
• haveSecEL2() : ArmSystem
• haveSecurity() : ArmSystem
• haveSemihosting() : ArmSystem
• haveSVE() : ArmSystem
• haveTME() : ArmSystem
• haveTokens() : TokenManager , TokenRequestPort
• haveVHE() : ArmSystem
• haveVirtualization() : ArmISA::TableWalker , ArmSystem
• hazard4kCheck() : SMMUTranslationProcess
• hazard4kHold() : SMMUTranslationProcess
• hazard4kRegister() : SMMUTranslationProcess
• hazard4kRelease() : SMMUTranslationProcess
• hazardIdHold() : SMMUTranslationProcess
• hazardIdRegister() : SMMUTranslationProcess
• hazardIdRelease() : SMMUTranslationProcess
• HBFDEntry() : HBFDEntry
• Hdf5() : Stats::Hdf5
• HDLcd() : HDLcd
• HDLcdStats() : HDLcd::HDLcdStats
• hdrLen() : iGbReg::Regs::SRRCTL
• head() : CircularQueue< T >
• headerComplete() : IGbE::TxDescCache
• height() : FrameBuffer
• HelloObject() : HelloObject
• HiFive() : HiFive
• highest() : ArmISA::ISA::MiscRegLUTEntryInitializer
• highestActiveGroup() : Gicv3CPUInterface
• highestActivePriority() : Gicv3CPUInterface
• highestEL() : ArmSystem
• highestELIs64() : ArmSystem
• Histogram() : Histogram , Stats::Histogram
• HistoryEntry() : SimpleIndirectPredictor::HistoryEntry
• HistorySpec() : MultiperspectivePerceptron::HistorySpec
• HistStor() : Stats::HistStor
• hitCallback() : CpuThread , DmaThread , GPUCoalescer , GpuWavefront , RubyDirectedTester , RubyPort::MemResponsePort , RubyTester , Sequencer , TesterThread
• hitExternalSnoop() : BaseDynInst< Impl >
• hlen() : Net::Ip6Hdr , Net::IpHdr
• hlim() : Net::Ip6Hdr
• HMCController() : HMCController
• hostCycles() : BaseKvmTimer
• hostDataAvailable() : PS2Device
• hostDispAddr() : AQLRingBuffer
• hostDispPktAddr() : HSAQueueEntry
• hostNs() : BaseKvmTimer
• hostPaths() : RedirectPath
• hostRead() : PS2Device
• hostRegDataAvailable() : PS2Device
• hostWrite() : PS2Device
• hpmCounterEnabled() : RiscvISA::ISA
• hppiCanPreempt() : Gicv3CPUInterface
• hppviCanPreempt() : Gicv3CPUInterface
• HSADevice() : HSADevice
• HSADriver() : HSADriver
• hsaPacketProc() : HSADevice
• HSAPacketProcessor() : HSAPacketProcessor
• HSAQueueDescriptor() : HSAQueueDescriptor
• HSAQueueEntry() : HSAQueueEntry
• hsaTask() : GPUDispatcher
• htmAbortTransaction() : CacheMemory , CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• htmCallback() : HTMSequencer
• HTMCheckpoint() : ArmISA::HTMCheckpoint
• HtmCmdRequest() : LSQ< Impl >::HtmCmdRequest
• htmCommitTransaction() : CacheMemory
• htmRetCodeConversion() : HTMSequencer
• htmSendAbortSignal() : AtomicSimpleCPU , BaseSimpleCPU , FullO3CPU< Impl > , TimingSimpleCPU
• HTMSequencer() : HTMSequencer
• htmTransactionFailedInCache() : Packet
• htoreg() : RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >
• Huffman() : Compressor::Encoder::Huffman
• HWScheduler() : HWScheduler
• HybridGen() : HybridGen
• hyp() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2H() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2HNonSecureRead() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2HNonSecureWrite() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2HRead() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2HSecureRead() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2HSecureWrite() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypE2HWrite() : ArmISA::ISA::MiscRegLUTEntryInitializer
• HypervisorCall() : ArmISA::HypervisorCall
• HypervisorTrap() : ArmISA::HypervisorTrap
• hypNonSecureRead() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypNonSecureWrite() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypRead() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypSecure() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypSecureRead() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypSecureWrite() : ArmISA::ISA::MiscRegLUTEntryInitializer
• hypWrite() : ArmISA::ISA::MiscRegLUTEntryInitializer