gem5  v21.0.1.0
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Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
[detail level 12345]
 ►NArmISA
 ►NArmISAInst
 ►NBitfieldBackend
 ►NBloomFilter
 ►NCompressor
 ►NCopyEngineReg
 ►Ncp
 ►NDebug
 ►NDecodeCache
 ►NFastModel
 ►NFreeBSD
 ►NGcn3ISAClasses that represnt vector/scalar operands in GCN3 ISA
 ►NGem5SystemC
 ►NGenericISA
 ►NGuestABI
 ►NiGbReg
 ►NIris
 ►NLinux
 ►NLoader
 ►Nm5
 ►NMinor
 ►NMipsISA
 ►NNet
 ►NNullISA
 ►NPowerISA
 ►NPrefetcherCopyright (c) 2018 Metempsy Technology Consulting All rights reserved
 ►NProbePointsName space containing shared probe point declarations
 ►NPs2
 ►NPseudoInst
 ►NQoS
 ►NReplacementPolicyCopyright (c) 2018-2020 Inria All rights reserved
 ►NRiscvISA
 ►Nsc_core
 ►Nsc_dp
 ►Nsc_dt
 ►Nsc_gem5
 ►NSCMI
 ►NSimClockThese are variables that are set based on the simulator frequency
 ►NSinic
 ►NSparcISA
 ►NStats
 ►NstdOverload hash function for BasicBlockRange type
 ►Ntlm
 ►Ntlm_utils
 ►NTrace
 ►NX86ISAThis is exposed globally, independent of the ISA
 ►NX86ISAInst
 C__SchedulingPolicyIntermediate class that derives from the i-face class, and implements its API
 C_amd_queue_s
 C_hsa_agent_dispatch_packet_s
 C_hsa_barrier_and_packet_s
 C_hsa_barrier_or_packet_s
 C_hsa_dispatch_packet_s
 C_hsa_queue_s
 C_hsa_signal_s
 CA9SCU
 Ca_new_struct
 ►CAapcs32
 ►CAapcs32Vfp
 ►CAapcs64
 CAbstractCacheEntry
 ►CAbstractController
 ►CAbstractMemoryAn abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information
 CAbstractNVMThis is an interface between the disk interface (which will handle the disk data transactions) and the timing model
 CAccess
 CAccessTraceForAddress
 CActivityRecorderActivityRecorder helper class that informs the CPU if it can switch over to being idle or not
 Cadapt_ext2gp
 Cadapt_gp2ext
 ►CAddressManager
 CAddressMonitor
 CAddressProfiler
 ►CAddrMapperAn address mapper changes the packet addresses in going from the response port side of the mapper to the request port side
 CAddrRangeEncapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc
 CAddrRangeMapThe AddrRangeMap uses an STL map to implement an interval tree for address decoding
 CAmbaDevice
 CAmbaDmaDevice
 CAmbaFake
 CAmbaIntDevice
 CAmbaPioDevice
 Camd_signal_s
 CAMDKernelCode
 CAp2ScpDoorbell
 CApertureRegister
 CAQLRingBufferInternal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer
 CArchTimerPer-CPU architected timer
 CArchTimerKvm
 ►CARMArchTLB
 CArmFreebsd
 ►CArmFreebsd32
 ►CArmFreebsd64
 CArmInterruptPinGeneric representation of an Arm interrupt pin
 CArmInterruptPinGenThis SimObject is instantiated in the python world and serves as an ArmInterruptPin generator
 ►CArmKvmCPUARM implementation of a KVM-based hardware virtualized CPU
 CArmLinux
 ►CArmLinux32
 ►CArmLinux64
 CArmLinuxProcess32A process with emulated Arm/Linux syscalls
 CArmLinuxProcess64A process with emulated Arm/Linux syscalls
 CArmPPI
 CArmPPIGenPrivate Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of generating more than one interrupt (one per ContextID)
 CArmProcess
 CArmProcess32
 CArmProcess64
 ►CArmSemihostingSemihosting for AArch32 and AArch64
 CArmSPI
 CArmSPIGenShared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a pointer to it and returns it every time it is asked for it (via the get metod)
 CArmSystem
 ►CArmV8KvmCPUThis is an implementation of a KVM-based ARMv8-compatible CPU
 Carr_struct1
 Carr_struct2
 CAssociativeSetCopyright (c) 2018 Metempsy Technology Consulting All rights reserved
 CAtagCmdline
 CAtagCore
 CAtagHeader
 CAtagMem
 CAtagNone
 CAtagRev
 CAtagSerial
 Cataparams
 CAtomicGeneric2Op
 CAtomicGeneric3Op
 CAtomicGenericPair3Op
 CAtomicOpAdd
 CAtomicOpAnd
 CAtomicOpCAS
 CAtomicOpDec
 CAtomicOpExch
 CAtomicOpFunctor
 CAtomicOpInc
 CAtomicOpMax
 CAtomicOpMin
 CAtomicOpOr
 CAtomicOpSub
 CAtomicOpXor
 CAtomicRequestProtocol
 CAtomicResponseProtocol
 ►CAtomicSimpleCPU
 CAuxVector
 Cb_new_struct
 CBackingStore
 CBackingStoreEntryA single entry for the backing store
 CBadDeviceBadDevice This device just panics when accessed
 ►CBankedArray
 CBarrier
 CBaseArmKvmCPU
 CBaseBufferArgBase class for BufferArg and TypedBufferArg, Not intended to be used directly
 ►CBaseCacheA basic cache interface
 ►CBaseCPU
 ►CBaseDynInst
 CBaseGdbRegCacheConcrete subclasses of this abstract class represent how the register values are transmitted on the wire
 CBaseGenBase class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator
 CBaseGic
 CBaseGicRegisters
 ►CBaseGlobalEventCommon base class for GlobalEvent and GlobalSyncEvent
 CBaseGlobalEventTemplateFunky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes
 CBaseHTMCheckpointTransactional Memory checkpoint
 CBaseIndexingPolicyA common base class for indexing table locations
 CBaseInterrupts
 CBaseISA
 ►CBaseKvmCPUBase class for KVM based CPU models
 CBaseKvmTimerTimer functions to interrupt VM execution after a number of simulation ticks
 ►CBaseMemProbeBase class for memory system probes accepting Packet instances
 CBaseMMU
 CBaseO3CPU
 CBaseO3DynInst
 ►CBasePixelPumpTiming generator for a pixel-based display
 ►CBaseRemoteGDB
 CBaseSetAssocA basic cache tag store
 CBaseSimpleCPU
 CBaseStackTrace
 ►CBaseTagsA common base class of Cache tagstore objects
 ►CBaseTLB
 ►CBaseTrafficGenThe traffic generator is a module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces
 ►CBaseXBarThe base crossbar contains the common elements of the non-coherent and coherent crossbar
 CBasicExtLink
 CBasicIntLink
 CBasicLink
 CBasicPioDevice
 CBasicRouter
 CBasicSignal
 ►CBiModeBPImplements a bi-mode branch predictor
 CBitfieldROType
 CBitfieldType
 ►CBitfieldTypeImpl
 CBitfieldWOType
 CBitUnionData
 CBlock
 ►CBmpWriter
 ►CBPredUnitBasically a wrapper class to hold both the branch predictor and the BTB
 CBreakPCEvent
 ►CBridgeA bridge is used to interface two different crossbars (or in general a memory-mapped requestor and responder), with buffering for requests and responses
 CBufferArgBufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call
 CBurstHelperA burst helper helps organize and manage a packet that is larger than the memory burst size
 CCacheA coherent cache that can be arranged in flexible topologies
 ►CCacheBlkA Basic Cache block
 CCacheBlkPrintWrapperSimple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block
 ►CCacheMemory
 CCacheRecorder
 CCallbackQueue
 CChannelAddrClass holding a guest address in a contiguous channel-local address space
 CChannelAddrRangeThe ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space
 CCheck
 CCheckerTemplated Checker class
 CCheckerCPUCheckerCPU class
 CCheckerThreadContextDerived ThreadContext class for use with the Checker
 CCheckpointIn
 CCheckTable
 CChunkGeneratorThis class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g
 CCircleBufCircular buffer backed by a vector
 ►CCircularQueueCircular queue
 ►CClintNOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf
 ►CClockDomainThe ClockDomain provides clock to group of clocked objects bundled under the same clock domain
 CClockedHelper class for objects that need to be clocked
 CClockedObjectExtends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object
 CClockRateControlBwIf
 CClockRateControlDummyProtocolType
 CClockRateControlFwIf
 CClockRateControlInitiatorSocket
 CClockRateControlSlaveBase
 CClockRateControlTargetSocket
 CCoalescedRequest
 CCoeff8
 CCoeff8x8
 ►CCoherentXBarA coherent crossbar connects a number of (potentially) snooping requestors and responders, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses
 CCommandReg
 ►CCommMonitorThe communication monitor is a SimObject which can monitor statistics of the communication happening between two ports in the memory system
 CCompressed
 CCompressedTagsA CompressedTags cache tag store
 CCompressionBlkA superblock is composed of sub-blocks, and each sub-block has information regarding its superblock and a pointer to its superblock tag
 ►CComputeUnit
 ►CConfigCache
 CConstProxyPtr
 CConsumer
 CContextDescriptor
 ►CCopyEngine
 CCoreDecouplingLTInitiator
 CCountedExitEvent
 ►CCowDiskImageSpecialization for accessing a copy-on-write disk image layer
 ►CCpuLocalTimer
 CCPUProgressEvent
 CCpuThread
 CCredit
 CCreditLink
 CCrossbarSwitch
 CCustomNoMaliGpu
 ►CCxxConfigDirectoryEntryConfig details entry for a SimObject
 CCxxConfigFileBaseConfig file wrapper providing a common interface to CxxConfigManager
 ►CCxxConfigManagerThis class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++
 CCxxConfigParamsBase for peer classes of SimObjectParams derived classes with parameter modifying member functions
 CCxxIniFileCxxConfigManager interface for using .ini files
 CCyclesCycles is a wrapper class for representing cycle counts, i.e
 CDataBlock
 CDataTranslationThis class represents part of a data address translation
 CDebugBreakEvent
 CDebugStep
 CDecoderFaultInst
 ►CDefaultBTB
 ►CDefaultCommitDefaultCommit handles single threaded and SMT commit
 ►CDefaultDecodeDefaultDecode class handles both single threaded and SMT decode
 CDefaultDecodeDefaultRenameStruct that defines the information passed from decode to rename
 ►CDefaultFetchDefaultFetch class handles both single threaded and SMT fetch
 CDefaultFetchDefaultDecodeStruct that defines the information passed from fetch to decode
 ►CDefaultIEWDefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback)
 CDefaultIEWDefaultCommitStruct that defines the information passed from IEW to commit
 ►CDefaultRenameDefaultRename handles both single threaded and SMT rename
 CDefaultRenameDefaultIEWStruct that defines the information passed from rename to IEW
 CDependencyEntryNode in a linked list
 CDependencyGraphArray of linked list that maintains the dependencies between producing instructions and consuming instructions
 CDerivedClockDomainThe derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain
 CDerivO3CPU
 CDeviceFDEntryHolds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls)
 CDirectedGenerator
 CDirectoryMemory
 CDiskImageBasic interface for accessing a disk image
 CDisplay
 CDisplayTimings
 ►CDistEtherLinkModel for a fixed bandwidth full duplex ethernet link
 ►CDistHeaderPkt
 ►CDistIfaceThe interface class to talk to peer gem5 processes
 CDmaCallbackDMA callback class
 CDmaDevice
 ►CDmaPort
 ►CDmaReadFifoBuffered DMA engine helper class
 CDMARequest
 CDMASequencer
 CDmaThread
 CDmesgEntry
 CDoorbellGeneric doorbell interface
 Cdp_regsEthernet device registers
 Cdp_rom
 CDrainableInterface for objects that might require draining before checkpointing
 CDrainManager
 CDramGenDRAM specific generator is for issuing request with variable page hit length and bank utilization
 ►CDRAMInterfaceInterface to DRAM devices with media specific parameters, statistics, and functions
 CDRAMPowerDRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system
 CDramRotGen
 ►CDRAMSim2
 CDRAMSim2WrapperWrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world
 ►CDRAMsim3
 CDRAMsim3WrapperWrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world
 CDumbTODDumbTOD simply returns some idea of time when read
 CDummyCheckerSpecific non-templated derived class used for SimObject configuration
 ►CDVFSHandlerDVFS Handler class, maintains a list of all the domains it can handle
 CDynPoolManager
 ►CElasticTraceThe elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU
 CEmbeddedPyBind
 CEmbeddedPython
 CEmulatedDriverEmulatedDriver is an abstract base class for fake SE-mode device drivers
 ►CEmulationPageTable
 CEnergyCtrl
 ►CEpisode
 CEtherBus
 CEtherDevBaseDummy class to keep the Python class hierarchy in sync with the C++ object hierarchy
 ►CEtherDevice
 CEtherDump
 CEtherInt
 ►CEtherLink
 ►CEtherSwitch
 CEtherTapBase
 CEtherTapInt
 CEtherTapStub
 CEthPacketData
 CEvent
 CEventBaseCommon base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions
 CEventFunctionWrapper
 CEventManager
 ►CEventQueueQueue of events sorted in time order
 CEventWrapper
 CExecContextThe ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model
 ►CExecStage
 CExitGenThe exit generator exits from the simulation once entered
 ►CExpectedMap
 CExplicitATTarget
 CExplicitLTTarget
 ►CExtensionPool
 ►CExternalMaster
 ►CExternalSlave
 CFailUnimplementedStatic instruction class for unimplemented instructions that cause simulator termination
 ►CFALRUA fully associative LRU cache
 CFALRUBlkA fully associative cache block
 CFaultBase
 ►CFaultModel
 CFDArray
 CFDEntryHolds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode
 ►CFetchStage
 ►CFetchUnit
 CFiberThis class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution
 CFifoSimple FIFO implementation backed by a circular buffer
 CFileFDEntryHolds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk)
 CFixedStreamGen
 CFlagsWrapper that groups a few flag bits under the same undelying container
 ►CFlashDeviceFlash Device model The Flash Device model is a timing model for a NAND flash device
 Cflit
 CflitBuffer
 CFloat16
 CFrameBufferInternal gem5 representation of a frame buffer
 CFreeBSDThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface
 CFUDesc
 ►CFullO3CPUFullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages
 Cfun
 CFunctionalRequestProtocol
 CFunctionalResponseProtocol
 CFunctionProfile
 CFuncUnit
 ►CFUPoolPool of FU's, specific to the new CPU model
 CFutexKeyFutexKey class defines an unique identifier for a particular futex in the system
 CFutexMapFutexMap class holds a map of all futexes used in the system
 ►CFVPBasePwrCtrl
 CFXSave
 CGarnetExtLink
 CGarnetIntLink
 CGarnetNetwork
 ►CGarnetSyntheticTraffic
 CGenericAlignmentFault
 CGenericArmPciHost
 CGenericHtmFailureFault
 CGenericPageTableFault
 CGenericPciHostConfigurable generic PCI host interface
 CGenericSatCounterImplements an n bit saturating counter and provides methods to increment, decrement, and read it
 CGenericSyscallABI
 ►CGenericSyscallABI32
 CGenericSyscallABI64
 ►CGenericTimer
 CGenericTimerFrame
 CGenericTimerISA
 CGenericTimerMem
 ►CGenericWatchdog
 ►CGicV2
 CGicv2m
 CGicv2mFrameUltimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m
 CGicv3
 ►CGicv3CPUInterface
 CGicv3Distributor
 ►CGicv3ItsGICv3 ITS module
 CGicv3Redistributor
 ►CGlobalEventThe main global event class
 ►CGlobalMemPipeline
 CGlobalsContainer for serializing global variables (not associated with any serialized object)
 CGlobalSimLoopExitEvent
 ►CGlobalSyncEventA special global event that synchronizes all threads and forces them to process asynchronously enqueued events
 CGoodbyeObject
 ►CGPUCoalescer
 ►CGPUCommandProcessor
 CGPUComputeDriver
 ►CGPUDispatcher
 CGPUDynInst
 CGPUExecContext
 CGPUStaticInst
 CGpuWavefront
 CHardBreakpoint
 CHBFDEntryExtends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags
 ►CHDLcd
 CHelloObject
 CHiFive
 CHistogram
 CHMCControllerHMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol
 Chsa_agent_dispatch_packet_sAgent dispatch packet
 Chsa_agent_sStruct containing an opaque handle to an agent, a device that participates in the HSA memory model
 Chsa_barrier_and_packet_sBarrier-AND packet
 Chsa_barrier_or_packet_sBarrier-OR packet
 Chsa_cache_sCache handle
 Chsa_callback_data_sApplication data handle that is passed to the serialization and deserialization functions
 Chsa_code_object_reader_sCode object reader handle
 Chsa_code_object_sStruct containing an opaque handle to a code object, which contains ISA for finalized kernels and indirect functions together with information about the global or readonly segment variables they reference
 Chsa_code_symbol_sCode object symbol handle
 Chsa_dim3_sThree-dimensional coordinate
 Chsa_executable_sStruct containing an opaque handle to an executable, which contains ISA for finalized kernels and indirect functions together with the allocated global or readonly segment variables they reference
 Chsa_executable_symbol_sExecutable symbol handle
 Chsa_isa_sInstruction set architecture
 Chsa_kernel_dispatch_packet_sAQL kernel dispatch packet
 Chsa_loaded_code_object_sLoaded code object handle
 Chsa_packet_header_s
 Chsa_queue_sUser mode queue
 Chsa_region_sA memory region represents a block of virtual memory with certain properties
 Chsa_signal_group_sGroup of signals
 Chsa_signal_sSignal handle
 Chsa_wavefront_sWavefront handle
 CHSADevice
 ►CHSADriver
 ►CHSAPacketProcessor
 CHSAQueueDescriptor
 CHSAQueueEntry
 CHTMSequencer
 CHUFFMTBL_ENTRY
 ►CHWScheduler
 CHybridGenHybrid NVM + DRAM specific generator is for issuing request with variable buffer hit length and bank utilization
 CI2CBus
 CI2CDevice
 ►CIdeControllerDevice model for an Intel PIIX4 IDE controller
 ►CIdeDiskIDE Disk device model
 CIdleGenThe idle generator does nothing
 CIdleStartEvent
 ►CIGbE
 CIGbEInt
 CIllegalExecInstThis class is modelling instructions which are not going to be executed since they are flagged as Illegal Execution Instructions (PSTATE.IL = 1 or CPSR.IL = 1)
 CImgWriter
 CImmOp
 CImmOp64
 CIndirectPredictor
 ►CIniFileThis class represents the contents of a ".ini" file
 CInputUnit
 CInstDecoder
 Cinstr
 ►CInstResult
 ►CInstructionQueueA standard instruction queue class
 ►CIntel8254TimerProgrammable Interval Timer (Intel 8254)
 CIntrControl
 CIntSinkPin
 CIntSinkPinBase
 CIntSourcePin
 CIntSourcePinBase
 CInvalidateGenerator
 ►CIob
 ►CIPACache
 CIsaFakeIsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites
 CIssueStruct
 CItsAction
 ►CItsCommandAn ItsCommand is created whenever there is a new command in the command queue
 CItsProcessItsProcess is a base coroutine wrapper which is spawned by the Gicv3Its module when the latter needs to perform different actions, like translating a peripheral's MSI into an LPI (See derived ItsTranslation) or processing a Command from the ITS queue (ItsCommand)
 CItsTranslationAn ItsTranslation is created whenever a peripheral writes a message in GITS_TRANSLATER (MSI)
 CKernelLaunchStaticInst
 CKernelWorkload
 Ckfd_event_data
 Ckfd_hsa_memory_exception_data
 Ckfd_ioctl_alloc_memory_of_gpu_args
 Ckfd_ioctl_alloc_memory_of_scratch_args
 Ckfd_ioctl_create_event_args
 Ckfd_ioctl_create_queue_args
 Ckfd_ioctl_cross_memory_copy_args
 Ckfd_ioctl_dbg_address_watch_args
 Ckfd_ioctl_dbg_register_args
 Ckfd_ioctl_dbg_unregister_args
 Ckfd_ioctl_dbg_wave_control_args
 Ckfd_ioctl_destroy_event_args
 Ckfd_ioctl_destroy_queue_args
 Ckfd_ioctl_free_memory_of_gpu_args
 Ckfd_ioctl_get_clock_counters_args
 Ckfd_ioctl_get_dmabuf_info_args
 Ckfd_ioctl_get_process_apertures_args
 Ckfd_ioctl_get_process_apertures_new_args
 Ckfd_ioctl_get_tile_config_args
 Ckfd_ioctl_get_version_args
 Ckfd_ioctl_import_dmabuf_args
 Ckfd_ioctl_ipc_export_handle_args
 Ckfd_ioctl_ipc_import_handle_args
 Ckfd_ioctl_map_memory_to_gpu_args
 Ckfd_ioctl_open_graphic_handle_args
 Ckfd_ioctl_reset_event_args
 Ckfd_ioctl_set_cu_mask_args
 Ckfd_ioctl_set_event_args
 Ckfd_ioctl_set_memory_policy_args
 Ckfd_ioctl_set_process_dgpu_aperture_args
 Ckfd_ioctl_set_trap_handler_args
 Ckfd_ioctl_unmap_memory_from_gpu_args
 Ckfd_ioctl_update_queue_args
 Ckfd_ioctl_wait_events_args
 Ckfd_memory_exception_failure
 Ckfd_memory_range
 Ckfd_process_device_apertures
 CKvmKVM parent interface
 CKvmDeviceKVM device wrapper
 CKvmFPReg
 CKvmKernelGicV2KVM in-kernel GIC abstraction
 ►CKvmVMKVM VM container
 CLaneDataLaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values just depending on its width
 CLdsChunkThis represents a slice of the overall LDS, intended to be associated with an individual workgroup
 ►CLdsState
 CLinearEquationThis class describes a linear equation with constant coefficients
 CLinearGenThe linear generator generates sequential requests from a start to an end address, with a fixed block size
 CLinearSystem
 CLinkedFiber
 CLinkEntry
 CLinkOrder
 ►CLinuxThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface
 CListenSocket
 CLocalBPImplements a local predictor that uses the PC to index into a table of counters
 ►CLocalMemPipeline
 CLocalSimLoopExitEvent
 CLockedAddrLocked address class that represents a physical address and a context id
 ►CLogger
 ►CLoopPredictor
 ►CLSQ
 ►CLSQUnitClass that implements the actual LQ and SQ for each specific thread
 ►CLTAGE
 Cltseqnum
 CMachineID
 CMaltaTop level class for Malta Chipset emulation
 CMaltaCChipMalta CChip CSR Emulation
 ►CMaltaIOMalta I/O device is a catch all for all the south bridge stuff we care to implement
 CMasterPort
 ►CMathExpr
 CMathExprPowerModelA Equation power model
 CMatrix64x12
 ►CMC146818Real-Time Clock (MC146818)
 CMcrMrcImplDefinedThis class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable even for unimplemented registers
 CMcrMrcMiscInstCertain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access
 CMcrrOp
 CMemBackdoor
 ►CMemCheckerMemChecker
 ►CMemCheckerMonitorImplements a MemChecker monitor, to be inserted between two ports
 ►CMemCmd
 ►CMemCtrlThe memory controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary controller
 ►CMemDelayThis abstract component provides a mechanism to delay packets
 ►CMemDepUnitMemory dependency unit class
 ►CMemFootprintProbeProbe to track footprint of accessed memory Two granularity of footprint measurement i.e
 ►CMemInterfaceGeneral interface to memory device Includes functions and parameters shared across media types
 CMemObjectExtends the ClockedObject for historical reasons
 Cmemory
 CMemPacketA memory packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address
 CMemStateThis class holds the memory state for the Process class and all of its derived, architecture-specific children
 ►CMemTestTests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes
 CMemTraceProbe
 CMessage
 CMessageBuffer
 CMHUMessage Handling Unit
 CMhuDoorbell
 ►CMinorCPUMinorCPU is an in-order CPU model with four fixed pipeline stages:
 CMinorFUA functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit)
 CMinorFUPoolA collection of MinorFUs
 CMinorFUTimingExtra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction
 CMinorOpClassBoxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking
 CMinorOpClassSetWrapper for a matchable set of op classes
 CMipsAccess
 ►CMipsLinux
 CMipsProcess
 CMiscRegImmOp64
 CMiscRegImplDefined64
 CMiscRegOp64This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS
 CMiscRegRegImmOp
 CMiscRegRegImmOp64
 ►Cmm
 CMmDisk
 CMmioVirtIO
 CMockInfoA mocked info class
 CMockListenSocket
 CMPP_LoopPredictor
 CMPP_LoopPredictor_8KB
 ►CMPP_StatisticalCorrector
 CMPP_StatisticalCorrector_64KB
 CMPP_StatisticalCorrector_8KB
 ►CMPP_TAGE
 CMPP_TAGE_8KB
 CMrrcOp
 CMrsOp
 ►CMSHRMiss Status and handling Register
 CMSHRQueueA Class for maintaining a list of pending and allocated memory requests
 CMSICAP
 CMSIX
 CMSIXCAP
 CMSIXPbaEntry
 CMSIXTable
 CMsrBase
 CMsrImmOp
 CMsrRegOp
 CMultiLevelPageTable
 ►CMultiperspectivePerceptron
 CMultiperspectivePerceptron64KB
 CMultiperspectivePerceptron8KB
 ►CMultiperspectivePerceptronTAGE
 CMultiperspectivePerceptronTAGE64KB
 CMultiperspectivePerceptronTAGE8KB
 ►CMultiSocketSimpleSwitchAT
 CMuxingKvmGic
 Cmy_extended_payload_types
 Cmy_extension
 CNamed
 CNetDest
 ►CNetwork
 CNetworkBridge
 ►CNetworkInterface
 CNetworkLink
 CNoMaliGpu
 CNonCachingSimpleCPUThe NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of just 'atomic'
 CNoncoherentCacheA non-coherent cache
 ►CNoncoherentXBarA non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides, and routes the request and response packets based on the address
 Cns_desc32
 Cns_desc64
 CNSGigENS DP83820 Ethernet device model
 CNSGigEInt
 CNvmGenNVM specific generator is for issuing request with variable buffer hit length and bank utilization
 ►CNVMInterfaceInterface to NVM devices with media specific parameters, statistics, and functions
 CO3CheckerSpecific non-templated derived class used for SimObject configuration
 CO3CPUImplImplementation specific struct that defines several key types to the CPU, the stages within the CPU, the time buffers, and the DynInst
 CO3ThreadContextDerived ThreadContext class for use with the O3CPU
 CO3ThreadStateClass that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc
 CObjectMatchObjectMatch contains a vector of expressions
 COFSchedulingPolicy
 COpDesc
 Coperand
 ►COperatingSystemThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface
 COutputDirectoryInterface for creating files in a gem5 output directory
 COutputFile
 COutputStream
 COutputUnit
 COutVcState
 CP9MsgHeader
 CP9MsgInfo
 ►CPacketA Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache)
 CPacketFifo
 CPacketFifoEntry
 ►CPacketQueueA packet queue is a class that holds deferred packets and later sends them using the associated CPU-side port or memory-side port
 CPageTableOps
 CPanicPCEvent
 CParseParam
 CParseParam< BitUnionType< T > >
 CParseParam< bool >
 CParseParam< std::string >
 CParseParam< T, decltype(to_number("", std::declval< T & >()), void())>
 CParseParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >
 CPc
 Cpcap_file_header
 Cpcap_pkthdr
 CPCEvent
 ►CPCEventQueue
 CPCEventScope
 CPciBar
 CPciBarNone
 CPciBusAddr
 CPciDevicePCI device, base implementation is only config space
 ►CPciHostThe PCI host describes the interface between PCI devices and a simulated system
 CPciIoBar
 CPciLegacyIoBar
 CPciMemBar
 CPciMemUpperBar
 CPciVirtIO
 CPendingWriteInst
 CPerfectCacheLineState
 CPerfectCacheMemory
 CPerfectSwitch
 CPerfKvmCounterAn instance of a performance counter
 CPerfKvmCounterConfigPerfEvent counter configuration
 CPerfKvmTimerPerfEvent based timer using the host's CPU cycle counter
 CPersistentTable
 CPersistentTableEntry
 CPhysicalMemoryThe physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect
 CPhysRegFileSimple physical register file class
 CPhysRegIdPhysical register ID
 CPioDeviceThis device is the base class which all devices senstive to an address range inherit from
 CPioPortThe PioPort class is a programmed i/o port that all devices that are sensitive to an address range use
 CPipeFDEntryHolds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants
 Cpipeline
 CPipeStageIFace
 CPixelInternal gem5 representation of a Pixel
 ►CPixelConverterConfigurable RGB pixel converter
 CPl011
 CPL031
 CPl050
 CPl111
 CPlatform
 ►CPlic
 CPlicIntDevice
 CPlicOutputNOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf
 CPMACheckerBased on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the Physical Memory Attributes
 CPMCAP
 ►CPngWriterImage writer implementing support for PNG
 CPollEvent
 CPollQueue
 CPoolManager
 ►CPortPorts are used to interface objects to each other
 CPortProxyThis object is a proxy for a port or other object which implements the functional response protocol, to be used for debug accesses
 CPosixKvmTimerTimer based on standard POSIX timers
 ►CPowerDomainThe PowerDomain groups PowerState objects together to regulate their power states
 ►CPowerLinux
 ►CPowerModel
 CPowerModelStateA PowerModelState is an abstract class used as interface to get power figures out of SimObjects
 CPowerProcess
 ►CPowerStateHelper class for objects that have power states
 CPrdEntry
 CPrdTableEntry
 CPrefetchEntry
 CPrintableAbstract base class for objects which support being printed to a stream for debugging
 CProbeListenerProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener
 CProbeListenerArgProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call
 CProbeListenerArgBaseProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type)
 CProbeListenerObjectThis class is a minimal wrapper around SimObject
 CProbeManagerProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points
 CProbePointProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint
 CProbePointArgProbePointArg generates a point for the class of Arg
 ►CProcess
 CProfileNode
 ►CProfiler
 ►CProtocolTester
 CProtoInputStreamA ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file name
 CProtoOutputStreamA ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file name
 CProtoStreamA ProtoStream provides the shared functionality of the input and output streams
 CProxyPtr
 CProxyPtr< void, Proxy >
 CProxyPtrBuffer
 CPS2Device
 CPS2Keyboard
 CPS2Mouse
 CPS2TouchKit
 CPXCAP
 CPybindSimObjectResolverResolve a SimObject name using the Pybind configuration
 CPyEventPyBind wrapper for Events
 CPyTrafficGen
 CQoSMemSinkInterface
 ►CQTIsaac
 CQueueA high-level queue interface, to be used by both the MSHR queue and the write buffer
 CQueueContext
 CQueuedRequestPortThe QueuedRequestPort combines two queues, a request queue and a snoop response queue, that both share the same port
 CQueuedResponsePortA queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port
 ►CQueueEntryA queue entry base class, to be used by both the MSHRs and write-queue entries
 CRandom
 CRandomGenThe random generator is similar to the linear one, but does not generate sequential addresses
 CRandomStreamGen
 CRangeAddrMapperRange address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset
 CRawDiskImageSpecialization for accessing a raw disk image
 CRealView
 ►CRealViewCtrl
 CRealViewOscThis is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface
 CRealViewTemperatureSensorThis device implements the temperature sensor used in the RealView/Versatile Express platform
 CRedirectPathRedirectPath stores a mapping from one 'appPath' to a vector of 'hostPath'
 CReExec
 CRefCountedDerive from RefCounted if you want to enable reference counting of this class
 CRefCountingPtrIf you want a reference counting pointer to a mutable object, create it like this:
 CRegIdRegister ID: describe an architectural register with its class and index
 CRegImmImmOp
 CRegImmOp
 CRegImmRegOp
 CRegImmRegShiftOp
 ►CRegisterBank
 ►CRegisterBankBase
 ►CRegisterBankTest
 CRegisterBufTest
 ►CRegisterFile
 CRegisterLBufTest
 CRegisterManager
 CRegisterManagerPolicyRegister Manager Policy abstract class
 CRegisterRaoTest
 CRegisterRazTest
 CRegMiscRegImmOp
 CRegMiscRegImmOp64
 CRegNone
 CRegOp
 CRegRegImmImmOp
 CRegRegImmImmOp64
 CRegRegImmOp
 CRegRegOp
 CRegRegRegImmOp
 CRegRegRegImmOp64
 CRegRegRegOp
 CRegRegRegRegOp
 CRejectException
 CRenameModeHelper structure to get the vector register mode for a given ISA
 CRenameMode< ArmISA::ISA >
 CReplaceableEntryA replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality
 CReqPacketQueue
 CRequest
 CRequestorInfoData about a specific requestor
 CRequestPortA RequestPort is a specialisation of a Port, which implements the default protocol for the three different level of transport functions
 CResponsePortA ResponsePort is a specialization of a port
 CRespPacketQueue
 CReturnAddrStackReturn address stack class, implements a simple RAS
 Crgb_t
 CRiscvLinux
 ►CRiscvLinux32
 ►CRiscvLinux64
 CRiscvProcess
 CRiscvProcess32
 CRiscvProcess64
 ►CRiscvRTCNOTE: This is a generic wrapper around the MC146818 RTC
 ►CROBROB class
 ►CRoot
 CRouteInfo
 CRouter
 CRoutingUnit
 CRRSchedulingPolicy
 ►CRubyDirectedTester
 CRubyDummyPort
 ►CRubyPort
 CRubyPortProxy
 ►CRubyPrefetcher
 CRubyRequest
 CRubySystem
 ►CRubyTester
 CScalarMemPipeline
 CScalarRegisterFile
 CScheduler
 ►CScheduleStage
 CScheduleToExecuteCommunication interface between Schedule and Execute stages
 CSchedulingPolicyInterface class for the wave scheduling policy
 CScoreboardImplements a simple scoreboard to track which registers are ready
 ►CScoreboardCheckStage
 CScoreboardCheckToScheduleCommunication interface between ScoreboardCheck and Schedule stages
 CScp
 CScp2ApDoorbell
 CSectorBlkA Basic Sector block
 CSectorSubBlkA sector is composed of sub-blocks, and each sub-block has information regarding its sector and a pointer to its sector tag
 ►CSectorTagsA SectorTags cache tag store
 ►CSemiPseudoAbi32
 ►CSemiPseudoAbi64
 CSequencer
 CSequencerRequest
 CSerialDeviceBase class for serial devices such as terminals
 ►CSerializableBasic support for object serialization
 ►CSerialLinkSerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization
 CSerialNullDeviceDummy serial device that discards all data sent to it
 CSeriesRequestGenerator
 CSESyscallFault
 CSet
 CSetAssociativeA set associative indexing policy
 CSETranslatingPortProxy
 CSEWorkload
 ►CShader
 CShowParam
 CShowParam< BitUnionType< T > >
 CShowParam< bool >
 CShowParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >
 CShowParam< T, std::enable_if_t< std::is_same< char, T >::value||std::is_same< unsigned char, T >::value||std::is_same< signed char, T >::value > >
 CSignalInterruptBwIf
 CSignalInterruptDummyProtocolType
 CSignalInterruptFwIf
 CSignalInterruptInitiatorSocket
 CSignalInterruptSlaveBase
 CSignalInterruptTargetSocket
 CSimObjectAbstract superclass for simulation objects
 CSimObjectResolverBase class to wrap object resolving functionality
 CSimpleAddressMapSimple address map implementation for the generic protocol
 ►CSimpleATInitiator1
 ►CSimpleATInitiator2
 CSimpleATTarget1
 CSimpleATTarget2
 ►CSimpleBusAT
 CSimpleBusLT
 ►CSimpleCacheA very simple cache object
 CSimpleCPUPolicyStruct that defines the key classes to be used by the CPU
 CSimpleDisk
 ►CSimpleExecContext
 CSimpleExtLink
 CSimpleFreeListFree list for a single class of registers (e.g., integer or floating point)
 ►CSimpleIndirectPredictor
 CSimpleInitiatorWrapper
 CSimpleIntLink
 CSimpleLTInitiator1TLM definitions
 CSimpleLTInitiator1_dmi
 CSimpleLTInitiator2
 CSimpleLTInitiator2_dmi
 CSimpleLTInitiator3
 CSimpleLTInitiator3_dmi
 CSimpleLTInitiator_ext
 CSimpleLTTarget1
 CSimpleLTTarget2
 CSimpleLTTarget_ext
 CSimpleMemDelayDelay packets by a constant time
 ►CSimpleMemobjA very simple memory object
 ►CSimpleMemoryThe simple memory is a basic single-ported memory controller with a configurable throughput and latency
 ►CSimpleNetwork
 CSimpleObject
 CSimplePoolManager
 CSimpleRenameMapRegister rename map for a single class of registers (e.g., integer or floating point)
 CSimpleTargetWrapper
 CSimpleThreadThe SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface
 CSimpleTimingPortThe simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic
 CSimpleTrace
 CSimpleUart
 ►CSimPoint
 CSkewedAssociativeA skewed associative indexing policy
 CSkipFuncBase
 CSlavePort
 CSMMUAction
 CSMMUATSDevicePort
 CSMMUATSMemoryPort
 CSMMUCommand
 CSMMUCommandExecProcess
 CSMMUControlPort
 CSMMUDevicePort
 CSMMUDeviceRetryEvent
 CSMMUEvent
 CSMMUProcess
 CSMMURegs
 CSMMURequestPort
 CSMMUSemaphore
 CSMMUSignal
 CSMMUTableWalkPort
 ►CSMMUTLB
 ►CSMMUTranslationProcess
 CSMMUTranslRequest
 ►CSMMUv3
 ►CSMMUv3BaseCache
 CSMMUv3DeviceInterface
 CSNHash
 ►CSnoopFilterThis snoop filter keeps track of which connected port has a particular line of data
 CSnoopRespPacketQueue
 CSocketFDEntry
 ►CSolarisThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface
 CSouthBridge
 ►CSp804
 CSp805
 ►CSparc32Linux
 CSparc32Process
 CSparc64Process
 ►CSparcLinux
 CSparcProcess
 CSparcSolaris
 CSrcClockDomainThe source clock domains provides the notion of a clock domain that is connected to a tunable clock source
 Cstack_el
 ►CStackDistCalcThe stack distance calculator is a passive object that merely observes the addresses pass to it
 ►CStackDistProbe
 Cstage1_2
 CStaticInstBase, ISA-independent static instruction class
 CStaticRegisterManagerPolicy
 ►CStatisticalCorrector
 CStatTest
 CStochasticGen
 CStoreSetImplements a store set predictor for determining if memory instructions are dependent upon each other
 CStoreTrace
 CStreamGen
 CStreamTableEntry
 CStridedGenThe strided generator generates sequential requests from a start to an end address, with a fixed block size
 CStringWrap
 CStubSlavePortImplement a ‘stub’ port which just responds to requests by printing a message
 CStubSlavePortHandler
 CSubBlock
 CSubSystemThe SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system
 CSuperBlkA basic compression superblock
 ►CSwitch
 CSwitchAllocator
 CSwitchingFiber
 CSyscallDescThis class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e
 CSyscallDescABI
 CSyscallDescTable
 CSyscallFlagTransTableThis struct is used to build target-OS-dependent tables that map the target's flags to the host's flags
 CSyscallRetryFault
 CSyscallReturnThis class represents the return value from an emulated system call, including any errno setting
 ►CSystem
 CSystemCounterGlobal system counter
 CSystemCounterListenerAbstract class for elements whose events depend on the counting speed of the System Counter
 CT1000
 ►CTAGE
 ►CTAGE_SC_L
 CTAGE_SC_L_64KB
 ►CTAGE_SC_L_64KB_StatisticalCorrector
 CTAGE_SC_L_8KB
 ►CTAGE_SC_L_8KB_StatisticalCorrector
 CTAGE_SC_L_LoopPredictor
 ►CTAGE_SC_L_TAGE
 CTAGE_SC_L_TAGE_64KB
 CTAGE_SC_L_TAGE_8KB
 ►CTAGEBase
 CTaggedEntryCopyright (c) 2020 Inria All rights reserved
 CTapEvent
 ►CTapListener
 ►CTBEStorage
 CTBETable
 ►CTCPIface
 CTempCacheBlkSpecial instance of CacheBlk for use with tempBlk that deals with its block address regeneration
 CTemperatureThe class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius
 ►CTerminal
 Ctest
 CTestABI
 CTestABI_1D
 CTestABI_2D
 CTestABI_Prepare
 ►CTestABI_TcInit
 Ctestbench
 CTestClass
 CTesterDma
 ►CTesterThread
 CTestProxy
 CThermalCapacitorA ThermalCapacitor is used to model a thermal capacitance between two thermal domains
 CThermalDomainA ThermalDomain is used to group objects under that operate under the same temperature
 CThermalEntityAn abstract class that represents any thermal entity which is used in the circuital thermal equivalent model
 CThermalModel
 CThermalNodeA ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains
 CThermalReferenceA ThermalReference is a thermal domain with fixed temperature
 CThermalResistorA ThermalResistor is used to model a thermal resistance between two thermal domains
 CThreadContextThreadContext is the external interface to all thread state for anything outside of the CPU
 ►CThreadStateStruct for holding general thread state that is needed across CPU models
 ►CThrottle
 CTickedTicked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking
 CTickedObjectTickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation
 CTime
 ►CTimeBuffer
 ►CTimeBufStructStruct that defines all backwards communication
 CTimerTable
 CTimingExpr
 CTimingExprBin
 CTimingExprEvalContextObject to gather the visible context for evaluation
 CTimingExprIf
 CTimingExprLet
 CTimingExprLiteral
 CTimingExprReadIntReg
 CTimingExprRef
 CTimingExprSrcReg
 CTimingExprUn
 CTimingRequestProtocol
 CTimingResponseProtocol
 ►CTimingSimpleCPU
 ►CTLBCoalescerThe TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB
 CTokenManager
 CTokenRequestPort
 CTokenResponsePort
 Ctop
 CTopology
 ►CTournamentBPImplements a tournament branch predictor, hopefully identical to the one used in the 21264
 ►CTraceCPUThe trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model
 ►CTraceGenThe trace replay generator reads a trace file and plays back the transactions
 CTraceRecordClass for recording cache contents
 ►CTrafficGenThe traffic generator is a module that generates stimuli for the memory system, based on a collection of simple behaviours that are either probabilistic or based on traces
 CTranslatingPortProxyThis proxy attempts to translate virtual addresses using the TLBs
 ►CTrieA trie is a tree-based data structure used for data retrieval
 CTrieTestData
 ►CTriggerQueue
 CTypedAtomicOpFunctor
 CTypedBufferArgTypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call
 CTypedRegisterTest
 CUart
 ►CUart8250
 ►CUFSHostDeviceUFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ label=" transfer/task/command request " fontsize=6]; transferHandler -> command [ label=" It is a command " fontsize=6]; command -> IDLE [ label=" Command done, no further action " fontsize=6]; transferHandler -> taskStart [ label=" It is a task " fontsize=6]; taskStart -> finalUTP [ label=" Task handled, now acknowledge (UFS) " fontsize=6]; transferHandler -> transferStart [ label=" It is a transfer " fontsize=6]; transferStart -> SCSIResume [ label=" Transfer, obtain the specific command " fontsize=6]; SCSIResume -> DiskDataFlowPhase [ label=" Disk data transfer (see other graphs) " fontsize=6]; SCSIResume -> DeviceDataPhase [ label=" Device info transfer (handled in SCSIResume) " fontsize=6]; DiskDataFlowPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; DeviceDataPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; transferDone -> finalUTP [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6]; finalUTP -> readDone [ label=" All handled, clear data structures " fontsize=6]; readDone -> IDLE [ label=" All handled, nothing outstanding " fontsize=6]; readDone -> transferHandler [ label=" All handled, handle next outstanding " fontsize=6]; }
 CUncoalescedTable
 CUncontendedMutex
 CUnifiedFreeListFreeList class that simply holds the list of free integer and floating point registers
 CUnifiedRenameMapUnified register rename map for all classes of registers
 CUnimpFault
 CUnknownOp
 CUnknownOp64
 CV7LPageTableOps
 CV8PageTableOps16k
 CV8PageTableOps4k
 CV8PageTableOps64k
 CValueSamplesA pair of value and its number of samples, used for sampling
 CVecLaneTVector Lane abstraction Another view of a container
 CVecPredRegContainerGeneric predicate register container
 CVecPredRegTPredicate register view
 CVecRegContainerVector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers
 CVecRegTVector Register Abstraction This generic class is a view in a particularization of MVC, to vector registers
 CVectorRegisterFile
 CVGic
 CVIPERCoalescer
 CVirtDescriptorVirtIO descriptor (chain) wrapper
 ►CVirtIO9PBaseThis class implements a VirtIO transport layer for the 9p network file system
 ►CVirtIO9PDiodVirtIO 9p proxy that communicates with the diod 9p server using pipes
 CVirtIO9PProxyVirtIO 9p proxy base class
 ►CVirtIO9PSocketVirtIO 9p proxy that communicates with a 9p server over tcp sockets
 ►CVirtIOBlockVirtIO block device
 ►CVirtIOConsoleVirtIO console
 CVirtIODeviceBaseBase class for all VirtIO-based devices
 CVirtIODummyDevice
 ►CVirtQueueBase wrapper around a virtqueue
 CVirtualChannel
 ►CVMA
 ►CVncInput
 CVncKeyboardA device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server
 CVncMouse
 ►CVncServer
 ►CVoltageDomainA VoltageDomain is used to group clock domains that operate under the same voltage
 Cvring
 Cvring_avail
 Cvring_desc
 Cvring_used
 Cvring_used_elem
 CWaitClass
 CWaiterStateWaiterState defines internal state of a waiter thread
 ►CWalkCache
 CWarnUnimplementedBase class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation)
 ►CWavefront
 CWFBarrierWF barrier slots
 CWholeTranslationStateThis class captures the state of an address translation
 CWireBuffer
 ►CWorkload
 CWriteAllocatorThe write allocator inspects write packets and detects streaming patterns
 CWriteMask
 CWriteQueueA write queue for all eviction packets, i.e
 ►CWriteQueueEntryWrite queue entry
 Cwriter
 CX86KvmCPUX86 implementation of a KVM-based hardware virtualized CPU
 ►CX86Linux
 ►CX86Linux32
 ►CX86Linux64
 CX86PseudoInstABI
Generated on Tue Jun 22 2021 15:29:16 for gem5 by doxygen 1.8.17