gem5  v21.1.0.2
SimpleATTarget1.h
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19 
20 #ifndef __SIMPLE_AT_TARGET1_H__
21 #define __SIMPLE_AT_TARGET1_H__
22 
23 #include "tlm.h"
24 #include "tlm_utils/simple_target_socket.h"
25 //#include <systemc>
26 #include <cassert>
27 #include <vector>
28 #include <queue>
29 //#include <iostream>
30 
32 {
33 public:
35  typedef tlm::tlm_phase phase_type;
38 
39 public:
41 
42 public:
46  socket("socket"),
49  {
50  // register nb_transport method
52 
56 
60 
64  }
65 
66  //
67  // Simple AT target
68  // - Request is accepted after ACCEPT delay (relative to end of prev request
69  // phase)
70  // - Response is started after RESPONSE delay (relative to end of prev resp
71  // phase)
72  //
74  {
75  if (phase == tlm::BEGIN_REQ) {
76  // transactions may be kept in queue after the initiator has send END_REQ
77  trans.acquire();
78 
79  sc_dt::uint64 address = trans.get_address();
80  assert(address < 400);
81 
82  unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
83  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
84  std::cout << name() << ": Received write request: A = 0x"
85  << std::hex << (unsigned int)address << ", D = 0x"
86  << data << std::dec
87  << " @ " << sc_core::sc_time_stamp() << std::endl;
88 
89  *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
90 
91  } else {
92  std::cout << name() << ": Received read request: A = 0x"
93  << std::hex << (unsigned int)address << std::dec
94  << " @ " << sc_core::sc_time_stamp() << std::endl;
95 
96  data = *reinterpret_cast<unsigned int*>(&mMem[address]);
97  }
98 
99  // Notify end of request phase after ACCEPT delay
100  if (mEndRequestQueue.empty()) {
102  }
103  mEndRequestQueue.push(&trans);
104 
105  // AT-noTA target
106  // - always return false
107  // - seperate call to indicate end of phase (do not update phase or t)
108  return tlm::TLM_ACCEPTED;
109 
110  } else if (phase == tlm::END_RESP) {
111 
112  // response phase ends after t
114 
115  return tlm::TLM_COMPLETED;
116  }
117 
118  // Not possible
119  assert(0); exit(1);
120 // return tlm::TLM_COMPLETED; //unreachable code
121  }
122 
123  void endRequest()
124  {
125  assert(!mEndRequestQueue.empty());
126  // end request phase of oldest transaction
127  phase_type phase = tlm::END_REQ;
129  transaction_type* trans = mEndRequestQueue.front();
130  assert(trans);
131  mEndRequestQueue.pop();
132  #if ( ! NDEBUG )
133  sync_enum_type r = socket->nb_transport_bw(*trans, phase, t);
134  #endif /* ! NDEBUG */
135  assert(r == tlm::TLM_ACCEPTED); // FIXME: initiator should return TLM_ACCEPTED?
136  assert(t == sc_core::SC_ZERO_TIME); // t must be SC_ZERO_TIME
137 
138  // Notify end of request phase for next transaction after ACCEPT delay
139  if (!mEndRequestQueue.empty()) {
141  }
142 
143  if (mResponseQueue.empty()) {
144  // Start processing transaction
145  // Notify begin of response phase after RESPONSE delay
147  }
148  mResponseQueue.push(trans);
149  }
150 
151  void beginResponse()
152  {
153  assert(!mResponseQueue.empty());
154  // start response phase of oldest transaction
155  phase_type phase = tlm::BEGIN_RESP;
157  transaction_type* trans = mResponseQueue.front();
158  assert(trans);
159 
160  // Set response data
161  trans->set_response_status(tlm::TLM_OK_RESPONSE);
162  if (trans->get_command() == tlm::TLM_READ_COMMAND) {
163  sc_dt::uint64 address = trans->get_address();
164  assert(address < 400);
165  *reinterpret_cast<unsigned int*>(trans->get_data_ptr()) =
166  *reinterpret_cast<unsigned int*>(&mMem[address]);
167  }
168 
169  switch (socket->nb_transport_bw(*trans, phase, t)) {
170  case tlm::TLM_COMPLETED:
171  // response phase ends after t
173  break;
174 
175  case tlm::TLM_ACCEPTED:
176  case tlm::TLM_UPDATED:
177  // initiator will call nb_transport to indicate end of response phase
178  break;
179 
180  default:
181  assert(0); exit(1);
182  };
183  }
184 
185  void endResponse()
186  {
187  assert(!mResponseQueue.empty());
188  mResponseQueue.front()->release();
189  mResponseQueue.pop();
190 
191  if (!mResponseQueue.empty()) {
192  // Start processing next transaction
193  // Notify begin of response phase after RESPONSE delay
195  }
196  }
197 
198 private:
201 
202 private:
203  unsigned char mMem[400];
204  std::queue<transaction_type*> mEndRequestQueue;
206  std::queue<transaction_type*> mResponseQueue;
209 };
210 
211 #endif
SimpleATTarget1::ACCEPT_DELAY
const sc_core::sc_time ACCEPT_DELAY
Definition: SimpleATTarget1.h:216
SimpleATTarget1::mEndRequestQueue
std::queue< transaction_type * > mEndRequestQueue
Definition: SimpleATTarget1.h:221
data
const char data[]
Definition: circlebuf.test.cc:48
sc_core::sc_module
Definition: sc_module.hh:98
tlm::tlm_phase
Definition: phase.hh:47
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
SimpleATTarget1::mMem
unsigned char mMem[400]
Definition: SimpleATTarget1.h:220
sc_core
Definition: messages.cc:31
SimpleATTarget1::endRequest
void endRequest()
Definition: SimpleATTarget1.h:140
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
tlm::TLM_UPDATED
@ TLM_UPDATED
Definition: fw_bw_ifs.hh:65
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
tlm::END_REQ
@ END_REQ
Definition: phase.hh:42
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SimpleATTarget1::socket
target_socket_type socket
Definition: SimpleATTarget1.h:57
SimpleATTarget1
Definition: SimpleATTarget1.h:31
SimpleATTarget1::endResponse
void endResponse()
Definition: SimpleATTarget1.h:202
SimpleATTarget1::mResponseQueue
std::queue< transaction_type * > mResponseQueue
Definition: SimpleATTarget1.h:223
sc_core::SC_NS
@ SC_NS
Definition: sc_time.hh:43
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
sc_core::sc_module::dont_initialize
void dont_initialize()
Definition: sc_module.cc:336
SimpleATTarget1::phase_type
tlm::tlm_phase phase_type
Definition: SimpleATTarget1.h:52
SC_METHOD
#define SC_METHOD(name)
Definition: sc_module.hh:300
sc_core::sc_event
Definition: sc_event.hh:169
SimpleATTarget1::SimpleATTarget1
SimpleATTarget1(sc_core::sc_module_name name)
Definition: SimpleATTarget1.h:61
sc_core::sc_time
Definition: sc_time.hh:49
SimpleATTarget1::mBeginResponseEvent
sc_core::sc_event mBeginResponseEvent
Definition: SimpleATTarget1.h:224
SimpleATTarget1::SC_HAS_PROCESS
SC_HAS_PROCESS(SimpleATTarget1)
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
sc_core::sc_module_name
Definition: sc_module_name.hh:41
SimpleATTarget1::transaction_type
tlm::tlm_generic_payload transaction_type
Definition: SimpleATTarget1.h:51
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
SimpleATTarget1::mEndRequestEvent
sc_core::sc_event mEndRequestEvent
Definition: SimpleATTarget1.h:222
SimpleATTarget1::target_socket_type
tlm_utils::simple_target_socket< SimpleATTarget1 > target_socket_type
Definition: SimpleATTarget1.h:54
SimpleATTarget1::beginResponse
void beginResponse()
Definition: SimpleATTarget1.h:168
tlm::END_RESP
@ END_RESP
Definition: phase.hh:44
tlm_utils::simple_target_socket< SimpleATTarget1 >
SimpleATTarget1::RESPONSE_DELAY
const sc_core::sc_time RESPONSE_DELAY
Definition: SimpleATTarget1.h:217
gem5::X86ISA::exit
Bitfield< 3 > exit
Definition: misc.hh:854
sc_core::sc_event::notify
void notify()
Definition: sc_event.cc:337
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
tlm::tlm_generic_payload
Definition: gp.hh:133
SimpleATTarget1::mEndResponseEvent
sc_core::sc_event mEndResponseEvent
Definition: SimpleATTarget1.h:225
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
sc_core::sc_module::sensitive
sc_sensitive sensitive
Definition: sc_module.hh:207
SimpleATTarget1::myNBTransport
sync_enum_type myNBTransport(transaction_type &trans, phase_type &phase, sc_core::sc_time &t)
Definition: SimpleATTarget1.h:90
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:127
tlm::BEGIN_RESP
@ BEGIN_RESP
Definition: phase.hh:43
tlm_utils::simple_target_socket_b::register_nb_transport_fw
void register_nb_transport_fw(MODULE *mod, sync_enum_type(MODULE::*cb)(transaction_type &, phase_type &, sc_core::sc_time &))
Definition: simple_target_socket.h:108
SimpleATTarget1::sync_enum_type
tlm::tlm_sync_enum sync_enum_type
Definition: SimpleATTarget1.h:53
tlm::TLM_ACCEPTED
@ TLM_ACCEPTED
Definition: fw_bw_ifs.hh:65

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