gem5  v21.1.0.2
SimpleATTarget2.h
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19 
20 #ifndef __SIMPLE_AT_TARGET2_H__
21 #define __SIMPLE_AT_TARGET2_H__
22 
23 #include "tlm.h"
24 #include "tlm_utils/simple_target_socket.h"
25 //#include <systemc>
26 #include <cassert>
27 #include <vector>
28 #include <queue>
29 //#include <iostream>
30 
32 {
33 public:
35  typedef tlm::tlm_phase phase_type;
38 
39 public:
41 
42 public:
46  socket("socket"),
49  {
50  // register nb_transport method
52 
56 
60  }
61 
62  //
63  // Simple AT-TA target
64  // - Request is accepted after fixed delay (relative to end of prev request
65  // phase)
66  // - Response is started after fixed delay (relative to end of prev resp
67  // phase)
68  //
70  phase_type& phase,
71  sc_core::sc_time& t)
72  {
73  if (phase == tlm::BEGIN_REQ) {
74  // transactions may be kept in queue after the initiator has send END_REQ
75  trans.acquire();
76 
77  sc_dt::uint64 address = trans.get_address();
78  assert(address < 400);
79 
80  unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
81  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
82  std::cout << name() << ": Received write request: A = 0x"
83  << std::hex << (unsigned int)address << ", D = 0x" << data
84  << std::dec << " @ " << sc_core::sc_time_stamp()
85  << std::endl;
86 
87  *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
88 
89  } else {
90  std::cout << name() << ": Received read request: A = 0x"
91  << std::hex << (unsigned int)address
92  << std::dec << " @ " << sc_core::sc_time_stamp()
93  << std::endl;
94 
95  data = *reinterpret_cast<unsigned int*>(&mMem[address]);
96  }
97 
98  // End request phase after accept delay
99  t += ACCEPT_DELAY;
100  phase = tlm::END_REQ;
101 
102  if (mResponseQueue.empty()) {
103  // Start processing transaction after accept delay
104  // Notify begin of response phase after accept delay + response delay
106  }
107  mResponseQueue.push(&trans);
108 
109  // AT-noTA target
110  // - always return false
111  // - immediately return delay to indicate end of phase
112  return tlm::TLM_UPDATED;
113 
114  } else if (phase == tlm::END_RESP) {
115 
116  // response phase ends after t
118 
119  return tlm::TLM_COMPLETED;
120  }
121 
122  // Not possible
123  assert(0); exit(1);
124 // return tlm::TLM_COMPLETED; //unreachable code
125  }
126 
127  void beginResponse()
128  {
129  assert(!mResponseQueue.empty());
130  // start response phase of oldest transaction
131  phase_type phase = tlm::BEGIN_RESP;
133  transaction_type* trans = mResponseQueue.front();
134  assert(trans);
135 
136  // Set response data
137  trans->set_response_status(tlm::TLM_OK_RESPONSE);
138  if (trans->get_command() == tlm::TLM_READ_COMMAND) {
139  sc_dt::uint64 address = trans->get_address();
140  assert(address < 400);
141  *reinterpret_cast<unsigned int*>(trans->get_data_ptr()) =
142  *reinterpret_cast<unsigned int*>(&mMem[address]);
143  }
144 
145  if (socket->nb_transport_bw(*trans, phase, t) == tlm::TLM_COMPLETED) {
146  // response phase ends after t
148 
149  } else {
150  // initiator will call nb_transport to indicate end of response phase
151  }
152  }
153 
154  void endResponse()
155  {
156  assert(!mResponseQueue.empty());
157  mResponseQueue.front()->release();
158  mResponseQueue.pop();
159 
160  // Start processing next transaction when previous response is accepted.
161  // Notify begin of response phase after RESPONSE delay
162  if (!mResponseQueue.empty()) {
164  }
165  }
166 
167 private:
170 
171 private:
172  unsigned char mMem[400];
173  std::queue<transaction_type*> mResponseQueue;
176 };
177 
178 #endif
SimpleATTarget2::SC_HAS_PROCESS
SC_HAS_PROCESS(SimpleATTarget2)
SimpleATTarget2::target_socket_type
tlm_utils::simple_target_socket< SimpleATTarget2 > target_socket_type
Definition: SimpleATTarget2.h:54
SimpleATTarget2
Definition: SimpleATTarget2.h:31
data
const char data[]
Definition: circlebuf.test.cc:48
SimpleATTarget2::transaction_type
tlm::tlm_generic_payload transaction_type
Definition: SimpleATTarget2.h:51
sc_core::sc_module
Definition: sc_module.hh:98
tlm::tlm_phase
Definition: phase.hh:47
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
SimpleATTarget2::mEndResponseEvent
sc_core::sc_event mEndResponseEvent
Definition: SimpleATTarget2.h:192
sc_core
Definition: messages.cc:31
SimpleATTarget2::mResponseQueue
std::queue< transaction_type * > mResponseQueue
Definition: SimpleATTarget2.h:190
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
tlm::TLM_UPDATED
@ TLM_UPDATED
Definition: fw_bw_ifs.hh:65
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
tlm::END_REQ
@ END_REQ
Definition: phase.hh:42
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SimpleATTarget2::beginResponse
void beginResponse()
Definition: SimpleATTarget2.h:144
SimpleATTarget2::SimpleATTarget2
SimpleATTarget2(sc_core::sc_module_name name)
Definition: SimpleATTarget2.h:61
SimpleATTarget2::myNBTransport
sync_enum_type myNBTransport(transaction_type &trans, phase_type &phase, sc_core::sc_time &t)
Definition: SimpleATTarget2.h:86
sc_core::SC_NS
@ SC_NS
Definition: sc_time.hh:43
SimpleATTarget2::mBeginResponseEvent
sc_core::sc_event mBeginResponseEvent
Definition: SimpleATTarget2.h:191
SimpleATTarget2::RESPONSE_DELAY
const sc_core::sc_time RESPONSE_DELAY
Definition: SimpleATTarget2.h:186
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
sc_core::sc_module::dont_initialize
void dont_initialize()
Definition: sc_module.cc:336
SC_METHOD
#define SC_METHOD(name)
Definition: sc_module.hh:300
sc_core::sc_event
Definition: sc_event.hh:169
sc_core::sc_time
Definition: sc_time.hh:49
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
SimpleATTarget2::sync_enum_type
tlm::tlm_sync_enum sync_enum_type
Definition: SimpleATTarget2.h:53
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
tlm::END_RESP
@ END_RESP
Definition: phase.hh:44
tlm_utils::simple_target_socket< SimpleATTarget2 >
gem5::X86ISA::exit
Bitfield< 3 > exit
Definition: misc.hh:854
sc_core::sc_event::notify
void notify()
Definition: sc_event.cc:337
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
tlm::tlm_generic_payload
Definition: gp.hh:133
SimpleATTarget2::mMem
unsigned char mMem[400]
Definition: SimpleATTarget2.h:189
SimpleATTarget2::phase_type
tlm::tlm_phase phase_type
Definition: SimpleATTarget2.h:52
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
SimpleATTarget2::ACCEPT_DELAY
const sc_core::sc_time ACCEPT_DELAY
Definition: SimpleATTarget2.h:185
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
sc_core::sc_module::sensitive
sc_sensitive sensitive
Definition: sc_module.hh:207
SimpleATTarget2::endResponse
void endResponse()
Definition: SimpleATTarget2.h:171
SimpleATTarget2::socket
target_socket_type socket
Definition: SimpleATTarget2.h:57
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:127
tlm::BEGIN_RESP
@ BEGIN_RESP
Definition: phase.hh:43
tlm_utils::simple_target_socket_b::register_nb_transport_fw
void register_nb_transport_fw(MODULE *mod, sync_enum_type(MODULE::*cb)(transaction_type &, phase_type &, sc_core::sc_time &))
Definition: simple_target_socket.h:108

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