gem5  v22.0.0.1
Classes | Namespaces | Enumerations | Functions | Variables
misc.hh File Reference
#include <bitset>
#include <tuple>
#include "arch/arm/regs/misc_types.hh"
#include "base/compiler.hh"
#include "dev/arm/generic_timer_miscregs_types.hh"

Go to the source code of this file.

Classes

struct  gem5::ArmISA::MiscRegNum32
 
struct  gem5::ArmISA::MiscRegNum64
 
struct  std::hash< gem5::ArmISA::MiscRegNum32 >
 
struct  std::hash< gem5::ArmISA::MiscRegNum64 >
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::ArmISA
 
 std
 Overload hash function for BasicBlockRange type.
 

Enumerations

enum  gem5::ArmISA::MiscRegIndex {
  gem5::ArmISA::MISCREG_CPSR = 0, gem5::ArmISA::MISCREG_SPSR, gem5::ArmISA::MISCREG_SPSR_FIQ, gem5::ArmISA::MISCREG_SPSR_IRQ,
  gem5::ArmISA::MISCREG_SPSR_SVC, gem5::ArmISA::MISCREG_SPSR_MON, gem5::ArmISA::MISCREG_SPSR_ABT, gem5::ArmISA::MISCREG_SPSR_HYP,
  gem5::ArmISA::MISCREG_SPSR_UND, gem5::ArmISA::MISCREG_ELR_HYP, gem5::ArmISA::MISCREG_FPSID, gem5::ArmISA::MISCREG_FPSCR,
  gem5::ArmISA::MISCREG_MVFR1, gem5::ArmISA::MISCREG_MVFR0, gem5::ArmISA::MISCREG_FPEXC, gem5::ArmISA::MISCREG_CPSR_MODE,
  gem5::ArmISA::MISCREG_CPSR_Q, gem5::ArmISA::MISCREG_FPSCR_EXC, gem5::ArmISA::MISCREG_FPSCR_QC, gem5::ArmISA::MISCREG_LOCKADDR,
  gem5::ArmISA::MISCREG_LOCKFLAG, gem5::ArmISA::MISCREG_PRRR_MAIR0, gem5::ArmISA::MISCREG_PRRR_MAIR0_NS, gem5::ArmISA::MISCREG_PRRR_MAIR0_S,
  gem5::ArmISA::MISCREG_NMRR_MAIR1, gem5::ArmISA::MISCREG_NMRR_MAIR1_NS, gem5::ArmISA::MISCREG_NMRR_MAIR1_S, gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR,
  gem5::ArmISA::MISCREG_SCTLR_RST, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::ArmISA::MISCREG_TLBINEEDSYNC, gem5::ArmISA::MISCREG_DBGDIDR,
  gem5::ArmISA::MISCREG_DBGDSCRint, gem5::ArmISA::MISCREG_DBGDCCINT, gem5::ArmISA::MISCREG_DBGDTRTXint, gem5::ArmISA::MISCREG_DBGDTRRXint,
  gem5::ArmISA::MISCREG_DBGWFAR, gem5::ArmISA::MISCREG_DBGVCR, gem5::ArmISA::MISCREG_DBGDTRRXext, gem5::ArmISA::MISCREG_DBGDSCRext,
  gem5::ArmISA::MISCREG_DBGDTRTXext, gem5::ArmISA::MISCREG_DBGOSECCR, gem5::ArmISA::MISCREG_DBGBVR0, gem5::ArmISA::MISCREG_DBGBVR1,
  gem5::ArmISA::MISCREG_DBGBVR2, gem5::ArmISA::MISCREG_DBGBVR3, gem5::ArmISA::MISCREG_DBGBVR4, gem5::ArmISA::MISCREG_DBGBVR5,
  gem5::ArmISA::MISCREG_DBGBVR6, gem5::ArmISA::MISCREG_DBGBVR7, gem5::ArmISA::MISCREG_DBGBVR8, gem5::ArmISA::MISCREG_DBGBVR9,
  gem5::ArmISA::MISCREG_DBGBVR10, gem5::ArmISA::MISCREG_DBGBVR11, gem5::ArmISA::MISCREG_DBGBVR12, gem5::ArmISA::MISCREG_DBGBVR13,
  gem5::ArmISA::MISCREG_DBGBVR14, gem5::ArmISA::MISCREG_DBGBVR15, gem5::ArmISA::MISCREG_DBGBCR0, gem5::ArmISA::MISCREG_DBGBCR1,
  gem5::ArmISA::MISCREG_DBGBCR2, gem5::ArmISA::MISCREG_DBGBCR3, gem5::ArmISA::MISCREG_DBGBCR4, gem5::ArmISA::MISCREG_DBGBCR5,
  gem5::ArmISA::MISCREG_DBGBCR6, gem5::ArmISA::MISCREG_DBGBCR7, gem5::ArmISA::MISCREG_DBGBCR8, gem5::ArmISA::MISCREG_DBGBCR9,
  gem5::ArmISA::MISCREG_DBGBCR10, gem5::ArmISA::MISCREG_DBGBCR11, gem5::ArmISA::MISCREG_DBGBCR12, gem5::ArmISA::MISCREG_DBGBCR13,
  gem5::ArmISA::MISCREG_DBGBCR14, gem5::ArmISA::MISCREG_DBGBCR15, gem5::ArmISA::MISCREG_DBGWVR0, gem5::ArmISA::MISCREG_DBGWVR1,
  gem5::ArmISA::MISCREG_DBGWVR2, gem5::ArmISA::MISCREG_DBGWVR3, gem5::ArmISA::MISCREG_DBGWVR4, gem5::ArmISA::MISCREG_DBGWVR5,
  gem5::ArmISA::MISCREG_DBGWVR6, gem5::ArmISA::MISCREG_DBGWVR7, gem5::ArmISA::MISCREG_DBGWVR8, gem5::ArmISA::MISCREG_DBGWVR9,
  gem5::ArmISA::MISCREG_DBGWVR10, gem5::ArmISA::MISCREG_DBGWVR11, gem5::ArmISA::MISCREG_DBGWVR12, gem5::ArmISA::MISCREG_DBGWVR13,
  gem5::ArmISA::MISCREG_DBGWVR14, gem5::ArmISA::MISCREG_DBGWVR15, gem5::ArmISA::MISCREG_DBGWCR0, gem5::ArmISA::MISCREG_DBGWCR1,
  gem5::ArmISA::MISCREG_DBGWCR2, gem5::ArmISA::MISCREG_DBGWCR3, gem5::ArmISA::MISCREG_DBGWCR4, gem5::ArmISA::MISCREG_DBGWCR5,
  gem5::ArmISA::MISCREG_DBGWCR6, gem5::ArmISA::MISCREG_DBGWCR7, gem5::ArmISA::MISCREG_DBGWCR8, gem5::ArmISA::MISCREG_DBGWCR9,
  gem5::ArmISA::MISCREG_DBGWCR10, gem5::ArmISA::MISCREG_DBGWCR11, gem5::ArmISA::MISCREG_DBGWCR12, gem5::ArmISA::MISCREG_DBGWCR13,
  gem5::ArmISA::MISCREG_DBGWCR14, gem5::ArmISA::MISCREG_DBGWCR15, gem5::ArmISA::MISCREG_DBGDRAR, gem5::ArmISA::MISCREG_DBGBXVR0,
  gem5::ArmISA::MISCREG_DBGBXVR1, gem5::ArmISA::MISCREG_DBGBXVR2, gem5::ArmISA::MISCREG_DBGBXVR3, gem5::ArmISA::MISCREG_DBGBXVR4,
  gem5::ArmISA::MISCREG_DBGBXVR5, gem5::ArmISA::MISCREG_DBGBXVR6, gem5::ArmISA::MISCREG_DBGBXVR7, gem5::ArmISA::MISCREG_DBGBXVR8,
  gem5::ArmISA::MISCREG_DBGBXVR9, gem5::ArmISA::MISCREG_DBGBXVR10, gem5::ArmISA::MISCREG_DBGBXVR11, gem5::ArmISA::MISCREG_DBGBXVR12,
  gem5::ArmISA::MISCREG_DBGBXVR13, gem5::ArmISA::MISCREG_DBGBXVR14, gem5::ArmISA::MISCREG_DBGBXVR15, gem5::ArmISA::MISCREG_DBGOSLAR,
  gem5::ArmISA::MISCREG_DBGOSLSR, gem5::ArmISA::MISCREG_DBGOSDLR, gem5::ArmISA::MISCREG_DBGPRCR, gem5::ArmISA::MISCREG_DBGDSAR,
  gem5::ArmISA::MISCREG_DBGCLAIMSET, gem5::ArmISA::MISCREG_DBGCLAIMCLR, gem5::ArmISA::MISCREG_DBGAUTHSTATUS, gem5::ArmISA::MISCREG_DBGDEVID2,
  gem5::ArmISA::MISCREG_DBGDEVID1, gem5::ArmISA::MISCREG_DBGDEVID0, gem5::ArmISA::MISCREG_TEECR, gem5::ArmISA::MISCREG_JIDR,
  gem5::ArmISA::MISCREG_TEEHBR, gem5::ArmISA::MISCREG_JOSCR, gem5::ArmISA::MISCREG_JMCR, gem5::ArmISA::MISCREG_MIDR,
  gem5::ArmISA::MISCREG_CTR, gem5::ArmISA::MISCREG_TCMTR, gem5::ArmISA::MISCREG_TLBTR, gem5::ArmISA::MISCREG_MPIDR,
  gem5::ArmISA::MISCREG_REVIDR, gem5::ArmISA::MISCREG_ID_PFR0, gem5::ArmISA::MISCREG_ID_PFR1, gem5::ArmISA::MISCREG_ID_DFR0,
  gem5::ArmISA::MISCREG_ID_AFR0, gem5::ArmISA::MISCREG_ID_MMFR0, gem5::ArmISA::MISCREG_ID_MMFR1, gem5::ArmISA::MISCREG_ID_MMFR2,
  gem5::ArmISA::MISCREG_ID_MMFR3, gem5::ArmISA::MISCREG_ID_MMFR4, gem5::ArmISA::MISCREG_ID_ISAR0, gem5::ArmISA::MISCREG_ID_ISAR1,
  gem5::ArmISA::MISCREG_ID_ISAR2, gem5::ArmISA::MISCREG_ID_ISAR3, gem5::ArmISA::MISCREG_ID_ISAR4, gem5::ArmISA::MISCREG_ID_ISAR5,
  gem5::ArmISA::MISCREG_ID_ISAR6, gem5::ArmISA::MISCREG_CCSIDR, gem5::ArmISA::MISCREG_CLIDR, gem5::ArmISA::MISCREG_AIDR,
  gem5::ArmISA::MISCREG_CSSELR, gem5::ArmISA::MISCREG_CSSELR_NS, gem5::ArmISA::MISCREG_CSSELR_S, gem5::ArmISA::MISCREG_VPIDR,
  gem5::ArmISA::MISCREG_VMPIDR, gem5::ArmISA::MISCREG_SCTLR, gem5::ArmISA::MISCREG_SCTLR_NS, gem5::ArmISA::MISCREG_SCTLR_S,
  gem5::ArmISA::MISCREG_ACTLR, gem5::ArmISA::MISCREG_ACTLR_NS, gem5::ArmISA::MISCREG_ACTLR_S, gem5::ArmISA::MISCREG_CPACR,
  gem5::ArmISA::MISCREG_SDCR, gem5::ArmISA::MISCREG_SCR, gem5::ArmISA::MISCREG_SDER, gem5::ArmISA::MISCREG_NSACR,
  gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_HACTLR, gem5::ArmISA::MISCREG_HCR, gem5::ArmISA::MISCREG_HCR2,
  gem5::ArmISA::MISCREG_HDCR, gem5::ArmISA::MISCREG_HCPTR, gem5::ArmISA::MISCREG_HSTR, gem5::ArmISA::MISCREG_HACR,
  gem5::ArmISA::MISCREG_TTBR0, gem5::ArmISA::MISCREG_TTBR0_NS, gem5::ArmISA::MISCREG_TTBR0_S, gem5::ArmISA::MISCREG_TTBR1,
  gem5::ArmISA::MISCREG_TTBR1_NS, gem5::ArmISA::MISCREG_TTBR1_S, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::MISCREG_TTBCR_NS,
  gem5::ArmISA::MISCREG_TTBCR_S, gem5::ArmISA::MISCREG_HTCR, gem5::ArmISA::MISCREG_VTCR, gem5::ArmISA::MISCREG_DACR,
  gem5::ArmISA::MISCREG_DACR_NS, gem5::ArmISA::MISCREG_DACR_S, gem5::ArmISA::MISCREG_DFSR, gem5::ArmISA::MISCREG_DFSR_NS,
  gem5::ArmISA::MISCREG_DFSR_S, gem5::ArmISA::MISCREG_IFSR, gem5::ArmISA::MISCREG_IFSR_NS, gem5::ArmISA::MISCREG_IFSR_S,
  gem5::ArmISA::MISCREG_ADFSR, gem5::ArmISA::MISCREG_ADFSR_NS, gem5::ArmISA::MISCREG_ADFSR_S, gem5::ArmISA::MISCREG_AIFSR,
  gem5::ArmISA::MISCREG_AIFSR_NS, gem5::ArmISA::MISCREG_AIFSR_S, gem5::ArmISA::MISCREG_HADFSR, gem5::ArmISA::MISCREG_HAIFSR,
  gem5::ArmISA::MISCREG_HSR, gem5::ArmISA::MISCREG_DFAR, gem5::ArmISA::MISCREG_DFAR_NS, gem5::ArmISA::MISCREG_DFAR_S,
  gem5::ArmISA::MISCREG_IFAR, gem5::ArmISA::MISCREG_IFAR_NS, gem5::ArmISA::MISCREG_IFAR_S, gem5::ArmISA::MISCREG_HDFAR,
  gem5::ArmISA::MISCREG_HIFAR, gem5::ArmISA::MISCREG_HPFAR, gem5::ArmISA::MISCREG_ICIALLUIS, gem5::ArmISA::MISCREG_BPIALLIS,
  gem5::ArmISA::MISCREG_PAR, gem5::ArmISA::MISCREG_PAR_NS, gem5::ArmISA::MISCREG_PAR_S, gem5::ArmISA::MISCREG_ICIALLU,
  gem5::ArmISA::MISCREG_ICIMVAU, gem5::ArmISA::MISCREG_CP15ISB, gem5::ArmISA::MISCREG_BPIALL, gem5::ArmISA::MISCREG_BPIMVA,
  gem5::ArmISA::MISCREG_DCIMVAC, gem5::ArmISA::MISCREG_DCISW, gem5::ArmISA::MISCREG_ATS1CPR, gem5::ArmISA::MISCREG_ATS1CPW,
  gem5::ArmISA::MISCREG_ATS1CUR, gem5::ArmISA::MISCREG_ATS1CUW, gem5::ArmISA::MISCREG_ATS12NSOPR, gem5::ArmISA::MISCREG_ATS12NSOPW,
  gem5::ArmISA::MISCREG_ATS12NSOUR, gem5::ArmISA::MISCREG_ATS12NSOUW, gem5::ArmISA::MISCREG_DCCMVAC, gem5::ArmISA::MISCREG_DCCSW,
  gem5::ArmISA::MISCREG_CP15DSB, gem5::ArmISA::MISCREG_CP15DMB, gem5::ArmISA::MISCREG_DCCMVAU, gem5::ArmISA::MISCREG_DCCIMVAC,
  gem5::ArmISA::MISCREG_DCCISW, gem5::ArmISA::MISCREG_ATS1HR, gem5::ArmISA::MISCREG_ATS1HW, gem5::ArmISA::MISCREG_TLBIALLIS,
  gem5::ArmISA::MISCREG_TLBIMVAIS, gem5::ArmISA::MISCREG_TLBIASIDIS, gem5::ArmISA::MISCREG_TLBIMVAAIS, gem5::ArmISA::MISCREG_TLBIMVALIS,
  gem5::ArmISA::MISCREG_TLBIMVAALIS, gem5::ArmISA::MISCREG_ITLBIALL, gem5::ArmISA::MISCREG_ITLBIMVA, gem5::ArmISA::MISCREG_ITLBIASID,
  gem5::ArmISA::MISCREG_DTLBIALL, gem5::ArmISA::MISCREG_DTLBIMVA, gem5::ArmISA::MISCREG_DTLBIASID, gem5::ArmISA::MISCREG_TLBIALL,
  gem5::ArmISA::MISCREG_TLBIMVA, gem5::ArmISA::MISCREG_TLBIASID, gem5::ArmISA::MISCREG_TLBIMVAA, gem5::ArmISA::MISCREG_TLBIMVAL,
  gem5::ArmISA::MISCREG_TLBIMVAAL, gem5::ArmISA::MISCREG_TLBIIPAS2IS, gem5::ArmISA::MISCREG_TLBIIPAS2LIS, gem5::ArmISA::MISCREG_TLBIALLHIS,
  gem5::ArmISA::MISCREG_TLBIMVAHIS, gem5::ArmISA::MISCREG_TLBIALLNSNHIS, gem5::ArmISA::MISCREG_TLBIMVALHIS, gem5::ArmISA::MISCREG_TLBIIPAS2,
  gem5::ArmISA::MISCREG_TLBIIPAS2L, gem5::ArmISA::MISCREG_TLBIALLH, gem5::ArmISA::MISCREG_TLBIMVAH, gem5::ArmISA::MISCREG_TLBIALLNSNH,
  gem5::ArmISA::MISCREG_TLBIMVALH, gem5::ArmISA::MISCREG_PMCR, gem5::ArmISA::MISCREG_PMCNTENSET, gem5::ArmISA::MISCREG_PMCNTENCLR,
  gem5::ArmISA::MISCREG_PMOVSR, gem5::ArmISA::MISCREG_PMSWINC, gem5::ArmISA::MISCREG_PMSELR, gem5::ArmISA::MISCREG_PMCEID0,
  gem5::ArmISA::MISCREG_PMCEID1, gem5::ArmISA::MISCREG_PMCCNTR, gem5::ArmISA::MISCREG_PMXEVTYPER, gem5::ArmISA::MISCREG_PMCCFILTR,
  gem5::ArmISA::MISCREG_PMXEVCNTR, gem5::ArmISA::MISCREG_PMUSERENR, gem5::ArmISA::MISCREG_PMINTENSET, gem5::ArmISA::MISCREG_PMINTENCLR,
  gem5::ArmISA::MISCREG_PMOVSSET, gem5::ArmISA::MISCREG_L2CTLR, gem5::ArmISA::MISCREG_L2ECTLR, gem5::ArmISA::MISCREG_PRRR,
  gem5::ArmISA::MISCREG_PRRR_NS, gem5::ArmISA::MISCREG_PRRR_S, gem5::ArmISA::MISCREG_MAIR0, gem5::ArmISA::MISCREG_MAIR0_NS,
  gem5::ArmISA::MISCREG_MAIR0_S, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_NMRR_NS, gem5::ArmISA::MISCREG_NMRR_S,
  gem5::ArmISA::MISCREG_MAIR1, gem5::ArmISA::MISCREG_MAIR1_NS, gem5::ArmISA::MISCREG_MAIR1_S, gem5::ArmISA::MISCREG_AMAIR0,
  gem5::ArmISA::MISCREG_AMAIR0_NS, gem5::ArmISA::MISCREG_AMAIR0_S, gem5::ArmISA::MISCREG_AMAIR1, gem5::ArmISA::MISCREG_AMAIR1_NS,
  gem5::ArmISA::MISCREG_AMAIR1_S, gem5::ArmISA::MISCREG_HMAIR0, gem5::ArmISA::MISCREG_HMAIR1, gem5::ArmISA::MISCREG_HAMAIR0,
  gem5::ArmISA::MISCREG_HAMAIR1, gem5::ArmISA::MISCREG_VBAR, gem5::ArmISA::MISCREG_VBAR_NS, gem5::ArmISA::MISCREG_VBAR_S,
  gem5::ArmISA::MISCREG_MVBAR, gem5::ArmISA::MISCREG_RMR, gem5::ArmISA::MISCREG_ISR, gem5::ArmISA::MISCREG_HVBAR,
  gem5::ArmISA::MISCREG_FCSEIDR, gem5::ArmISA::MISCREG_CONTEXTIDR, gem5::ArmISA::MISCREG_CONTEXTIDR_NS, gem5::ArmISA::MISCREG_CONTEXTIDR_S,
  gem5::ArmISA::MISCREG_TPIDRURW, gem5::ArmISA::MISCREG_TPIDRURW_NS, gem5::ArmISA::MISCREG_TPIDRURW_S, gem5::ArmISA::MISCREG_TPIDRURO,
  gem5::ArmISA::MISCREG_TPIDRURO_NS, gem5::ArmISA::MISCREG_TPIDRURO_S, gem5::ArmISA::MISCREG_TPIDRPRW, gem5::ArmISA::MISCREG_TPIDRPRW_NS,
  gem5::ArmISA::MISCREG_TPIDRPRW_S, gem5::ArmISA::MISCREG_HTPIDR, gem5::ArmISA::MISCREG_CNTFRQ, gem5::ArmISA::MISCREG_CNTPCT,
  gem5::ArmISA::MISCREG_CNTVCT, gem5::ArmISA::MISCREG_CNTP_CTL, gem5::ArmISA::MISCREG_CNTP_CTL_NS, gem5::ArmISA::MISCREG_CNTP_CTL_S,
  gem5::ArmISA::MISCREG_CNTP_CVAL, gem5::ArmISA::MISCREG_CNTP_CVAL_NS, gem5::ArmISA::MISCREG_CNTP_CVAL_S, gem5::ArmISA::MISCREG_CNTP_TVAL,
  gem5::ArmISA::MISCREG_CNTP_TVAL_NS, gem5::ArmISA::MISCREG_CNTP_TVAL_S, gem5::ArmISA::MISCREG_CNTV_CTL, gem5::ArmISA::MISCREG_CNTV_CVAL,
  gem5::ArmISA::MISCREG_CNTV_TVAL, gem5::ArmISA::MISCREG_CNTKCTL, gem5::ArmISA::MISCREG_CNTHCTL, gem5::ArmISA::MISCREG_CNTHP_CTL,
  gem5::ArmISA::MISCREG_CNTHP_CVAL, gem5::ArmISA::MISCREG_CNTHP_TVAL, gem5::ArmISA::MISCREG_CNTVOFF, gem5::ArmISA::MISCREG_IL1DATA0,
  gem5::ArmISA::MISCREG_IL1DATA1, gem5::ArmISA::MISCREG_IL1DATA2, gem5::ArmISA::MISCREG_IL1DATA3, gem5::ArmISA::MISCREG_DL1DATA0,
  gem5::ArmISA::MISCREG_DL1DATA1, gem5::ArmISA::MISCREG_DL1DATA2, gem5::ArmISA::MISCREG_DL1DATA3, gem5::ArmISA::MISCREG_DL1DATA4,
  gem5::ArmISA::MISCREG_RAMINDEX, gem5::ArmISA::MISCREG_L2ACTLR, gem5::ArmISA::MISCREG_CBAR, gem5::ArmISA::MISCREG_HTTBR,
  gem5::ArmISA::MISCREG_VTTBR, gem5::ArmISA::MISCREG_CPUMERRSR, gem5::ArmISA::MISCREG_L2MERRSR, gem5::ArmISA::MISCREG_MDCCINT_EL1,
  gem5::ArmISA::MISCREG_OSDTRRX_EL1, gem5::ArmISA::MISCREG_MDSCR_EL1, gem5::ArmISA::MISCREG_OSDTRTX_EL1, gem5::ArmISA::MISCREG_OSECCR_EL1,
  gem5::ArmISA::MISCREG_DBGBVR0_EL1, gem5::ArmISA::MISCREG_DBGBVR1_EL1, gem5::ArmISA::MISCREG_DBGBVR2_EL1, gem5::ArmISA::MISCREG_DBGBVR3_EL1,
  gem5::ArmISA::MISCREG_DBGBVR4_EL1, gem5::ArmISA::MISCREG_DBGBVR5_EL1, gem5::ArmISA::MISCREG_DBGBVR6_EL1, gem5::ArmISA::MISCREG_DBGBVR7_EL1,
  gem5::ArmISA::MISCREG_DBGBVR8_EL1, gem5::ArmISA::MISCREG_DBGBVR9_EL1, gem5::ArmISA::MISCREG_DBGBVR10_EL1, gem5::ArmISA::MISCREG_DBGBVR11_EL1,
  gem5::ArmISA::MISCREG_DBGBVR12_EL1, gem5::ArmISA::MISCREG_DBGBVR13_EL1, gem5::ArmISA::MISCREG_DBGBVR14_EL1, gem5::ArmISA::MISCREG_DBGBVR15_EL1,
  gem5::ArmISA::MISCREG_DBGBCR0_EL1, gem5::ArmISA::MISCREG_DBGBCR1_EL1, gem5::ArmISA::MISCREG_DBGBCR2_EL1, gem5::ArmISA::MISCREG_DBGBCR3_EL1,
  gem5::ArmISA::MISCREG_DBGBCR4_EL1, gem5::ArmISA::MISCREG_DBGBCR5_EL1, gem5::ArmISA::MISCREG_DBGBCR6_EL1, gem5::ArmISA::MISCREG_DBGBCR7_EL1,
  gem5::ArmISA::MISCREG_DBGBCR8_EL1, gem5::ArmISA::MISCREG_DBGBCR9_EL1, gem5::ArmISA::MISCREG_DBGBCR10_EL1, gem5::ArmISA::MISCREG_DBGBCR11_EL1,
  gem5::ArmISA::MISCREG_DBGBCR12_EL1, gem5::ArmISA::MISCREG_DBGBCR13_EL1, gem5::ArmISA::MISCREG_DBGBCR14_EL1, gem5::ArmISA::MISCREG_DBGBCR15_EL1,
  gem5::ArmISA::MISCREG_DBGWVR0_EL1, gem5::ArmISA::MISCREG_DBGWVR1_EL1, gem5::ArmISA::MISCREG_DBGWVR2_EL1, gem5::ArmISA::MISCREG_DBGWVR3_EL1,
  gem5::ArmISA::MISCREG_DBGWVR4_EL1, gem5::ArmISA::MISCREG_DBGWVR5_EL1, gem5::ArmISA::MISCREG_DBGWVR6_EL1, gem5::ArmISA::MISCREG_DBGWVR7_EL1,
  gem5::ArmISA::MISCREG_DBGWVR8_EL1, gem5::ArmISA::MISCREG_DBGWVR9_EL1, gem5::ArmISA::MISCREG_DBGWVR10_EL1, gem5::ArmISA::MISCREG_DBGWVR11_EL1,
  gem5::ArmISA::MISCREG_DBGWVR12_EL1, gem5::ArmISA::MISCREG_DBGWVR13_EL1, gem5::ArmISA::MISCREG_DBGWVR14_EL1, gem5::ArmISA::MISCREG_DBGWVR15_EL1,
  gem5::ArmISA::MISCREG_DBGWCR0_EL1, gem5::ArmISA::MISCREG_DBGWCR1_EL1, gem5::ArmISA::MISCREG_DBGWCR2_EL1, gem5::ArmISA::MISCREG_DBGWCR3_EL1,
  gem5::ArmISA::MISCREG_DBGWCR4_EL1, gem5::ArmISA::MISCREG_DBGWCR5_EL1, gem5::ArmISA::MISCREG_DBGWCR6_EL1, gem5::ArmISA::MISCREG_DBGWCR7_EL1,
  gem5::ArmISA::MISCREG_DBGWCR8_EL1, gem5::ArmISA::MISCREG_DBGWCR9_EL1, gem5::ArmISA::MISCREG_DBGWCR10_EL1, gem5::ArmISA::MISCREG_DBGWCR11_EL1,
  gem5::ArmISA::MISCREG_DBGWCR12_EL1, gem5::ArmISA::MISCREG_DBGWCR13_EL1, gem5::ArmISA::MISCREG_DBGWCR14_EL1, gem5::ArmISA::MISCREG_DBGWCR15_EL1,
  gem5::ArmISA::MISCREG_MDCCSR_EL0, gem5::ArmISA::MISCREG_MDDTR_EL0, gem5::ArmISA::MISCREG_MDDTRTX_EL0, gem5::ArmISA::MISCREG_MDDTRRX_EL0,
  gem5::ArmISA::MISCREG_DBGVCR32_EL2, gem5::ArmISA::MISCREG_MDRAR_EL1, gem5::ArmISA::MISCREG_OSLAR_EL1, gem5::ArmISA::MISCREG_OSLSR_EL1,
  gem5::ArmISA::MISCREG_OSDLR_EL1, gem5::ArmISA::MISCREG_DBGPRCR_EL1, gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1, gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1,
  gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1, gem5::ArmISA::MISCREG_TEECR32_EL1, gem5::ArmISA::MISCREG_TEEHBR32_EL1, gem5::ArmISA::MISCREG_MIDR_EL1,
  gem5::ArmISA::MISCREG_MPIDR_EL1, gem5::ArmISA::MISCREG_REVIDR_EL1, gem5::ArmISA::MISCREG_ID_PFR0_EL1, gem5::ArmISA::MISCREG_ID_PFR1_EL1,
  gem5::ArmISA::MISCREG_ID_DFR0_EL1, gem5::ArmISA::MISCREG_ID_AFR0_EL1, gem5::ArmISA::MISCREG_ID_MMFR0_EL1, gem5::ArmISA::MISCREG_ID_MMFR1_EL1,
  gem5::ArmISA::MISCREG_ID_MMFR2_EL1, gem5::ArmISA::MISCREG_ID_MMFR3_EL1, gem5::ArmISA::MISCREG_ID_MMFR4_EL1, gem5::ArmISA::MISCREG_ID_ISAR0_EL1,
  gem5::ArmISA::MISCREG_ID_ISAR1_EL1, gem5::ArmISA::MISCREG_ID_ISAR2_EL1, gem5::ArmISA::MISCREG_ID_ISAR3_EL1, gem5::ArmISA::MISCREG_ID_ISAR4_EL1,
  gem5::ArmISA::MISCREG_ID_ISAR5_EL1, gem5::ArmISA::MISCREG_ID_ISAR6_EL1, gem5::ArmISA::MISCREG_MVFR0_EL1, gem5::ArmISA::MISCREG_MVFR1_EL1,
  gem5::ArmISA::MISCREG_MVFR2_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1,
  gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1,
  gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_CCSIDR_EL1,
  gem5::ArmISA::MISCREG_CLIDR_EL1, gem5::ArmISA::MISCREG_AIDR_EL1, gem5::ArmISA::MISCREG_CSSELR_EL1, gem5::ArmISA::MISCREG_CTR_EL0,
  gem5::ArmISA::MISCREG_DCZID_EL0, gem5::ArmISA::MISCREG_VPIDR_EL2, gem5::ArmISA::MISCREG_VMPIDR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL1,
  gem5::ArmISA::MISCREG_SCTLR_EL12, gem5::ArmISA::MISCREG_ACTLR_EL1, gem5::ArmISA::MISCREG_CPACR_EL1, gem5::ArmISA::MISCREG_CPACR_EL12,
  gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_ACTLR_EL2, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_MDCR_EL2,
  gem5::ArmISA::MISCREG_CPTR_EL2, gem5::ArmISA::MISCREG_HSTR_EL2, gem5::ArmISA::MISCREG_HACR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL3,
  gem5::ArmISA::MISCREG_ACTLR_EL3, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SDER32_EL3, gem5::ArmISA::MISCREG_CPTR_EL3,
  gem5::ArmISA::MISCREG_MDCR_EL3, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL12, gem5::ArmISA::MISCREG_TTBR1_EL1,
  gem5::ArmISA::MISCREG_TTBR1_EL12, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL12, gem5::ArmISA::MISCREG_TTBR0_EL2,
  gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_VTTBR_EL2, gem5::ArmISA::MISCREG_VTCR_EL2, gem5::ArmISA::MISCREG_VSTTBR_EL2,
  gem5::ArmISA::MISCREG_VSTCR_EL2, gem5::ArmISA::MISCREG_TTBR0_EL3, gem5::ArmISA::MISCREG_TCR_EL3, gem5::ArmISA::MISCREG_DACR32_EL2,
  gem5::ArmISA::MISCREG_SPSR_EL1, gem5::ArmISA::MISCREG_SPSR_EL12, gem5::ArmISA::MISCREG_ELR_EL1, gem5::ArmISA::MISCREG_ELR_EL12,
  gem5::ArmISA::MISCREG_SP_EL0, gem5::ArmISA::MISCREG_SPSEL, gem5::ArmISA::MISCREG_CURRENTEL, gem5::ArmISA::MISCREG_NZCV,
  gem5::ArmISA::MISCREG_DAIF, gem5::ArmISA::MISCREG_FPCR, gem5::ArmISA::MISCREG_FPSR, gem5::ArmISA::MISCREG_DSPSR_EL0,
  gem5::ArmISA::MISCREG_DLR_EL0, gem5::ArmISA::MISCREG_SPSR_EL2, gem5::ArmISA::MISCREG_ELR_EL2, gem5::ArmISA::MISCREG_SP_EL1,
  gem5::ArmISA::MISCREG_SPSR_IRQ_AA64, gem5::ArmISA::MISCREG_SPSR_ABT_AA64, gem5::ArmISA::MISCREG_SPSR_UND_AA64, gem5::ArmISA::MISCREG_SPSR_FIQ_AA64,
  gem5::ArmISA::MISCREG_SPSR_EL3, gem5::ArmISA::MISCREG_ELR_EL3, gem5::ArmISA::MISCREG_SP_EL2, gem5::ArmISA::MISCREG_AFSR0_EL1,
  gem5::ArmISA::MISCREG_AFSR0_EL12, gem5::ArmISA::MISCREG_AFSR1_EL1, gem5::ArmISA::MISCREG_AFSR1_EL12, gem5::ArmISA::MISCREG_ESR_EL1,
  gem5::ArmISA::MISCREG_ESR_EL12, gem5::ArmISA::MISCREG_IFSR32_EL2, gem5::ArmISA::MISCREG_AFSR0_EL2, gem5::ArmISA::MISCREG_AFSR1_EL2,
  gem5::ArmISA::MISCREG_ESR_EL2, gem5::ArmISA::MISCREG_FPEXC32_EL2, gem5::ArmISA::MISCREG_AFSR0_EL3, gem5::ArmISA::MISCREG_AFSR1_EL3,
  gem5::ArmISA::MISCREG_ESR_EL3, gem5::ArmISA::MISCREG_FAR_EL1, gem5::ArmISA::MISCREG_FAR_EL12, gem5::ArmISA::MISCREG_FAR_EL2,
  gem5::ArmISA::MISCREG_HPFAR_EL2, gem5::ArmISA::MISCREG_FAR_EL3, gem5::ArmISA::MISCREG_IC_IALLUIS, gem5::ArmISA::MISCREG_PAR_EL1,
  gem5::ArmISA::MISCREG_IC_IALLU, gem5::ArmISA::MISCREG_DC_IVAC_Xt, gem5::ArmISA::MISCREG_DC_ISW_Xt, gem5::ArmISA::MISCREG_AT_S1E1R_Xt,
  gem5::ArmISA::MISCREG_AT_S1E1W_Xt, gem5::ArmISA::MISCREG_AT_S1E0R_Xt, gem5::ArmISA::MISCREG_AT_S1E0W_Xt, gem5::ArmISA::MISCREG_DC_CSW_Xt,
  gem5::ArmISA::MISCREG_DC_CISW_Xt, gem5::ArmISA::MISCREG_DC_ZVA_Xt, gem5::ArmISA::MISCREG_IC_IVAU_Xt, gem5::ArmISA::MISCREG_DC_CVAC_Xt,
  gem5::ArmISA::MISCREG_DC_CVAU_Xt, gem5::ArmISA::MISCREG_DC_CIVAC_Xt, gem5::ArmISA::MISCREG_AT_S1E2R_Xt, gem5::ArmISA::MISCREG_AT_S1E2W_Xt,
  gem5::ArmISA::MISCREG_AT_S12E1R_Xt, gem5::ArmISA::MISCREG_AT_S12E1W_Xt, gem5::ArmISA::MISCREG_AT_S12E0R_Xt, gem5::ArmISA::MISCREG_AT_S12E0W_Xt,
  gem5::ArmISA::MISCREG_AT_S1E3R_Xt, gem5::ArmISA::MISCREG_AT_S1E3W_Xt, gem5::ArmISA::MISCREG_TLBI_VMALLE1IS, gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt,
  gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt,
  gem5::ArmISA::MISCREG_TLBI_VMALLE1, gem5::ArmISA::MISCREG_TLBI_VAE1_Xt, gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt, gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt,
  gem5::ArmISA::MISCREG_TLBI_VALE1_Xt, gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt,
  gem5::ArmISA::MISCREG_TLBI_ALLE2IS, gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt, gem5::ArmISA::MISCREG_TLBI_ALLE1IS, gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt,
  gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS, gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, gem5::ArmISA::MISCREG_TLBI_ALLE2,
  gem5::ArmISA::MISCREG_TLBI_VAE2_Xt, gem5::ArmISA::MISCREG_TLBI_ALLE1, gem5::ArmISA::MISCREG_TLBI_VALE2_Xt, gem5::ArmISA::MISCREG_TLBI_VMALLS12E1,
  gem5::ArmISA::MISCREG_TLBI_ALLE3IS, gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt, gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt, gem5::ArmISA::MISCREG_TLBI_ALLE3,
  gem5::ArmISA::MISCREG_TLBI_VAE3_Xt, gem5::ArmISA::MISCREG_TLBI_VALE3_Xt, gem5::ArmISA::MISCREG_PMINTENSET_EL1, gem5::ArmISA::MISCREG_PMINTENCLR_EL1,
  gem5::ArmISA::MISCREG_PMCR_EL0, gem5::ArmISA::MISCREG_PMCNTENSET_EL0, gem5::ArmISA::MISCREG_PMCNTENCLR_EL0, gem5::ArmISA::MISCREG_PMOVSCLR_EL0,
  gem5::ArmISA::MISCREG_PMSWINC_EL0, gem5::ArmISA::MISCREG_PMSELR_EL0, gem5::ArmISA::MISCREG_PMCEID0_EL0, gem5::ArmISA::MISCREG_PMCEID1_EL0,
  gem5::ArmISA::MISCREG_PMCCNTR_EL0, gem5::ArmISA::MISCREG_PMXEVTYPER_EL0, gem5::ArmISA::MISCREG_PMCCFILTR_EL0, gem5::ArmISA::MISCREG_PMXEVCNTR_EL0,
  gem5::ArmISA::MISCREG_PMUSERENR_EL0, gem5::ArmISA::MISCREG_PMOVSSET_EL0, gem5::ArmISA::MISCREG_MAIR_EL1, gem5::ArmISA::MISCREG_MAIR_EL12,
  gem5::ArmISA::MISCREG_AMAIR_EL1, gem5::ArmISA::MISCREG_AMAIR_EL12, gem5::ArmISA::MISCREG_MAIR_EL2, gem5::ArmISA::MISCREG_AMAIR_EL2,
  gem5::ArmISA::MISCREG_MAIR_EL3, gem5::ArmISA::MISCREG_AMAIR_EL3, gem5::ArmISA::MISCREG_L2CTLR_EL1, gem5::ArmISA::MISCREG_L2ECTLR_EL1,
  gem5::ArmISA::MISCREG_VBAR_EL1, gem5::ArmISA::MISCREG_VBAR_EL12, gem5::ArmISA::MISCREG_RVBAR_EL1, gem5::ArmISA::MISCREG_ISR_EL1,
  gem5::ArmISA::MISCREG_VBAR_EL2, gem5::ArmISA::MISCREG_RVBAR_EL2, gem5::ArmISA::MISCREG_VBAR_EL3, gem5::ArmISA::MISCREG_RVBAR_EL3,
  gem5::ArmISA::MISCREG_RMR_EL3, gem5::ArmISA::MISCREG_CONTEXTIDR_EL1, gem5::ArmISA::MISCREG_CONTEXTIDR_EL12, gem5::ArmISA::MISCREG_TPIDR_EL1,
  gem5::ArmISA::MISCREG_TPIDR_EL0, gem5::ArmISA::MISCREG_TPIDRRO_EL0, gem5::ArmISA::MISCREG_TPIDR_EL2, gem5::ArmISA::MISCREG_TPIDR_EL3,
  gem5::ArmISA::MISCREG_CNTFRQ_EL0, gem5::ArmISA::MISCREG_CNTPCT_EL0, gem5::ArmISA::MISCREG_CNTVCT_EL0, gem5::ArmISA::MISCREG_CNTP_CTL_EL0,
  gem5::ArmISA::MISCREG_CNTP_CVAL_EL0, gem5::ArmISA::MISCREG_CNTP_TVAL_EL0, gem5::ArmISA::MISCREG_CNTV_CTL_EL0, gem5::ArmISA::MISCREG_CNTV_CVAL_EL0,
  gem5::ArmISA::MISCREG_CNTV_TVAL_EL0, gem5::ArmISA::MISCREG_CNTP_CTL_EL02, gem5::ArmISA::MISCREG_CNTP_CVAL_EL02, gem5::ArmISA::MISCREG_CNTP_TVAL_EL02,
  gem5::ArmISA::MISCREG_CNTV_CTL_EL02, gem5::ArmISA::MISCREG_CNTV_CVAL_EL02, gem5::ArmISA::MISCREG_CNTV_TVAL_EL02, gem5::ArmISA::MISCREG_CNTKCTL_EL1,
  gem5::ArmISA::MISCREG_CNTKCTL_EL12, gem5::ArmISA::MISCREG_CNTPS_CTL_EL1, gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1, gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1,
  gem5::ArmISA::MISCREG_CNTHCTL_EL2, gem5::ArmISA::MISCREG_CNTHP_CTL_EL2, gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2,
  gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2, gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHV_CTL_EL2,
  gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2, gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2,
  gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2, gem5::ArmISA::MISCREG_CNTVOFF_EL2, gem5::ArmISA::MISCREG_PMEVCNTR0_EL0, gem5::ArmISA::MISCREG_PMEVCNTR1_EL0,
  gem5::ArmISA::MISCREG_PMEVCNTR2_EL0, gem5::ArmISA::MISCREG_PMEVCNTR3_EL0, gem5::ArmISA::MISCREG_PMEVCNTR4_EL0, gem5::ArmISA::MISCREG_PMEVCNTR5_EL0,
  gem5::ArmISA::MISCREG_PMEVTYPER0_EL0, gem5::ArmISA::MISCREG_PMEVTYPER1_EL0, gem5::ArmISA::MISCREG_PMEVTYPER2_EL0, gem5::ArmISA::MISCREG_PMEVTYPER3_EL0,
  gem5::ArmISA::MISCREG_PMEVTYPER4_EL0, gem5::ArmISA::MISCREG_PMEVTYPER5_EL0, gem5::ArmISA::MISCREG_IL1DATA0_EL1, gem5::ArmISA::MISCREG_IL1DATA1_EL1,
  gem5::ArmISA::MISCREG_IL1DATA2_EL1, gem5::ArmISA::MISCREG_IL1DATA3_EL1, gem5::ArmISA::MISCREG_DL1DATA0_EL1, gem5::ArmISA::MISCREG_DL1DATA1_EL1,
  gem5::ArmISA::MISCREG_DL1DATA2_EL1, gem5::ArmISA::MISCREG_DL1DATA3_EL1, gem5::ArmISA::MISCREG_DL1DATA4_EL1, gem5::ArmISA::MISCREG_L2ACTLR_EL1,
  gem5::ArmISA::MISCREG_CPUACTLR_EL1, gem5::ArmISA::MISCREG_CPUECTLR_EL1, gem5::ArmISA::MISCREG_CPUMERRSR_EL1, gem5::ArmISA::MISCREG_L2MERRSR_EL1,
  gem5::ArmISA::MISCREG_CBAR_EL1, gem5::ArmISA::MISCREG_CONTEXTIDR_EL2, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1,
  gem5::ArmISA::MISCREG_APDAKeyHi_EL1, gem5::ArmISA::MISCREG_APDAKeyLo_EL1, gem5::ArmISA::MISCREG_APDBKeyHi_EL1, gem5::ArmISA::MISCREG_APDBKeyLo_EL1,
  gem5::ArmISA::MISCREG_APGAKeyHi_EL1, gem5::ArmISA::MISCREG_APGAKeyLo_EL1, gem5::ArmISA::MISCREG_APIAKeyHi_EL1, gem5::ArmISA::MISCREG_APIAKeyLo_EL1,
  gem5::ArmISA::MISCREG_APIBKeyHi_EL1, gem5::ArmISA::MISCREG_APIBKeyLo_EL1, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_IAR0_EL1,
  gem5::ArmISA::MISCREG_ICC_EOIR0_EL1, gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1,
  gem5::ArmISA::MISCREG_ICC_AP0R1_EL1, gem5::ArmISA::MISCREG_ICC_AP0R2_EL1, gem5::ArmISA::MISCREG_ICC_AP0R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1,
  gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS,
  gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S,
  gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S, gem5::ArmISA::MISCREG_ICC_DIR_EL1,
  gem5::ArmISA::MISCREG_ICC_RPR_EL1, gem5::ArmISA::MISCREG_ICC_SGI1R_EL1, gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1, gem5::ArmISA::MISCREG_ICC_SGI0R_EL1,
  gem5::ArmISA::MISCREG_ICC_IAR1_EL1, gem5::ArmISA::MISCREG_ICC_EOIR1_EL1, gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1,
  gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS,
  gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICC_SRE_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS, gem5::ArmISA::MISCREG_ICC_SRE_EL1_S,
  gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S,
  gem5::ArmISA::MISCREG_ICC_SRE_EL2, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::ArmISA::MISCREG_ICC_SRE_EL3, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3,
  gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP0R1_EL2, gem5::ArmISA::MISCREG_ICH_AP0R2_EL2, gem5::ArmISA::MISCREG_ICH_AP0R3_EL2,
  gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R1_EL2, gem5::ArmISA::MISCREG_ICH_AP1R2_EL2, gem5::ArmISA::MISCREG_ICH_AP1R3_EL2,
  gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_VTR_EL2, gem5::ArmISA::MISCREG_ICH_MISR_EL2, gem5::ArmISA::MISCREG_ICH_EISR_EL2,
  gem5::ArmISA::MISCREG_ICH_ELRSR_EL2, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_LR1_EL2,
  gem5::ArmISA::MISCREG_ICH_LR2_EL2, gem5::ArmISA::MISCREG_ICH_LR3_EL2, gem5::ArmISA::MISCREG_ICH_LR4_EL2, gem5::ArmISA::MISCREG_ICH_LR5_EL2,
  gem5::ArmISA::MISCREG_ICH_LR6_EL2, gem5::ArmISA::MISCREG_ICH_LR7_EL2, gem5::ArmISA::MISCREG_ICH_LR8_EL2, gem5::ArmISA::MISCREG_ICH_LR9_EL2,
  gem5::ArmISA::MISCREG_ICH_LR10_EL2, gem5::ArmISA::MISCREG_ICH_LR11_EL2, gem5::ArmISA::MISCREG_ICH_LR12_EL2, gem5::ArmISA::MISCREG_ICH_LR13_EL2,
  gem5::ArmISA::MISCREG_ICH_LR14_EL2, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICV_PMR_EL1, gem5::ArmISA::MISCREG_ICV_IAR0_EL1,
  gem5::ArmISA::MISCREG_ICV_EOIR0_EL1, gem5::ArmISA::MISCREG_ICV_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICV_BPR0_EL1, gem5::ArmISA::MISCREG_ICV_AP0R0_EL1,
  gem5::ArmISA::MISCREG_ICV_AP0R1_EL1, gem5::ArmISA::MISCREG_ICV_AP0R2_EL1, gem5::ArmISA::MISCREG_ICV_AP0R3_EL1, gem5::ArmISA::MISCREG_ICV_AP1R0_EL1,
  gem5::ArmISA::MISCREG_ICV_AP1R0_EL1_NS, gem5::ArmISA::MISCREG_ICV_AP1R0_EL1_S, gem5::ArmISA::MISCREG_ICV_AP1R1_EL1, gem5::ArmISA::MISCREG_ICV_AP1R1_EL1_NS,
  gem5::ArmISA::MISCREG_ICV_AP1R1_EL1_S, gem5::ArmISA::MISCREG_ICV_AP1R2_EL1, gem5::ArmISA::MISCREG_ICV_AP1R2_EL1_NS, gem5::ArmISA::MISCREG_ICV_AP1R2_EL1_S,
  gem5::ArmISA::MISCREG_ICV_AP1R3_EL1, gem5::ArmISA::MISCREG_ICV_AP1R3_EL1_NS, gem5::ArmISA::MISCREG_ICV_AP1R3_EL1_S, gem5::ArmISA::MISCREG_ICV_DIR_EL1,
  gem5::ArmISA::MISCREG_ICV_RPR_EL1, gem5::ArmISA::MISCREG_ICV_SGI1R_EL1, gem5::ArmISA::MISCREG_ICV_ASGI1R_EL1, gem5::ArmISA::MISCREG_ICV_SGI0R_EL1,
  gem5::ArmISA::MISCREG_ICV_IAR1_EL1, gem5::ArmISA::MISCREG_ICV_EOIR1_EL1, gem5::ArmISA::MISCREG_ICV_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICV_BPR1_EL1,
  gem5::ArmISA::MISCREG_ICV_BPR1_EL1_NS, gem5::ArmISA::MISCREG_ICV_BPR1_EL1_S, gem5::ArmISA::MISCREG_ICV_CTLR_EL1, gem5::ArmISA::MISCREG_ICV_CTLR_EL1_NS,
  gem5::ArmISA::MISCREG_ICV_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICV_SRE_EL1, gem5::ArmISA::MISCREG_ICV_SRE_EL1_NS, gem5::ArmISA::MISCREG_ICV_SRE_EL1_S,
  gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1_S,
  gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_AP0R1, gem5::ArmISA::MISCREG_ICC_AP0R2, gem5::ArmISA::MISCREG_ICC_AP0R3,
  gem5::ArmISA::MISCREG_ICC_AP1R0, gem5::ArmISA::MISCREG_ICC_AP1R0_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_S, gem5::ArmISA::MISCREG_ICC_AP1R1,
  gem5::ArmISA::MISCREG_ICC_AP1R1_NS, gem5::ArmISA::MISCREG_ICC_AP1R1_S, gem5::ArmISA::MISCREG_ICC_AP1R2, gem5::ArmISA::MISCREG_ICC_AP1R2_NS,
  gem5::ArmISA::MISCREG_ICC_AP1R2_S, gem5::ArmISA::MISCREG_ICC_AP1R3, gem5::ArmISA::MISCREG_ICC_AP1R3_NS, gem5::ArmISA::MISCREG_ICC_AP1R3_S,
  gem5::ArmISA::MISCREG_ICC_ASGI1R, gem5::ArmISA::MISCREG_ICC_BPR0, gem5::ArmISA::MISCREG_ICC_BPR1, gem5::ArmISA::MISCREG_ICC_BPR1_NS,
  gem5::ArmISA::MISCREG_ICC_BPR1_S, gem5::ArmISA::MISCREG_ICC_CTLR, gem5::ArmISA::MISCREG_ICC_CTLR_NS, gem5::ArmISA::MISCREG_ICC_CTLR_S,
  gem5::ArmISA::MISCREG_ICC_DIR, gem5::ArmISA::MISCREG_ICC_EOIR0, gem5::ArmISA::MISCREG_ICC_EOIR1, gem5::ArmISA::MISCREG_ICC_HPPIR0,
  gem5::ArmISA::MISCREG_ICC_HPPIR1, gem5::ArmISA::MISCREG_ICC_HSRE, gem5::ArmISA::MISCREG_ICC_IAR0, gem5::ArmISA::MISCREG_ICC_IAR1,
  gem5::ArmISA::MISCREG_ICC_IGRPEN0, gem5::ArmISA::MISCREG_ICC_IGRPEN1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_S,
  gem5::ArmISA::MISCREG_ICC_MCTLR, gem5::ArmISA::MISCREG_ICC_MGRPEN1, gem5::ArmISA::MISCREG_ICC_MSRE, gem5::ArmISA::MISCREG_ICC_PMR,
  gem5::ArmISA::MISCREG_ICC_RPR, gem5::ArmISA::MISCREG_ICC_SGI0R, gem5::ArmISA::MISCREG_ICC_SGI1R, gem5::ArmISA::MISCREG_ICC_SRE,
  gem5::ArmISA::MISCREG_ICC_SRE_NS, gem5::ArmISA::MISCREG_ICC_SRE_S, gem5::ArmISA::MISCREG_ICH_AP0R0, gem5::ArmISA::MISCREG_ICH_AP0R1,
  gem5::ArmISA::MISCREG_ICH_AP0R2, gem5::ArmISA::MISCREG_ICH_AP0R3, gem5::ArmISA::MISCREG_ICH_AP1R0, gem5::ArmISA::MISCREG_ICH_AP1R1,
  gem5::ArmISA::MISCREG_ICH_AP1R2, gem5::ArmISA::MISCREG_ICH_AP1R3, gem5::ArmISA::MISCREG_ICH_HCR, gem5::ArmISA::MISCREG_ICH_VTR,
  gem5::ArmISA::MISCREG_ICH_MISR, gem5::ArmISA::MISCREG_ICH_EISR, gem5::ArmISA::MISCREG_ICH_ELRSR, gem5::ArmISA::MISCREG_ICH_VMCR,
  gem5::ArmISA::MISCREG_ICH_LR0, gem5::ArmISA::MISCREG_ICH_LR1, gem5::ArmISA::MISCREG_ICH_LR2, gem5::ArmISA::MISCREG_ICH_LR3,
  gem5::ArmISA::MISCREG_ICH_LR4, gem5::ArmISA::MISCREG_ICH_LR5, gem5::ArmISA::MISCREG_ICH_LR6, gem5::ArmISA::MISCREG_ICH_LR7,
  gem5::ArmISA::MISCREG_ICH_LR8, gem5::ArmISA::MISCREG_ICH_LR9, gem5::ArmISA::MISCREG_ICH_LR10, gem5::ArmISA::MISCREG_ICH_LR11,
  gem5::ArmISA::MISCREG_ICH_LR12, gem5::ArmISA::MISCREG_ICH_LR13, gem5::ArmISA::MISCREG_ICH_LR14, gem5::ArmISA::MISCREG_ICH_LR15,
  gem5::ArmISA::MISCREG_ICH_LRC0, gem5::ArmISA::MISCREG_ICH_LRC1, gem5::ArmISA::MISCREG_ICH_LRC2, gem5::ArmISA::MISCREG_ICH_LRC3,
  gem5::ArmISA::MISCREG_ICH_LRC4, gem5::ArmISA::MISCREG_ICH_LRC5, gem5::ArmISA::MISCREG_ICH_LRC6, gem5::ArmISA::MISCREG_ICH_LRC7,
  gem5::ArmISA::MISCREG_ICH_LRC8, gem5::ArmISA::MISCREG_ICH_LRC9, gem5::ArmISA::MISCREG_ICH_LRC10, gem5::ArmISA::MISCREG_ICH_LRC11,
  gem5::ArmISA::MISCREG_ICH_LRC12, gem5::ArmISA::MISCREG_ICH_LRC13, gem5::ArmISA::MISCREG_ICH_LRC14, gem5::ArmISA::MISCREG_ICH_LRC15,
  gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1, gem5::ArmISA::MISCREG_ZCR_EL3, gem5::ArmISA::MISCREG_ZCR_EL2, gem5::ArmISA::MISCREG_ZCR_EL12,
  gem5::ArmISA::MISCREG_ZCR_EL1, gem5::ArmISA::NUM_PHYS_MISCREGS, gem5::ArmISA::MISCREG_NOP, gem5::ArmISA::MISCREG_RAZ,
  gem5::ArmISA::MISCREG_UNKNOWN, gem5::ArmISA::MISCREG_IMPDEF_UNIMPL, gem5::ArmISA::MISCREG_ERRIDR_EL1, gem5::ArmISA::MISCREG_ERRSELR_EL1,
  gem5::ArmISA::MISCREG_ERXFR_EL1, gem5::ArmISA::MISCREG_ERXCTLR_EL1, gem5::ArmISA::MISCREG_ERXSTATUS_EL1, gem5::ArmISA::MISCREG_ERXADDR_EL1,
  gem5::ArmISA::MISCREG_ERXMISC0_EL1, gem5::ArmISA::MISCREG_ERXMISC1_EL1, gem5::ArmISA::MISCREG_DISR_EL1, gem5::ArmISA::MISCREG_VSESR_EL2,
  gem5::ArmISA::MISCREG_VDISR_EL2, gem5::ArmISA::MISCREG_PAN, gem5::ArmISA::MISCREG_UAO, gem5::ArmISA::NUM_MISCREGS
}
 
enum  gem5::ArmISA::MiscRegInfo {
  gem5::ArmISA::MISCREG_IMPLEMENTED, gem5::ArmISA::MISCREG_UNVERIFIABLE, gem5::ArmISA::MISCREG_WARN_NOT_FAIL, gem5::ArmISA::MISCREG_MUTEX,
  gem5::ArmISA::MISCREG_BANKED, gem5::ArmISA::MISCREG_BANKED64, gem5::ArmISA::MISCREG_BANKED_CHILD, gem5::ArmISA::MISCREG_USR_NS_RD,
  gem5::ArmISA::MISCREG_USR_NS_WR, gem5::ArmISA::MISCREG_USR_S_RD, gem5::ArmISA::MISCREG_USR_S_WR, gem5::ArmISA::MISCREG_PRI_NS_RD,
  gem5::ArmISA::MISCREG_PRI_NS_WR, gem5::ArmISA::MISCREG_PRI_S_RD, gem5::ArmISA::MISCREG_PRI_S_WR, gem5::ArmISA::MISCREG_HYP_NS_RD,
  gem5::ArmISA::MISCREG_HYP_NS_WR, gem5::ArmISA::MISCREG_HYP_S_RD, gem5::ArmISA::MISCREG_HYP_S_WR, gem5::ArmISA::MISCREG_HYP_E2H_NS_RD,
  gem5::ArmISA::MISCREG_HYP_E2H_NS_WR, gem5::ArmISA::MISCREG_HYP_E2H_S_RD, gem5::ArmISA::MISCREG_HYP_E2H_S_WR, gem5::ArmISA::MISCREG_MON_NS0_RD,
  gem5::ArmISA::MISCREG_MON_NS0_WR, gem5::ArmISA::MISCREG_MON_NS1_RD, gem5::ArmISA::MISCREG_MON_NS1_WR, gem5::ArmISA::MISCREG_MON_E2H_RD,
  gem5::ArmISA::MISCREG_MON_E2H_WR, gem5::ArmISA::NUM_MISCREG_INFOS
}
 

Functions

MiscRegIndex gem5::ArmISA::decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex gem5::ArmISA::decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
 
MiscRegNum64 gem5::ArmISA::encodeAArch64SysReg (MiscRegIndex misc_reg)
 
bool gem5::ArmISA::aarch64SysRegReadOnly (MiscRegIndex miscReg)
 
MiscRegIndex gem5::ArmISA::decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex gem5::ArmISA::decodeCP15Reg64 (unsigned crm, unsigned opc1)
 
std::tuple< bool, bool > gem5::ArmISA::canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to read coprocessor registers. More...
 
std::tuple< bool, bool > gem5::ArmISA::canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to write coprocessor registers. More...
 
bool gem5::ArmISA::AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
 
bool gem5::ArmISA::canReadAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
bool gem5::ArmISA::canWriteAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
int gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
 
int gem5::ArmISA::snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
 
int gem5::ArmISA::snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
 
void gem5::ArmISA::preUnflattenMiscReg ()
 
int gem5::ArmISA::unflattenMiscReg (int reg)
 

Variables

const char *const gem5::ArmISA::miscRegName []
 
static const uint32_t gem5::ArmISA::CondCodesMask = 0xF00F0000
 
static const uint32_t gem5::ArmISA::CpsrMaskQ = 0x08000000
 
static const uint32_t gem5::ArmISA::ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
 
static const uint32_t gem5::ArmISA::CpsrMask = ApsrMask | 0x00F003DF
 
static const uint32_t gem5::ArmISA::FpCondCodesMask = 0xF0000000
 
static const uint32_t gem5::ArmISA::FpscrQcMask = 0x08000000
 
static const uint32_t gem5::ArmISA::FpscrAhpMask = 0x04000000
 
static const uint32_t gem5::ArmISA::FpscrExcMask = 0x0000009F
 

Generated on Sat Jun 18 2022 08:12:44 for gem5 by doxygen 1.8.17