This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. More...

#include <misc64.hh>

Inheritance diagram for gem5::MiscRegOp64:

Public Member Functions
virtual uint32_t	iss () const

bool	miscRead () const

Fault	generateTrap (ArmISA::ExceptionLevel el) const

Fault	generateTrap (ArmISA::ExceptionLevel el, ArmISA::ExceptionClass ec, uint32_t iss) const

Public Member Functions inherited from gem5::ArmISA::ArmStaticInst
virtual void	annotateFault (ArmFault *fault)

uint8_t	getIntWidth () const

ssize_t	instSize () const
	Returns the byte size of current instruction.

MachInst	encoding () const
	Returns the real encoding of the instruction: the machInst field is in fact always 64 bit wide and contains some instruction metadata, which means it differs from the real opcode.

size_t	asBytes (void *buf, size_t max_size) override
	Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

Fault	undefined (bool disabled=false) const

Public Member Functions inherited from gem5::StaticInst
uint8_t	numSrcRegs () const
	Number of source registers.

uint8_t	numDestRegs () const
	Number of destination registers.

uint8_t	numDestRegs (RegClassType type) const
	Number of destination registers of a particular type.

bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isVector () const

bool	isMatrix () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isFullMemBarrier () const

bool	isReadBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isUnverifiable () const

bool	isPseudo () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isHtmStart () const

bool	isHtmStop () const

bool	isHtmCancel () const

bool	isInvalid () const

bool	isHtmCmd () const

void	setFirstMicroop ()

void	setLastMicroop ()

void	setDelayedCommit ()

void	setFlag (Flags f)

OpClass	opClass () const
	Operation class. Used to select appropriate function unit in issue.

const RegId &	destRegIdx (int i) const
	Return logical index (architectural reg num) of i'th destination reg.

void	setDestRegIdx (int i, const RegId &val)

const RegId &	srcRegIdx (int i) const
	Return logical index (architectural reg num) of i'th source reg.

void	setSrcRegIdx (int i, const RegId &val)

virtual	~StaticInst ()

virtual Fault	execute (ExecContext xc, trace::InstRecord traceData) const =0

virtual Fault	initiateAcc (ExecContext xc, trace::InstRecord traceData) const

virtual Fault	completeAcc (Packet pkt, ExecContext xc, trace::InstRecord *trace_data) const

size_t	size () const

virtual void	size (size_t newSize)

virtual StaticInstPtr	fetchMicroop (MicroPC upc) const
	Return the microop that goes with a particular micropc.

virtual std::unique_ptr< PCStateBase >	branchTarget (const PCStateBase &pc) const
	Return the target address for a PC-relative branch.

virtual std::unique_ptr< PCStateBase >	branchTarget (ThreadContext *tc) const
	Return the target address for an indirect branch (jump).

virtual const std::string &	disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const
	Return string representation of disassembled instruction.

void	printFlags (std::ostream &outs, const std::string &separator) const
	Print a separator separated list of this instruction's set flag names on the given stream.

std::string	getName ()
	Return name of machine instruction.

Public Member Functions inherited from gem5::RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one.

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects.

void	incref () const
	Increment the reference count.

void	decref () const
	Decrement the reference count and destroy the object if all references are gone.

Protected Member Functions
	MiscRegOp64 (const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, bool misc_read)

uint32_t	_iss (const ArmISA::MiscRegNum64 &misc_reg, RegIndex int_index) const

Protected Member Functions inherited from gem5::ArmISA::ArmStaticInst
int32_t	shift_rm_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

int32_t	shift_rm_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

bool	shift_carry_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

bool	shift_carry_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const

int64_t	shiftReg64 (uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const

int64_t	extendReg64 (uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const

	ArmStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)

void	printIntReg (std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
	Print a register name for disassembly given the unique dependence tag number (FP or int).

void	printFloatReg (std::ostream &os, RegIndex reg_idx) const

void	printVecReg (std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const

void	printVecPredReg (std::ostream &os, RegIndex reg_idx) const

void	printCCReg (std::ostream &os, RegIndex reg_idx) const

void	printMiscReg (std::ostream &os, RegIndex reg_idx) const

void	printMnemonic (std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const

void	printTarget (std::ostream &os, Addr target, const loader::SymbolTable *symtab) const

void	printCondition (std::ostream &os, unsigned code, bool noImplicit=false) const

void	printMemSymbol (std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const

void	printShiftOperand (std::ostream &os, RegIndex rm, bool immShift, uint32_t shiftAmt, RegIndex rs, ArmShiftType type) const

void	printExtendOperand (bool firstOperand, std::ostream &os, RegIndex rm, ArmExtendType type, int64_t shiftAmt) const

void	printPFflags (std::ostream &os, int flag) const

void	printDataInst (std::ostream &os, bool withImm) const

void	printDataInst (std::ostream &os, bool withImm, bool immShift, bool s, RegIndex rd, RegIndex rn, RegIndex rm, RegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const

void	advancePC (PCStateBase &pcState) const override

void	advancePC (ThreadContext *tc) const override

uint64_t	getEMI () const override

std::unique_ptr< PCStateBase >	buildRetPC (const PCStateBase &cur_pc, const PCStateBase &call_pc) const override

std::string	generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override
	Internal function to generate disassembly string.

Fault	disabledFault () const

bool	isWFxTrapping (ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const

Fault	softwareBreakpoint32 (ExecContext *xc, uint16_t imm) const
	Trigger a Software Breakpoint.

Fault	advSIMDFPAccessTrap64 (ExceptionLevel el) const
	Trap an access to Advanced SIMD or FP registers due to access control bits.

Fault	checkFPAdvSIMDTrap64 (ThreadContext *tc, CPSR cpsr) const
	Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.

Fault	checkFPAdvSIMDEnabled64 (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

Fault	checkAdvSIMDOrFPEnabled32 (ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
	Check if a VFP/SIMD access from aarch32 should be allowed.

Fault	checkForWFxTrap32 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
	Check if WFE/WFI instruction execution in aarch32 should be trapped.

Fault	checkForWFxTrap64 (ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
	Check if WFE/WFI instruction execution in aarch64 should be trapped.

Fault	trapWFx (ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
	WFE/WFI trapping helper function.

Fault	checkSETENDEnabled (ThreadContext *tc, CPSR cpsr) const
	Check if SETEND instruction execution in aarch32 should be trapped.

Fault	undefinedFault32 (ThreadContext *tc, ExceptionLevel el) const
	UNDEFINED behaviour in AArch32.

Fault	undefinedFault64 (ThreadContext *tc, ExceptionLevel el) const
	UNDEFINED behaviour in AArch64.

Fault	sveAccessTrap (ExceptionLevel el) const
	Trap an access to SVE registers due to access control bits.

Fault	checkSveEnabled (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

Fault	smeAccessTrap (ExceptionLevel el, uint32_t iss=0) const
	Trap an access to SME registers due to access control bits.

Fault	checkSmeEnabled (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check if SME is enabled by checking the SME and FP bits of CPACR_EL1, CPTR_EL2, and CPTR_EL3.

Fault	checkSmeAccess (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an SME access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

Fault	checkSveSmeEnabled (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
	Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3, but choosing the correct set of traps to check based on Streaming Mode.

CPSR	getPSTATEFromPSR (ThreadContext *tc, CPSR cpsr, CPSR spsr) const
	Get the new PSTATE from a SPSR register in preparation for an exception return.

bool	generalExceptionsToAArch64 (ThreadContext *tc, ExceptionLevel pstateEL) const
	Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch64, because either EL1 is using AArch64 or TGE is in force and EL2 is using AArch64.

Protected Member Functions inherited from gem5::StaticInst
void	setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest)
	Set the pointers which point to the arrays of source and destination register indices.

	StaticInst (const char *_mnemonic, OpClass op_class)
	Constructor.

template<typename T >
size_t	simpleAsBytes (void *buf, size_t max_size, const T &t)

Protected Attributes
bool	_miscRead

Protected Attributes inherited from gem5::ArmISA::ArmStaticInst
bool	aarch64

uint8_t	intWidth

ExtMachInst	machInst

Protected Attributes inherited from gem5::StaticInst
std::bitset< Num_Flags >	flags
	Flag values for this instruction.

OpClass	_opClass
	See opClass().

uint8_t	_numSrcRegs = 0
	See numSrcRegs().

uint8_t	_numDestRegs = 0
	See numDestRegs().

std::array< uint8_t, MiscRegClass+1 >	_numTypedDestRegs = {}

size_t	_size = 0
	Instruction size in bytes.

const char *	mnemonic
	Base mnemonic (e.g., "add").

std::unique_ptr< std::string >	cachedDisassembly
	String representation of disassembly (lazily evaluated via disassemble()).

Additional Inherited Members
Public Types inherited from gem5::StaticInst
using	RegIdArrayPtr = RegId (StaticInst:: *)[]

Static Public Member Functions inherited from gem5::ArmISA::ArmStaticInst
static unsigned	getCurSveVecLenInBits (ThreadContext *tc)

static unsigned	getCurSveVecLenInQWords (ThreadContext *tc)

template<typename T >
static unsigned	getCurSveVecLen (ThreadContext *tc)

static unsigned	getCurSmeVecLenInBits (ThreadContext *tc)

static unsigned	getCurSmeVecLenInQWords (ThreadContext *tc)

template<typename T >
static unsigned	getCurSmeVecLen (ThreadContext *tc)

Static Public Attributes inherited from gem5::StaticInst
static StaticInstPtr	nullStaticInstPtr
	Pointer to a statically allocated "null" instruction object.

Static Protected Member Functions inherited from gem5::ArmISA::ArmStaticInst
template<int width>
static bool	saturateOp (int32_t &res, int64_t op1, int64_t op2, bool sub=false)

static bool	satInt (int32_t &res, int64_t op, int width)

template<int width>
static bool	uSaturateOp (uint32_t &res, int64_t op1, int64_t op2, bool sub=false)

static bool	uSatInt (int32_t &res, int64_t op, int width)

static void	activateBreakpoint (ThreadContext *tc)

static uint32_t	cpsrWriteByInstr (CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)

static uint32_t	spsrWriteByInstr (uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)

static Addr	readPC (ExecContext *xc)

static void	setNextPC (ExecContext *xc, Addr val)

template<class T >
static T	cSwap (T val, bool big)

template<class T , class E >
static T	cSwap (T val, bool big)

static void	setIWNextPC (ExecContext *xc, Addr val)

static void	setAIWNextPC (ExecContext *xc, Addr val)

Detailed Description

This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS.

The common denominator or those instruction is the chance that the system register access is trapped to an upper Exception level. MiscRegOp64 is providing that feature. Other "pseudo" instructions, like access to implementation defined registers can inherit from this class to make use of the trapping functionalities even if there is no data movement between GPRs and system register.

Definition at line 157 of file misc64.hh.

Constructor & Destructor Documentation

◆ MiscRegOp64()

gem5::MiscRegOp64::MiscRegOp64	(	const char *	mnem,
		ArmISA::ExtMachInst	_machInst,
		OpClass	__opClass,
		bool	misc_read )

inlineprotected

Definition at line 162 of file misc64.hh.

Member Function Documentation

◆ _iss()

uint32_t gem5::MiscRegOp64::_iss	(	const ArmISA::MiscRegNum64 &	misc_reg,
		RegIndex	int_index ) const

protected

Definition at line 114 of file misc64.cc.

References _miscRead, gem5::ArmISA::MiscRegNum64::crm, gem5::ArmISA::MiscRegNum64::crn, gem5::ArmISA::MiscRegNum64::op0, gem5::ArmISA::MiscRegNum64::op1, and gem5::ArmISA::MiscRegNum64::op2.

Referenced by gem5::ArmISA::SysDC64::iss(), gem5::MiscRegImplDefined64::iss(), gem5::MiscRegRegImmOp64::iss(), and gem5::RegMiscRegImmOp64::iss().

◆ generateTrap() [1/2]

Fault gem5::MiscRegOp64::generateTrap ( ArmISA::ExceptionLevel el ) const

Definition at line 126 of file misc64.cc.

References gem5::ArmISA::el, generateTrap(), and iss().

Referenced by generateTrap().

◆ generateTrap() [2/2]

Fault gem5::MiscRegOp64::generateTrap	(	ArmISA::ExceptionLevel	el,
		ArmISA::ExceptionClass	ec,
		uint32_t	iss ) const

Definition at line 132 of file misc64.cc.

References gem5::ArmISA::ec, gem5::ArmISA::el, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::ArmStaticInst::getEMI(), iss(), and panic.

◆ iss()

virtual uint32_t gem5::MiscRegOp64::iss ( ) const

inlinevirtual

Reimplemented in gem5::ArmISA::SysDC64, gem5::MiscRegImplDefined64, gem5::MiscRegRegImmOp64, and gem5::RegMiscRegImmOp64.

Definition at line 172 of file misc64.hh.

Referenced by generateTrap(), and generateTrap().

◆ miscRead()

bool gem5::MiscRegOp64::miscRead ( ) const

inline

Definition at line 174 of file misc64.hh.

References _miscRead.

Referenced by gem5::ArmISA::MiscRegLUTEntry::checkFault().

Member Data Documentation

◆ _miscRead

bool gem5::MiscRegOp64::_miscRead

protected

Definition at line 160 of file misc64.hh.

Referenced by _iss(), and miscRead().

The documentation for this class was generated from the following files:

arch/arm/insts/misc64.hh
arch/arm/insts/misc64.cc

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members