#include <string>
#include <unordered_map>
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/riscv/types.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "debug/MiscRegs.hh"
#include "enums/RiscvType.hh"

Classes
struct	gem5::RiscvISA::CSRMetadata

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

namespace	gem5::RiscvISA

Enumerations
enum	gem5::RiscvISA::MiscRegIndex { gem5::RiscvISA::MISCREG_PRV = 0 , gem5::RiscvISA::MISCREG_ISA , gem5::RiscvISA::MISCREG_VENDORID , gem5::RiscvISA::MISCREG_ARCHID , gem5::RiscvISA::MISCREG_IMPID , gem5::RiscvISA::MISCREG_HARTID , gem5::RiscvISA::MISCREG_STATUS , gem5::RiscvISA::MISCREG_IP , gem5::RiscvISA::MISCREG_IE , gem5::RiscvISA::MISCREG_CYCLE , gem5::RiscvISA::MISCREG_TIME , gem5::RiscvISA::MISCREG_INSTRET , gem5::RiscvISA::MISCREG_HPMCOUNTER03 , gem5::RiscvISA::MISCREG_HPMCOUNTER04 , gem5::RiscvISA::MISCREG_HPMCOUNTER05 , gem5::RiscvISA::MISCREG_HPMCOUNTER06 , gem5::RiscvISA::MISCREG_HPMCOUNTER07 , gem5::RiscvISA::MISCREG_HPMCOUNTER08 , gem5::RiscvISA::MISCREG_HPMCOUNTER09 , gem5::RiscvISA::MISCREG_HPMCOUNTER10 , gem5::RiscvISA::MISCREG_HPMCOUNTER11 , gem5::RiscvISA::MISCREG_HPMCOUNTER12 , gem5::RiscvISA::MISCREG_HPMCOUNTER13 , gem5::RiscvISA::MISCREG_HPMCOUNTER14 , gem5::RiscvISA::MISCREG_HPMCOUNTER15 , gem5::RiscvISA::MISCREG_HPMCOUNTER16 , gem5::RiscvISA::MISCREG_HPMCOUNTER17 , gem5::RiscvISA::MISCREG_HPMCOUNTER18 , gem5::RiscvISA::MISCREG_HPMCOUNTER19 , gem5::RiscvISA::MISCREG_HPMCOUNTER20 , gem5::RiscvISA::MISCREG_HPMCOUNTER21 , gem5::RiscvISA::MISCREG_HPMCOUNTER22 , gem5::RiscvISA::MISCREG_HPMCOUNTER23 , gem5::RiscvISA::MISCREG_HPMCOUNTER24 , gem5::RiscvISA::MISCREG_HPMCOUNTER25 , gem5::RiscvISA::MISCREG_HPMCOUNTER26 , gem5::RiscvISA::MISCREG_HPMCOUNTER27 , gem5::RiscvISA::MISCREG_HPMCOUNTER28 , gem5::RiscvISA::MISCREG_HPMCOUNTER29 , gem5::RiscvISA::MISCREG_HPMCOUNTER30 , gem5::RiscvISA::MISCREG_HPMCOUNTER31 , gem5::RiscvISA::MISCREG_HPMEVENT03 , gem5::RiscvISA::MISCREG_HPMEVENT04 , gem5::RiscvISA::MISCREG_HPMEVENT05 , gem5::RiscvISA::MISCREG_HPMEVENT06 , gem5::RiscvISA::MISCREG_HPMEVENT07 , gem5::RiscvISA::MISCREG_HPMEVENT08 , gem5::RiscvISA::MISCREG_HPMEVENT09 , gem5::RiscvISA::MISCREG_HPMEVENT10 , gem5::RiscvISA::MISCREG_HPMEVENT11 , gem5::RiscvISA::MISCREG_HPMEVENT12 , gem5::RiscvISA::MISCREG_HPMEVENT13 , gem5::RiscvISA::MISCREG_HPMEVENT14 , gem5::RiscvISA::MISCREG_HPMEVENT15 , gem5::RiscvISA::MISCREG_HPMEVENT16 , gem5::RiscvISA::MISCREG_HPMEVENT17 , gem5::RiscvISA::MISCREG_HPMEVENT18 , gem5::RiscvISA::MISCREG_HPMEVENT19 , gem5::RiscvISA::MISCREG_HPMEVENT20 , gem5::RiscvISA::MISCREG_HPMEVENT21 , gem5::RiscvISA::MISCREG_HPMEVENT22 , gem5::RiscvISA::MISCREG_HPMEVENT23 , gem5::RiscvISA::MISCREG_HPMEVENT24 , gem5::RiscvISA::MISCREG_HPMEVENT25 , gem5::RiscvISA::MISCREG_HPMEVENT26 , gem5::RiscvISA::MISCREG_HPMEVENT27 , gem5::RiscvISA::MISCREG_HPMEVENT28 , gem5::RiscvISA::MISCREG_HPMEVENT29 , gem5::RiscvISA::MISCREG_HPMEVENT30 , gem5::RiscvISA::MISCREG_HPMEVENT31 , gem5::RiscvISA::MISCREG_TSELECT , gem5::RiscvISA::MISCREG_TDATA1 , gem5::RiscvISA::MISCREG_TDATA2 , gem5::RiscvISA::MISCREG_TDATA3 , gem5::RiscvISA::MISCREG_DCSR , gem5::RiscvISA::MISCREG_DPC , gem5::RiscvISA::MISCREG_DSCRATCH , gem5::RiscvISA::MISCREG_MEDELEG , gem5::RiscvISA::MISCREG_MIDELEG , gem5::RiscvISA::MISCREG_MTVEC , gem5::RiscvISA::MISCREG_MCOUNTEREN , gem5::RiscvISA::MISCREG_MSCRATCH , gem5::RiscvISA::MISCREG_MEPC , gem5::RiscvISA::MISCREG_MCAUSE , gem5::RiscvISA::MISCREG_MTVAL , gem5::RiscvISA::MISCREG_PMPCFG0 , gem5::RiscvISA::MISCREG_PMPCFG1 , gem5::RiscvISA::MISCREG_PMPCFG2 , gem5::RiscvISA::MISCREG_PMPCFG3 , gem5::RiscvISA::MISCREG_PMPADDR00 , gem5::RiscvISA::MISCREG_PMPADDR01 , gem5::RiscvISA::MISCREG_PMPADDR02 , gem5::RiscvISA::MISCREG_PMPADDR03 , gem5::RiscvISA::MISCREG_PMPADDR04 , gem5::RiscvISA::MISCREG_PMPADDR05 , gem5::RiscvISA::MISCREG_PMPADDR06 , gem5::RiscvISA::MISCREG_PMPADDR07 , gem5::RiscvISA::MISCREG_PMPADDR08 , gem5::RiscvISA::MISCREG_PMPADDR09 , gem5::RiscvISA::MISCREG_PMPADDR10 , gem5::RiscvISA::MISCREG_PMPADDR11 , gem5::RiscvISA::MISCREG_PMPADDR12 , gem5::RiscvISA::MISCREG_PMPADDR13 , gem5::RiscvISA::MISCREG_PMPADDR14 , gem5::RiscvISA::MISCREG_PMPADDR15 , gem5::RiscvISA::MISCREG_SEDELEG , gem5::RiscvISA::MISCREG_SIDELEG , gem5::RiscvISA::MISCREG_STVEC , gem5::RiscvISA::MISCREG_SCOUNTEREN , gem5::RiscvISA::MISCREG_SSCRATCH , gem5::RiscvISA::MISCREG_SEPC , gem5::RiscvISA::MISCREG_SCAUSE , gem5::RiscvISA::MISCREG_STVAL , gem5::RiscvISA::MISCREG_SATP , gem5::RiscvISA::MISCREG_UTVEC , gem5::RiscvISA::MISCREG_USCRATCH , gem5::RiscvISA::MISCREG_UEPC , gem5::RiscvISA::MISCREG_UCAUSE , gem5::RiscvISA::MISCREG_UTVAL , gem5::RiscvISA::MISCREG_FFLAGS , gem5::RiscvISA::MISCREG_FRM , gem5::RiscvISA::MISCREG_VSTART , gem5::RiscvISA::MISCREG_VXSAT , gem5::RiscvISA::MISCREG_VXRM , gem5::RiscvISA::MISCREG_VCSR , gem5::RiscvISA::MISCREG_VL , gem5::RiscvISA::MISCREG_VTYPE , gem5::RiscvISA::MISCREG_VLENB , gem5::RiscvISA::MISCREG_NMIVEC , gem5::RiscvISA::MISCREG_NMIE , gem5::RiscvISA::MISCREG_NMIP , gem5::RiscvISA::MISCREG_MSTATUSH , gem5::RiscvISA::MISCREG_CYCLEH , gem5::RiscvISA::MISCREG_TIMEH , gem5::RiscvISA::MISCREG_INSTRETH , gem5::RiscvISA::MISCREG_HPMCOUNTER03H , gem5::RiscvISA::MISCREG_HPMCOUNTER04H , gem5::RiscvISA::MISCREG_HPMCOUNTER05H , gem5::RiscvISA::MISCREG_HPMCOUNTER06H , gem5::RiscvISA::MISCREG_HPMCOUNTER07H , gem5::RiscvISA::MISCREG_HPMCOUNTER08H , gem5::RiscvISA::MISCREG_HPMCOUNTER09H , gem5::RiscvISA::MISCREG_HPMCOUNTER10H , gem5::RiscvISA::MISCREG_HPMCOUNTER11H , gem5::RiscvISA::MISCREG_HPMCOUNTER12H , gem5::RiscvISA::MISCREG_HPMCOUNTER13H , gem5::RiscvISA::MISCREG_HPMCOUNTER14H , gem5::RiscvISA::MISCREG_HPMCOUNTER15H , gem5::RiscvISA::MISCREG_HPMCOUNTER16H , gem5::RiscvISA::MISCREG_HPMCOUNTER17H , gem5::RiscvISA::MISCREG_HPMCOUNTER18H , gem5::RiscvISA::MISCREG_HPMCOUNTER19H , gem5::RiscvISA::MISCREG_HPMCOUNTER20H , gem5::RiscvISA::MISCREG_HPMCOUNTER21H , gem5::RiscvISA::MISCREG_HPMCOUNTER22H , gem5::RiscvISA::MISCREG_HPMCOUNTER23H , gem5::RiscvISA::MISCREG_HPMCOUNTER24H , gem5::RiscvISA::MISCREG_HPMCOUNTER25H , gem5::RiscvISA::MISCREG_HPMCOUNTER26H , gem5::RiscvISA::MISCREG_HPMCOUNTER27H , gem5::RiscvISA::MISCREG_HPMCOUNTER28H , gem5::RiscvISA::MISCREG_HPMCOUNTER29H , gem5::RiscvISA::MISCREG_HPMCOUNTER30H , gem5::RiscvISA::MISCREG_HPMCOUNTER31H , gem5::RiscvISA::NUM_PHYS_MISCREGS , gem5::RiscvISA::MISCREG_MSTATUS = MISCREG_STATUS , gem5::RiscvISA::MISCREG_MIP = MISCREG_IP , gem5::RiscvISA::MISCREG_MIE = MISCREG_IE , gem5::RiscvISA::MISCREG_FFLAGS_EXE = NUM_PHYS_MISCREGS , gem5::RiscvISA::MISCREG_FCSR , gem5::RiscvISA::MISCREG_USTATUS , gem5::RiscvISA::MISCREG_UIP , gem5::RiscvISA::MISCREG_UIE , gem5::RiscvISA::MISCREG_SSTATUS , gem5::RiscvISA::MISCREG_SIP , gem5::RiscvISA::MISCREG_SIE , gem5::RiscvISA::NUM_MISCREGS }

enum	gem5::RiscvISA::CSRIndex { gem5::RiscvISA::CSR_USTATUS = 0x000 , gem5::RiscvISA::CSR_UIE = 0x004 , gem5::RiscvISA::CSR_UTVEC = 0x005 , gem5::RiscvISA::CSR_USCRATCH = 0x040 , gem5::RiscvISA::CSR_UEPC = 0x041 , gem5::RiscvISA::CSR_UCAUSE = 0x042 , gem5::RiscvISA::CSR_UTVAL = 0x043 , gem5::RiscvISA::CSR_UIP = 0x044 , gem5::RiscvISA::CSR_FFLAGS = 0x001 , gem5::RiscvISA::CSR_FRM = 0x002 , gem5::RiscvISA::CSR_FCSR = 0x003 , gem5::RiscvISA::CSR_CYCLE = 0xC00 , gem5::RiscvISA::CSR_TIME = 0xC01 , gem5::RiscvISA::CSR_INSTRET = 0xC02 , gem5::RiscvISA::CSR_HPMCOUNTER03 = 0xC03 , gem5::RiscvISA::CSR_HPMCOUNTER04 = 0xC04 , gem5::RiscvISA::CSR_HPMCOUNTER05 = 0xC05 , gem5::RiscvISA::CSR_HPMCOUNTER06 = 0xC06 , gem5::RiscvISA::CSR_HPMCOUNTER07 = 0xC07 , gem5::RiscvISA::CSR_HPMCOUNTER08 = 0xC08 , gem5::RiscvISA::CSR_HPMCOUNTER09 = 0xC09 , gem5::RiscvISA::CSR_HPMCOUNTER10 = 0xC0A , gem5::RiscvISA::CSR_HPMCOUNTER11 = 0xC0B , gem5::RiscvISA::CSR_HPMCOUNTER12 = 0xC0C , gem5::RiscvISA::CSR_HPMCOUNTER13 = 0xC0D , gem5::RiscvISA::CSR_HPMCOUNTER14 = 0xC0E , gem5::RiscvISA::CSR_HPMCOUNTER15 = 0xC0F , gem5::RiscvISA::CSR_HPMCOUNTER16 = 0xC10 , gem5::RiscvISA::CSR_HPMCOUNTER17 = 0xC11 , gem5::RiscvISA::CSR_HPMCOUNTER18 = 0xC12 , gem5::RiscvISA::CSR_HPMCOUNTER19 = 0xC13 , gem5::RiscvISA::CSR_HPMCOUNTER20 = 0xC14 , gem5::RiscvISA::CSR_HPMCOUNTER21 = 0xC15 , gem5::RiscvISA::CSR_HPMCOUNTER22 = 0xC16 , gem5::RiscvISA::CSR_HPMCOUNTER23 = 0xC17 , gem5::RiscvISA::CSR_HPMCOUNTER24 = 0xC18 , gem5::RiscvISA::CSR_HPMCOUNTER25 = 0xC19 , gem5::RiscvISA::CSR_HPMCOUNTER26 = 0xC1A , gem5::RiscvISA::CSR_HPMCOUNTER27 = 0xC1B , gem5::RiscvISA::CSR_HPMCOUNTER28 = 0xC1C , gem5::RiscvISA::CSR_HPMCOUNTER29 = 0xC1D , gem5::RiscvISA::CSR_HPMCOUNTER30 = 0xC1E , gem5::RiscvISA::CSR_HPMCOUNTER31 = 0xC1F , gem5::RiscvISA::CSR_CYCLEH = 0xC80 , gem5::RiscvISA::CSR_TIMEH = 0xC81 , gem5::RiscvISA::CSR_INSTRETH = 0xC82 , gem5::RiscvISA::CSR_HPMCOUNTER03H = 0xC83 , gem5::RiscvISA::CSR_HPMCOUNTER04H = 0xC84 , gem5::RiscvISA::CSR_HPMCOUNTER05H = 0xC85 , gem5::RiscvISA::CSR_HPMCOUNTER06H = 0xC86 , gem5::RiscvISA::CSR_HPMCOUNTER07H = 0xC87 , gem5::RiscvISA::CSR_HPMCOUNTER08H = 0xC88 , gem5::RiscvISA::CSR_HPMCOUNTER09H = 0xC89 , gem5::RiscvISA::CSR_HPMCOUNTER10H = 0xC8A , gem5::RiscvISA::CSR_HPMCOUNTER11H = 0xC8B , gem5::RiscvISA::CSR_HPMCOUNTER12H = 0xC8C , gem5::RiscvISA::CSR_HPMCOUNTER13H = 0xC8D , gem5::RiscvISA::CSR_HPMCOUNTER14H = 0xC8E , gem5::RiscvISA::CSR_HPMCOUNTER15H = 0xC8F , gem5::RiscvISA::CSR_HPMCOUNTER16H = 0xC90 , gem5::RiscvISA::CSR_HPMCOUNTER17H = 0xC91 , gem5::RiscvISA::CSR_HPMCOUNTER18H = 0xC92 , gem5::RiscvISA::CSR_HPMCOUNTER19H = 0xC93 , gem5::RiscvISA::CSR_HPMCOUNTER20H = 0xC94 , gem5::RiscvISA::CSR_HPMCOUNTER21H = 0xC95 , gem5::RiscvISA::CSR_HPMCOUNTER22H = 0xC96 , gem5::RiscvISA::CSR_HPMCOUNTER23H = 0xC97 , gem5::RiscvISA::CSR_HPMCOUNTER24H = 0xC98 , gem5::RiscvISA::CSR_HPMCOUNTER25H = 0xC99 , gem5::RiscvISA::CSR_HPMCOUNTER26H = 0xC9A , gem5::RiscvISA::CSR_HPMCOUNTER27H = 0xC9B , gem5::RiscvISA::CSR_HPMCOUNTER28H = 0xC9C , gem5::RiscvISA::CSR_HPMCOUNTER29H = 0xC9D , gem5::RiscvISA::CSR_HPMCOUNTER30H = 0xC9E , gem5::RiscvISA::CSR_HPMCOUNTER31H = 0xC9F , gem5::RiscvISA::CSR_SSTATUS = 0x100 , gem5::RiscvISA::CSR_SEDELEG = 0x102 , gem5::RiscvISA::CSR_SIDELEG = 0x103 , gem5::RiscvISA::CSR_SIE = 0x104 , gem5::RiscvISA::CSR_STVEC = 0x105 , gem5::RiscvISA::CSR_SCOUNTEREN = 0x106 , gem5::RiscvISA::CSR_SSCRATCH = 0x140 , gem5::RiscvISA::CSR_SEPC = 0x141 , gem5::RiscvISA::CSR_SCAUSE = 0x142 , gem5::RiscvISA::CSR_STVAL = 0x143 , gem5::RiscvISA::CSR_SIP = 0x144 , gem5::RiscvISA::CSR_SATP = 0x180 , gem5::RiscvISA::CSR_MVENDORID = 0xF11 , gem5::RiscvISA::CSR_MARCHID = 0xF12 , gem5::RiscvISA::CSR_MIMPID = 0xF13 , gem5::RiscvISA::CSR_MHARTID = 0xF14 , gem5::RiscvISA::CSR_MSTATUS = 0x300 , gem5::RiscvISA::CSR_MISA = 0x301 , gem5::RiscvISA::CSR_MEDELEG = 0x302 , gem5::RiscvISA::CSR_MIDELEG = 0x303 , gem5::RiscvISA::CSR_MIE = 0x304 , gem5::RiscvISA::CSR_MTVEC = 0x305 , gem5::RiscvISA::CSR_MCOUNTEREN = 0x306 , gem5::RiscvISA::CSR_MSTATUSH = 0x310 , gem5::RiscvISA::CSR_MSCRATCH = 0x340 , gem5::RiscvISA::CSR_MEPC = 0x341 , gem5::RiscvISA::CSR_MCAUSE = 0x342 , gem5::RiscvISA::CSR_MTVAL = 0x343 , gem5::RiscvISA::CSR_MIP = 0x344 , gem5::RiscvISA::CSR_PMPCFG0 = 0x3A0 , gem5::RiscvISA::CSR_PMPCFG1 = 0x3A1 , gem5::RiscvISA::CSR_PMPCFG2 = 0x3A2 , gem5::RiscvISA::CSR_PMPCFG3 = 0x3A3 , gem5::RiscvISA::CSR_PMPADDR00 = 0x3B0 , gem5::RiscvISA::CSR_PMPADDR01 = 0x3B1 , gem5::RiscvISA::CSR_PMPADDR02 = 0x3B2 , gem5::RiscvISA::CSR_PMPADDR03 = 0x3B3 , gem5::RiscvISA::CSR_PMPADDR04 = 0x3B4 , gem5::RiscvISA::CSR_PMPADDR05 = 0x3B5 , gem5::RiscvISA::CSR_PMPADDR06 = 0x3B6 , gem5::RiscvISA::CSR_PMPADDR07 = 0x3B7 , gem5::RiscvISA::CSR_PMPADDR08 = 0x3B8 , gem5::RiscvISA::CSR_PMPADDR09 = 0x3B9 , gem5::RiscvISA::CSR_PMPADDR10 = 0x3BA , gem5::RiscvISA::CSR_PMPADDR11 = 0x3BB , gem5::RiscvISA::CSR_PMPADDR12 = 0x3BC , gem5::RiscvISA::CSR_PMPADDR13 = 0x3BD , gem5::RiscvISA::CSR_PMPADDR14 = 0x3BE , gem5::RiscvISA::CSR_PMPADDR15 = 0x3BF , gem5::RiscvISA::CSR_MCYCLE = 0xB00 , gem5::RiscvISA::CSR_MINSTRET = 0xB02 , gem5::RiscvISA::CSR_MHPMCOUNTER03 = 0xB03 , gem5::RiscvISA::CSR_MHPMCOUNTER04 = 0xB04 , gem5::RiscvISA::CSR_MHPMCOUNTER05 = 0xB05 , gem5::RiscvISA::CSR_MHPMCOUNTER06 = 0xB06 , gem5::RiscvISA::CSR_MHPMCOUNTER07 = 0xB07 , gem5::RiscvISA::CSR_MHPMCOUNTER08 = 0xB08 , gem5::RiscvISA::CSR_MHPMCOUNTER09 = 0xB09 , gem5::RiscvISA::CSR_MHPMCOUNTER10 = 0xB0A , gem5::RiscvISA::CSR_MHPMCOUNTER11 = 0xB0B , gem5::RiscvISA::CSR_MHPMCOUNTER12 = 0xB0C , gem5::RiscvISA::CSR_MHPMCOUNTER13 = 0xB0D , gem5::RiscvISA::CSR_MHPMCOUNTER14 = 0xB0E , gem5::RiscvISA::CSR_MHPMCOUNTER15 = 0xB0F , gem5::RiscvISA::CSR_MHPMCOUNTER16 = 0xB10 , gem5::RiscvISA::CSR_MHPMCOUNTER17 = 0xB11 , gem5::RiscvISA::CSR_MHPMCOUNTER18 = 0xB12 , gem5::RiscvISA::CSR_MHPMCOUNTER19 = 0xB13 , gem5::RiscvISA::CSR_MHPMCOUNTER20 = 0xB14 , gem5::RiscvISA::CSR_MHPMCOUNTER21 = 0xB15 , gem5::RiscvISA::CSR_MHPMCOUNTER22 = 0xB16 , gem5::RiscvISA::CSR_MHPMCOUNTER23 = 0xB17 , gem5::RiscvISA::CSR_MHPMCOUNTER24 = 0xB18 , gem5::RiscvISA::CSR_MHPMCOUNTER25 = 0xB19 , gem5::RiscvISA::CSR_MHPMCOUNTER26 = 0xB1A , gem5::RiscvISA::CSR_MHPMCOUNTER27 = 0xB1B , gem5::RiscvISA::CSR_MHPMCOUNTER28 = 0xB1C , gem5::RiscvISA::CSR_MHPMCOUNTER29 = 0xB1D , gem5::RiscvISA::CSR_MHPMCOUNTER30 = 0xB1E , gem5::RiscvISA::CSR_MHPMCOUNTER31 = 0xB1F , gem5::RiscvISA::CSR_MCYCLEH = 0xB80 , gem5::RiscvISA::CSR_MINSTRETH = 0xB82 , gem5::RiscvISA::CSR_MHPMCOUNTER03H = 0xB83 , gem5::RiscvISA::CSR_MHPMCOUNTER04H = 0xB84 , gem5::RiscvISA::CSR_MHPMCOUNTER05H = 0xB85 , gem5::RiscvISA::CSR_MHPMCOUNTER06H = 0xB86 , gem5::RiscvISA::CSR_MHPMCOUNTER07H = 0xB87 , gem5::RiscvISA::CSR_MHPMCOUNTER08H = 0xB88 , gem5::RiscvISA::CSR_MHPMCOUNTER09H = 0xB89 , gem5::RiscvISA::CSR_MHPMCOUNTER10H = 0xB8A , gem5::RiscvISA::CSR_MHPMCOUNTER11H = 0xB8B , gem5::RiscvISA::CSR_MHPMCOUNTER12H = 0xB8C , gem5::RiscvISA::CSR_MHPMCOUNTER13H = 0xB8D , gem5::RiscvISA::CSR_MHPMCOUNTER14H = 0xB8E , gem5::RiscvISA::CSR_MHPMCOUNTER15H = 0xB8F , gem5::RiscvISA::CSR_MHPMCOUNTER16H = 0xB90 , gem5::RiscvISA::CSR_MHPMCOUNTER17H = 0xB91 , gem5::RiscvISA::CSR_MHPMCOUNTER18H = 0xB92 , gem5::RiscvISA::CSR_MHPMCOUNTER19H = 0xB93 , gem5::RiscvISA::CSR_MHPMCOUNTER20H = 0xB94 , gem5::RiscvISA::CSR_MHPMCOUNTER21H = 0xB95 , gem5::RiscvISA::CSR_MHPMCOUNTER22H = 0xB96 , gem5::RiscvISA::CSR_MHPMCOUNTER23H = 0xB97 , gem5::RiscvISA::CSR_MHPMCOUNTER24H = 0xB98 , gem5::RiscvISA::CSR_MHPMCOUNTER25H = 0xB99 , gem5::RiscvISA::CSR_MHPMCOUNTER26H = 0xB9A , gem5::RiscvISA::CSR_MHPMCOUNTER27H = 0xB9B , gem5::RiscvISA::CSR_MHPMCOUNTER28H = 0xB9C , gem5::RiscvISA::CSR_MHPMCOUNTER29H = 0xB9D , gem5::RiscvISA::CSR_MHPMCOUNTER30H = 0xB9E , gem5::RiscvISA::CSR_MHPMCOUNTER31H = 0xB9F , gem5::RiscvISA::CSR_MHPMEVENT03 = 0x323 , gem5::RiscvISA::CSR_MHPMEVENT04 = 0x324 , gem5::RiscvISA::CSR_MHPMEVENT05 = 0x325 , gem5::RiscvISA::CSR_MHPMEVENT06 = 0x326 , gem5::RiscvISA::CSR_MHPMEVENT07 = 0x327 , gem5::RiscvISA::CSR_MHPMEVENT08 = 0x328 , gem5::RiscvISA::CSR_MHPMEVENT09 = 0x329 , gem5::RiscvISA::CSR_MHPMEVENT10 = 0x32A , gem5::RiscvISA::CSR_MHPMEVENT11 = 0x32B , gem5::RiscvISA::CSR_MHPMEVENT12 = 0x32C , gem5::RiscvISA::CSR_MHPMEVENT13 = 0x32D , gem5::RiscvISA::CSR_MHPMEVENT14 = 0x32E , gem5::RiscvISA::CSR_MHPMEVENT15 = 0x32F , gem5::RiscvISA::CSR_MHPMEVENT16 = 0x330 , gem5::RiscvISA::CSR_MHPMEVENT17 = 0x331 , gem5::RiscvISA::CSR_MHPMEVENT18 = 0x332 , gem5::RiscvISA::CSR_MHPMEVENT19 = 0x333 , gem5::RiscvISA::CSR_MHPMEVENT20 = 0x334 , gem5::RiscvISA::CSR_MHPMEVENT21 = 0x335 , gem5::RiscvISA::CSR_MHPMEVENT22 = 0x336 , gem5::RiscvISA::CSR_MHPMEVENT23 = 0x337 , gem5::RiscvISA::CSR_MHPMEVENT24 = 0x338 , gem5::RiscvISA::CSR_MHPMEVENT25 = 0x339 , gem5::RiscvISA::CSR_MHPMEVENT26 = 0x33A , gem5::RiscvISA::CSR_MHPMEVENT27 = 0x33B , gem5::RiscvISA::CSR_MHPMEVENT28 = 0x33C , gem5::RiscvISA::CSR_MHPMEVENT29 = 0x33D , gem5::RiscvISA::CSR_MHPMEVENT30 = 0x33E , gem5::RiscvISA::CSR_MHPMEVENT31 = 0x33F , gem5::RiscvISA::CSR_TSELECT = 0x7A0 , gem5::RiscvISA::CSR_TDATA1 = 0x7A1 , gem5::RiscvISA::CSR_TDATA2 = 0x7A2 , gem5::RiscvISA::CSR_TDATA3 = 0x7A3 , gem5::RiscvISA::CSR_DCSR = 0x7B0 , gem5::RiscvISA::CSR_DPC = 0x7B1 , gem5::RiscvISA::CSR_DSCRATCH = 0x7B2 , gem5::RiscvISA::CSR_VSTART = 0x008 , gem5::RiscvISA::CSR_VXSAT = 0x009 , gem5::RiscvISA::CSR_VXRM = 0x00A , gem5::RiscvISA::CSR_VCSR = 0x00F , gem5::RiscvISA::CSR_VL = 0xC20 , gem5::RiscvISA::CSR_VTYPE = 0xC21 , gem5::RiscvISA::CSR_VLENB = 0xC22 }

Functions
constexpr RegClass	gem5::RiscvISA::miscRegClass (MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs)

template<typename... T>
constexpr uint64_t	gem5::RiscvISA::rvTypeFlags (T... args)

template<typename... T>
constexpr uint64_t	gem5::RiscvISA::isaExtsFlags (T... isa_exts)

constexpr uint64_t	gem5::RiscvISA::isaExtsFlags ()

	gem5::RiscvISA::BitUnion64 (STATUS) Bitfield< 63 > rv64_sd
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org.

	gem5::RiscvISA::EndBitUnion (STATUS) BitUnion64(MISA) Bitfield< 63
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, v1.11 and v1.12 in Figure 3.1, accessible at www.riscv.org.

	gem5::RiscvISA::EndBitUnion (MISA) BitUnion64(INTERRUPT) Bitfield< 63
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org.

	gem5::RiscvISA::EndBitUnion (INTERRUPT) const off_t MXL_OFFSETS[enums

Variables
const std::unordered_map< int, CSRMetadata >	gem5::RiscvISA::CSRData

Bitfield< 35, 34 >	gem5::RiscvISA::sxl

Bitfield< 33, 32 >	gem5::RiscvISA::uxl

Bitfield< 31 >	gem5::RiscvISA::rv32_sd

Bitfield< 22 >	gem5::RiscvISA::tsr

Bitfield< 21 >	gem5::RiscvISA::tw

Bitfield< 20 >	gem5::RiscvISA::tvm

Bitfield< 19 >	gem5::RiscvISA::mxr

Bitfield< 18 >	gem5::RiscvISA::sum

Bitfield< 17 >	gem5::RiscvISA::mprv

Bitfield< 16, 15 >	gem5::RiscvISA::xs

Bitfield< 14, 13 >	gem5::RiscvISA::fs

Bitfield< 12, 11 >	gem5::RiscvISA::mpp

Bitfield< 8 >	gem5::RiscvISA::spp

Bitfield< 7 >	gem5::RiscvISA::mpie

Bitfield< 5 >	gem5::RiscvISA::spie

Bitfield< 4 >	gem5::RiscvISA::upie

Bitfield< 3 >	gem5::RiscvISA::mie

Bitfield< 1 >	gem5::RiscvISA::sie

Bitfield< 0 >	gem5::RiscvISA::uie

	gem5::RiscvISA::rv64_mxl

Bitfield< 31, 30 >	gem5::RiscvISA::rv32_mxl

Bitfield< 23 >	gem5::RiscvISA::rvx

Bitfield< 21 >	gem5::RiscvISA::rvv

Bitfield< 20 >	gem5::RiscvISA::rvu

Bitfield< 19 >	gem5::RiscvISA::rvt

Bitfield< 18 >	gem5::RiscvISA::rvs

Bitfield< 16 >	gem5::RiscvISA::rvq

Bitfield< 15 >	gem5::RiscvISA::rvp

Bitfield< 13 >	gem5::RiscvISA::rvn

Bitfield< 12 >	gem5::RiscvISA::rvm

Bitfield< 11 >	gem5::RiscvISA::rvl

Bitfield< 10 >	gem5::RiscvISA::rvk

Bitfield< 9 >	gem5::RiscvISA::rvj

Bitfield< 8 >	gem5::RiscvISA::rvi

Bitfield< 7 >	gem5::RiscvISA::rvh

Bitfield< 6 >	gem5::RiscvISA::rvg

Bitfield< 5 >	gem5::RiscvISA::rvf

Bitfield< 4 >	gem5::RiscvISA::rve

Bitfield< 3 >	gem5::RiscvISA::rvd

Bitfield< 2 >	gem5::RiscvISA::rvc

Bitfield< 1 >	gem5::RiscvISA::rvb

Bitfield< 0 >	gem5::RiscvISA::rva

	gem5::RiscvISA::local

Bitfield< 11 >	gem5::RiscvISA::mei

Bitfield< 9 >	gem5::RiscvISA::sei

Bitfield< 8 >	gem5::RiscvISA::uei

Bitfield< 7 >	gem5::RiscvISA::mti

Bitfield< 5 >	gem5::RiscvISA::sti

Bitfield< 4 >	gem5::RiscvISA::uti

Bitfield< 3 >	gem5::RiscvISA::msi

Bitfield< 1 >	gem5::RiscvISA::ssi

Bitfield< 0 >	gem5::RiscvISA::usi

const off_t	gem5::RiscvISA::MBE_OFFSET [enums::Num_RiscvType]

const off_t	gem5::RiscvISA::SBE_OFFSET [enums::Num_RiscvType]

const off_t	gem5::RiscvISA::SXL_OFFSET = 34

const off_t	gem5::RiscvISA::UXL_OFFSET = 32

const off_t	gem5::RiscvISA::FS_OFFSET = 13

const off_t	gem5::RiscvISA::VS_OFFSET = 9

const off_t	gem5::RiscvISA::FRM_OFFSET = 5

const RegVal	gem5::RiscvISA::ISA_MXL_MASKS [enums::Num_RiscvType]

const RegVal	gem5::RiscvISA::ISA_EXT_MASK = mask(26)

const RegVal	gem5::RiscvISA::ISA_EXT_C_MASK = 1UL << ('c' - 'a')

const RegVal	gem5::RiscvISA::MISA_MASKS [enums::Num_RiscvType]

const RegVal	gem5::RiscvISA::STATUS_SD_MASKS [enums::Num_RiscvType]

const RegVal	gem5::RiscvISA::STATUS_MBE_MASK [enums::Num_RiscvType]

const RegVal	gem5::RiscvISA::STATUS_SBE_MASK [enums::Num_RiscvType]

const RegVal	gem5::RiscvISA::STATUS_SXL_MASK = 3ULL << SXL_OFFSET

const RegVal	gem5::RiscvISA::STATUS_UXL_MASK = 3ULL << UXL_OFFSET

const RegVal	gem5::RiscvISA::STATUS_TSR_MASK = 1ULL << 22

const RegVal	gem5::RiscvISA::STATUS_TW_MASK = 1ULL << 21

const RegVal	gem5::RiscvISA::STATUS_TVM_MASK = 1ULL << 20

const RegVal	gem5::RiscvISA::STATUS_MXR_MASK = 1ULL << 19

const RegVal	gem5::RiscvISA::STATUS_SUM_MASK = 1ULL << 18

const RegVal	gem5::RiscvISA::STATUS_MPRV_MASK = 1ULL << 17

const RegVal	gem5::RiscvISA::STATUS_XS_MASK = 3ULL << 15

const RegVal	gem5::RiscvISA::STATUS_FS_MASK = 3ULL << FS_OFFSET

const RegVal	gem5::RiscvISA::STATUS_MPP_MASK = 3ULL << 11

const RegVal	gem5::RiscvISA::STATUS_VS_MASK = 3ULL << VS_OFFSET

const RegVal	gem5::RiscvISA::STATUS_SPP_MASK = 1ULL << 8

const RegVal	gem5::RiscvISA::STATUS_MPIE_MASK = 1ULL << 7

const RegVal	gem5::RiscvISA::STATUS_SPIE_MASK = 1ULL << 5

const RegVal	gem5::RiscvISA::STATUS_UPIE_MASK = 1ULL << 4

const RegVal	gem5::RiscvISA::STATUS_MIE_MASK = 1ULL << 3

const RegVal	gem5::RiscvISA::STATUS_SIE_MASK = 1ULL << 1

const RegVal	gem5::RiscvISA::STATUS_UIE_MASK = 1ULL << 0

const RegVal	gem5::RiscvISA::MSTATUS_MASKS [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::MSTATUSH_MASKS [enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::SSTATUS_MASKS [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::USTATUS_MASKS [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::LOCAL_MASK = mask(63,16)

const RegVal	gem5::RiscvISA::MEI_MASK = 1ULL << 11

const RegVal	gem5::RiscvISA::SEI_MASK = 1ULL << 9

const RegVal	gem5::RiscvISA::UEI_MASK = 1ULL << 8

const RegVal	gem5::RiscvISA::MTI_MASK = 1ULL << 7

const RegVal	gem5::RiscvISA::STI_MASK = 1ULL << 5

const RegVal	gem5::RiscvISA::UTI_MASK = 1ULL << 4

const RegVal	gem5::RiscvISA::MSI_MASK = 1ULL << 3

const RegVal	gem5::RiscvISA::SSI_MASK = 1ULL << 1

const RegVal	gem5::RiscvISA::USI_MASK = 1ULL << 0

const RegVal	gem5::RiscvISA::MI_MASK [enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::SI_MASK [enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::UI_MASK [enums::Num_PrivilegeModeSet]

const RegVal	gem5::RiscvISA::FFLAGS_MASK = (1 << FRM_OFFSET) - 1

const RegVal	gem5::RiscvISA::FRM_MASK = 0x7

const RegVal	gem5::RiscvISA::CAUSE_INTERRUPT_MASKS [enums::Num_RiscvType]

const std::unordered_map< int, RegVal >	gem5::RiscvISA::CSRMasks [enums::Num_RiscvType][enums::Num_PrivilegeModeSet]

Classes

Namespaces

Enumerations

Functions

Variables