gem5 v24.1.0.1
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misc.hh
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1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * Copyright (c) 2019 Yifei Liu
5 * Copyright (c) 2020 Barkhausen Institut
6 * Copyright (c) 2021 StreamComputing Corp
7 * All rights reserved
8 *
9 * The license below extends only to copyright in the software and shall
10 * not be construed as granting a license to any other intellectual
11 * property including but not limited to intellectual property relating
12 * to a hardware implementation of the functionality of the software
13 * licensed hereunder. You may use the software subject to the license
14 * terms below provided that you ensure that this notice is replicated
15 * unmodified and in its entirety in all distributions of the software,
16 * modified or unmodified, in source code or in binary form.
17 *
18 * Copyright (c) 2016 RISC-V Foundation
19 * Copyright (c) 2016 The University of Virginia
20 * Copyright (c) 2024 University of Rostock
21 * All rights reserved.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions are
25 * met: redistributions of source code must retain the above copyright
26 * notice, this list of conditions and the following disclaimer;
27 * redistributions in binary form must reproduce the above copyright
28 * notice, this list of conditions and the following disclaimer in the
29 * documentation and/or other materials provided with the distribution;
30 * neither the name of the copyright holders nor the names of its
31 * contributors may be used to endorse or promote products derived from
32 * this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 */
46
47#ifndef __ARCH_RISCV_REGS_MISC_HH__
48#define __ARCH_RISCV_REGS_MISC_HH__
49
50#include <string>
51#include <unordered_map>
52
55#include "arch/riscv/types.hh"
56#include "base/bitunion.hh"
57#include "base/types.hh"
58#include "cpu/reg_class.hh"
59#include "debug/MiscRegs.hh"
60#include "enums/RiscvType.hh"
61
62namespace gem5
63{
64
65namespace RiscvISA
66{
67
69{
147
157 MISCREG_PMPCFG1, // pmpcfg1 is rv32 only
159 MISCREG_PMPCFG3, // pmpcfg3 is rv32 only
176
187
195
203
204 // These registers are not in the standard, hence does not exist in the
205 // CSRData map. These are mainly used to provide a minimal implementation
206 // for non-maskable-interrupt in our simple cpu.
207 // non-maskable-interrupt-vector-base-address: NMI version of xTVEC
209 // non-maskable-interrupt-enable: NMI version of xIE
211 // non-maskable-interrupt-pending: NMI version of xIP
213
214 // the following MicsRegIndex are RV32 only
216
249
251
255 // This CSR shared the same space with MISCREG_FFLAGS
264
267
269 NUM_MISCREGS, debug::MiscRegs);
270
272{
273 CSR_USTATUS = 0x000,
274 CSR_UIE = 0x004,
275 CSR_UTVEC = 0x005,
277 CSR_UEPC = 0x041,
278 CSR_UCAUSE = 0x042,
279 CSR_UTVAL = 0x043,
280 CSR_UIP = 0x044,
281 CSR_FFLAGS = 0x001,
282 CSR_FRM = 0x002,
283 CSR_FCSR = 0x003,
284 CSR_CYCLE = 0xC00,
285 CSR_TIME = 0xC01,
286 CSR_INSTRET = 0xC02,
316
317 // rv32 only csr register begin
318 CSR_CYCLEH = 0xC80,
319 CSR_TIMEH = 0xC81,
350 // rv32 only csr register end
351
352 CSR_SSTATUS = 0x100,
353 CSR_SEDELEG = 0x102,
354 CSR_SIDELEG = 0x103,
355 CSR_SIE = 0x104,
356 CSR_STVEC = 0x105,
359 CSR_SEPC = 0x141,
360 CSR_SCAUSE = 0x142,
361 CSR_STVAL = 0x143,
362 CSR_SIP = 0x144,
363 CSR_SATP = 0x180,
364 CSR_SENVCFG = 0x10A, // 20240411 RISCV spec, volume 2
365
367 CSR_MARCHID = 0xF12,
368 CSR_MIMPID = 0xF13,
369 CSR_MHARTID = 0xF14,
370 CSR_MSTATUS = 0x300,
371 CSR_MISA = 0x301,
372 CSR_MEDELEG = 0x302,
373 CSR_MIDELEG = 0x303,
374 CSR_MIE = 0x304,
375 CSR_MTVEC = 0x305,
377 CSR_MSTATUSH = 0x310, // rv32 only
379 CSR_MEPC = 0x341,
380 CSR_MCAUSE = 0x342,
381 CSR_MTVAL = 0x343,
382 CSR_MIP = 0x344,
383 CSR_PMPCFG0 = 0x3A0,
384 CSR_PMPCFG1 = 0x3A1, // pmpcfg1 rv32 only
385 CSR_PMPCFG2 = 0x3A2,
386 CSR_PMPCFG3 = 0x3A3,// pmpcfg3 rv32 only
403 CSR_MCYCLE = 0xB00,
434
435 // rv32 only csr register begin
436 CSR_MCYCLEH = 0xB80,
467 // rv32 only csr register end
468
498
499 CSR_TSELECT = 0x7A0,
500 CSR_TDATA1 = 0x7A1,
501 CSR_TDATA2 = 0x7A2,
502 CSR_TDATA3 = 0x7A3,
503 CSR_DCSR = 0x7B0,
504 CSR_DPC = 0x7B1,
506
507 CSR_VSTART = 0x008,
508 CSR_VXSAT = 0x009,
509 CSR_VXRM = 0x00A,
510 CSR_VCSR = 0x00F,
511 CSR_VL = 0xC20,
512 CSR_VTYPE = 0xC21,
513 CSR_VLENB = 0xC22
515
517{
518 const std::string name;
519 const int physIndex;
520 const uint64_t rvTypes;
521 const uint64_t isaExts;
522};
523
524template <typename... T>
525constexpr uint64_t rvTypeFlags(T... args) {
526 return ((1 << args) | ...);
527}
528
529template <typename... T>
530constexpr uint64_t isaExtsFlags(T... isa_exts) {
531 return ((1ULL << (isa_exts - 'a')) | ...);
532}
533
534constexpr uint64_t isaExtsFlags() {
535 return 0ULL;
536}
537
538const std::unordered_map<int, CSRMetadata> CSRData = {
540 {"ustatus", MISCREG_USTATUS, rvTypeFlags(RV64, RV32),
541 isaExtsFlags('n')}},
542 {CSR_UIE,
543 {"uie", MISCREG_UIE, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}},
544 {CSR_UTVEC,
545 {"utvec", MISCREG_UTVEC, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}},
547 {"uscratch", MISCREG_USCRATCH, rvTypeFlags(RV64, RV32),
548 isaExtsFlags('n')}},
549 {CSR_UEPC,
550 {"uepc", MISCREG_UEPC, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}},
551 {CSR_UCAUSE,
552 {"ucause", MISCREG_UCAUSE, rvTypeFlags(RV64, RV32),
553 isaExtsFlags('n')}},
554 {CSR_UTVAL,
555 {"utval", MISCREG_UTVAL, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}},
556 {CSR_UIP,
557 {"uip", MISCREG_UIP, rvTypeFlags(RV64, RV32), isaExtsFlags('n')}},
558 {CSR_FFLAGS,
559 {"fflags", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32),
560 isaExtsFlags('f')}},
561 {CSR_FRM,
562 {"frm", MISCREG_FRM, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
563 {CSR_FCSR,
564 {"fcsr", MISCREG_FCSR, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
565 {CSR_CYCLE,
567 {CSR_TIME,
572 {"hpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32),
573 isaExtsFlags()}},
575 {"hpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32),
576 isaExtsFlags()}},
578 {"hpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32),
579 isaExtsFlags()}},
581 {"hpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32),
582 isaExtsFlags()}},
584 {"hpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32),
585 isaExtsFlags()}},
587 {"hpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32),
588 isaExtsFlags()}},
590 {"hpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32),
591 isaExtsFlags()}},
593 {"hpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32),
594 isaExtsFlags()}},
596 {"hpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32),
597 isaExtsFlags()}},
599 {"hpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32),
600 isaExtsFlags()}},
602 {"hpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32),
603 isaExtsFlags()}},
605 {"hpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32),
606 isaExtsFlags()}},
608 {"hpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32),
609 isaExtsFlags()}},
611 {"hpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32),
612 isaExtsFlags()}},
614 {"hpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32),
615 isaExtsFlags()}},
617 {"hpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32),
618 isaExtsFlags()}},
620 {"hpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32),
621 isaExtsFlags()}},
623 {"hpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32),
624 isaExtsFlags()}},
626 {"hpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32),
627 isaExtsFlags()}},
629 {"hpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32),
630 isaExtsFlags()}},
632 {"hpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32),
633 isaExtsFlags()}},
635 {"hpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32),
636 isaExtsFlags()}},
638 {"hpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32),
639 isaExtsFlags()}},
641 {"hpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32),
642 isaExtsFlags()}},
644 {"hpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32),
645 isaExtsFlags()}},
647 {"hpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32),
648 isaExtsFlags()}},
650 {"hpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32),
651 isaExtsFlags()}},
653 {"hpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32),
654 isaExtsFlags()}},
656 {"hpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32),
657 isaExtsFlags()}},
658 {CSR_CYCLEH,
660 {CSR_TIMEH,
663 {"instreth", MISCREG_INSTRETH, rvTypeFlags(RV32), isaExtsFlags()}},
665 {"hpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32),
666 isaExtsFlags()}},
668 {"hpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32),
669 isaExtsFlags()}},
671 {"hpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32),
672 isaExtsFlags()}},
674 {"hpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32),
675 isaExtsFlags()}},
677 {"hpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32),
678 isaExtsFlags()}},
680 {"hpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32),
681 isaExtsFlags()}},
683 {"hpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32),
684 isaExtsFlags()}},
686 {"hpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32),
687 isaExtsFlags()}},
689 {"hpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32),
690 isaExtsFlags()}},
692 {"hpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32),
693 isaExtsFlags()}},
695 {"hpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32),
696 isaExtsFlags()}},
698 {"hpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32),
699 isaExtsFlags()}},
701 {"hpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32),
702 isaExtsFlags()}},
704 {"hpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32),
705 isaExtsFlags()}},
707 {"hpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32),
708 isaExtsFlags()}},
710 {"hpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32),
711 isaExtsFlags()}},
713 {"hpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32),
714 isaExtsFlags()}},
716 {"hpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32),
717 isaExtsFlags()}},
719 {"hpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32),
720 isaExtsFlags()}},
722 {"hpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32),
723 isaExtsFlags()}},
725 {"hpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32),
726 isaExtsFlags()}},
728 {"hpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32),
729 isaExtsFlags()}},
731 {"hpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32),
732 isaExtsFlags()}},
734 {"hpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32),
735 isaExtsFlags()}},
737 {"hpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32),
738 isaExtsFlags()}},
740 {"hpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32),
741 isaExtsFlags()}},
743 {"hpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32),
744 isaExtsFlags()}},
746 {"hpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32),
747 isaExtsFlags()}},
749 {"hpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32),
750 isaExtsFlags()}},
751
753 {"sstatus", MISCREG_SSTATUS, rvTypeFlags(RV64, RV32),
754 isaExtsFlags('s')}},
756 {"sedeleg", MISCREG_SEDELEG, rvTypeFlags(RV64, RV32),
757 isaExtsFlags('s')}},
759 {"sideleg", MISCREG_SIDELEG, rvTypeFlags(RV64, RV32),
760 isaExtsFlags('s')}},
761 {CSR_SIE,
762 {"sie", MISCREG_SIE, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
763 {CSR_STVEC,
764 {"stvec", MISCREG_STVEC, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
766 {"scounteren", MISCREG_SCOUNTEREN, rvTypeFlags(RV64, RV32),
767 isaExtsFlags('s')}},
769 {"sscratch", MISCREG_SSCRATCH, rvTypeFlags(RV64, RV32),
770 isaExtsFlags('s')}},
771 {CSR_SEPC,
772 {"sepc", MISCREG_SEPC, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
773 {CSR_SCAUSE,
774 {"scause", MISCREG_SCAUSE, rvTypeFlags(RV64, RV32),
775 isaExtsFlags('s')}},
776 {CSR_STVAL,
777 {"stval", MISCREG_STVAL, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
778 {CSR_SIP,
779 {"sip", MISCREG_SIP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
780 {CSR_SATP,
781 {"satp", MISCREG_SATP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
783 {"senvcfg", MISCREG_SENVCFG, rvTypeFlags(RV64, RV32),
784 isaExtsFlags('s')}},
785
787 {"mvendorid", MISCREG_VENDORID, rvTypeFlags(RV64, RV32),
788 isaExtsFlags()}},
790 {"marchid", MISCREG_ARCHID, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
791 {CSR_MIMPID,
794 {"mhartid", MISCREG_HARTID, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
797 {CSR_MISA,
803 {CSR_MIE,
805 {CSR_MTVEC,
808 {"mcounteren", MISCREG_MCOUNTEREN, rvTypeFlags(RV64, RV32),
809 isaExtsFlags()}},
811 {"mstatush", MISCREG_MSTATUSH, rvTypeFlags(RV32), isaExtsFlags()}},
813 {"mscratch", MISCREG_MSCRATCH, rvTypeFlags(RV64, RV32),
814 isaExtsFlags()}},
815 {CSR_MEPC,
817 {CSR_MCAUSE,
819 {CSR_MTVAL,
821 {CSR_MIP,
825 // pmpcfg1 rv32 only
827 {"pmpcfg1", MISCREG_PMPCFG1, rvTypeFlags(RV32), isaExtsFlags()}},
830 // pmpcfg3 rv32 only
832 {"pmpcfg3", MISCREG_PMPCFG3, rvTypeFlags(RV32), isaExtsFlags()}},
834 {"pmpaddr0", MISCREG_PMPADDR00, rvTypeFlags(RV64, RV32),
835 isaExtsFlags()}},
837 {"pmpaddr1", MISCREG_PMPADDR01, rvTypeFlags(RV64, RV32),
838 isaExtsFlags()}},
840 {"pmpaddr2", MISCREG_PMPADDR02, rvTypeFlags(RV64, RV32),
841 isaExtsFlags()}},
843 {"pmpaddr3", MISCREG_PMPADDR03, rvTypeFlags(RV64, RV32),
844 isaExtsFlags()}},
846 {"pmpaddr4", MISCREG_PMPADDR04, rvTypeFlags(RV64, RV32),
847 isaExtsFlags()}},
849 {"pmpaddr5", MISCREG_PMPADDR05, rvTypeFlags(RV64, RV32),
850 isaExtsFlags()}},
852 {"pmpaddr6", MISCREG_PMPADDR06, rvTypeFlags(RV64, RV32),
853 isaExtsFlags()}},
855 {"pmpaddr7", MISCREG_PMPADDR07, rvTypeFlags(RV64, RV32),
856 isaExtsFlags()}},
858 {"pmpaddr8", MISCREG_PMPADDR08, rvTypeFlags(RV64, RV32),
859 isaExtsFlags()}},
861 {"pmpaddr9", MISCREG_PMPADDR09, rvTypeFlags(RV64, RV32),
862 isaExtsFlags()}},
864 {"pmpaddr10", MISCREG_PMPADDR10, rvTypeFlags(RV64, RV32),
865 isaExtsFlags()}},
867 {"pmpaddr11", MISCREG_PMPADDR11, rvTypeFlags(RV64, RV32),
868 isaExtsFlags()}},
870 {"pmpaddr12", MISCREG_PMPADDR12, rvTypeFlags(RV64, RV32),
871 isaExtsFlags()}},
873 {"pmpaddr13", MISCREG_PMPADDR13, rvTypeFlags(RV64, RV32),
874 isaExtsFlags()}},
876 {"pmpaddr14", MISCREG_PMPADDR14, rvTypeFlags(RV64, RV32),
877 isaExtsFlags()}},
879 {"pmpaddr15", MISCREG_PMPADDR15, rvTypeFlags(RV64, RV32),
880 isaExtsFlags()}},
881 {CSR_MCYCLE,
884 {"minstret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32),
885 isaExtsFlags()}},
887 {"mhpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32),
888 isaExtsFlags()}},
890 {"mhpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32),
891 isaExtsFlags()}},
893 {"mhpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32),
894 isaExtsFlags()}},
896 {"mhpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32),
897 isaExtsFlags()}},
899 {"mhpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32),
900 isaExtsFlags()}},
902 {"mhpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32),
903 isaExtsFlags()}},
905 {"mhpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32),
906 isaExtsFlags()}},
908 {"mhpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32),
909 isaExtsFlags()}},
911 {"mhpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32),
912 isaExtsFlags()}},
914 {"mhpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32),
915 isaExtsFlags()}},
917 {"mhpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32),
918 isaExtsFlags()}},
920 {"mhpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32),
921 isaExtsFlags()}},
923 {"mhpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32),
924 isaExtsFlags()}},
926 {"mhpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32),
927 isaExtsFlags()}},
929 {"mhpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32),
930 isaExtsFlags()}},
932 {"mhpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32),
933 isaExtsFlags()}},
935 {"mhpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32),
936 isaExtsFlags()}},
938 {"mhpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32),
939 isaExtsFlags()}},
941 {"mhpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32),
942 isaExtsFlags()}},
944 {"mhpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32),
945 isaExtsFlags()}},
947 {"mhpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32),
948 isaExtsFlags()}},
950 {"mhpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32),
951 isaExtsFlags()}},
953 {"mhpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32),
954 isaExtsFlags()}},
956 {"mhpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32),
957 isaExtsFlags()}},
959 {"mhpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32),
960 isaExtsFlags()}},
962 {"mhpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32),
963 isaExtsFlags()}},
965 {"mhpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32),
966 isaExtsFlags()}},
968 {"mhpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32),
969 isaExtsFlags()}},
971 {"mhpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32),
972 isaExtsFlags()}},
973
975 {"mcycleh", MISCREG_CYCLEH, rvTypeFlags(RV32), isaExtsFlags()}},
977 {"minstreth", MISCREG_INSTRETH, rvTypeFlags(RV32), isaExtsFlags()}},
979 {"mhpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32),
980 isaExtsFlags()}},
982 {"mhpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32),
983 isaExtsFlags()}},
985 {"mhpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32),
986 isaExtsFlags()}},
988 {"mhpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32),
989 isaExtsFlags()}},
991 {"mhpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32),
992 isaExtsFlags()}},
994 {"mhpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32),
995 isaExtsFlags()}},
997 {"mhpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32),
998 isaExtsFlags()}},
1000 {"mhpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32),
1001 isaExtsFlags()}},
1003 {"mhpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32),
1004 isaExtsFlags()}},
1006 {"mhpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32),
1007 isaExtsFlags()}},
1009 {"mhpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32),
1010 isaExtsFlags()}},
1012 {"mhpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32),
1013 isaExtsFlags()}},
1015 {"mhpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32),
1016 isaExtsFlags()}},
1018 {"mhpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32),
1019 isaExtsFlags()}},
1021 {"mhpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32),
1022 isaExtsFlags()}},
1024 {"mhpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32),
1025 isaExtsFlags()}},
1027 {"mhpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32),
1028 isaExtsFlags()}},
1030 {"mhpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32),
1031 isaExtsFlags()}},
1033 {"mhpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32),
1034 isaExtsFlags()}},
1036 {"mhpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32),
1037 isaExtsFlags()}},
1039 {"mhpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32),
1040 isaExtsFlags()}},
1042 {"mhpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32),
1043 isaExtsFlags()}},
1045 {"mhpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32),
1046 isaExtsFlags()}},
1048 {"mhpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32),
1049 isaExtsFlags()}},
1051 {"mhpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32),
1052 isaExtsFlags()}},
1054 {"mhpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32),
1055 isaExtsFlags()}},
1057 {"mhpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32),
1058 isaExtsFlags()}},
1060 {"mhpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32),
1061 isaExtsFlags()}},
1063 {"mhpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32),
1064 isaExtsFlags()}},
1065
1067 {"mhpmevent03", MISCREG_HPMEVENT03, rvTypeFlags(RV64, RV32),
1068 isaExtsFlags()}},
1070 {"mhpmevent04", MISCREG_HPMEVENT04, rvTypeFlags(RV64, RV32),
1071 isaExtsFlags()}},
1073 {"mhpmevent05", MISCREG_HPMEVENT05, rvTypeFlags(RV64, RV32),
1074 isaExtsFlags()}},
1076 {"mhpmevent06", MISCREG_HPMEVENT06, rvTypeFlags(RV64, RV32),
1077 isaExtsFlags()}},
1079 {"mhpmevent07", MISCREG_HPMEVENT07, rvTypeFlags(RV64, RV32),
1080 isaExtsFlags()}},
1082 {"mhpmevent08", MISCREG_HPMEVENT08, rvTypeFlags(RV64, RV32),
1083 isaExtsFlags()}},
1085 {"mhpmevent09", MISCREG_HPMEVENT09, rvTypeFlags(RV64, RV32),
1086 isaExtsFlags()}},
1088 {"mhpmevent10", MISCREG_HPMEVENT10, rvTypeFlags(RV64, RV32),
1089 isaExtsFlags()}},
1091 {"mhpmevent11", MISCREG_HPMEVENT11, rvTypeFlags(RV64, RV32),
1092 isaExtsFlags()}},
1094 {"mhpmevent12", MISCREG_HPMEVENT12, rvTypeFlags(RV64, RV32),
1095 isaExtsFlags()}},
1097 {"mhpmevent13", MISCREG_HPMEVENT13, rvTypeFlags(RV64, RV32),
1098 isaExtsFlags()}},
1100 {"mhpmevent14", MISCREG_HPMEVENT14, rvTypeFlags(RV64, RV32),
1101 isaExtsFlags()}},
1103 {"mhpmevent15", MISCREG_HPMEVENT15, rvTypeFlags(RV64, RV32),
1104 isaExtsFlags()}},
1106 {"mhpmevent16", MISCREG_HPMEVENT16, rvTypeFlags(RV64, RV32),
1107 isaExtsFlags()}},
1109 {"mhpmevent17", MISCREG_HPMEVENT17, rvTypeFlags(RV64, RV32),
1110 isaExtsFlags()}},
1112 {"mhpmevent18", MISCREG_HPMEVENT18, rvTypeFlags(RV64, RV32),
1113 isaExtsFlags()}},
1115 {"mhpmevent19", MISCREG_HPMEVENT19, rvTypeFlags(RV64, RV32),
1116 isaExtsFlags()}},
1118 {"mhpmevent20", MISCREG_HPMEVENT20, rvTypeFlags(RV64, RV32),
1119 isaExtsFlags()}},
1121 {"mhpmevent21", MISCREG_HPMEVENT21, rvTypeFlags(RV64, RV32),
1122 isaExtsFlags()}},
1124 {"mhpmevent22", MISCREG_HPMEVENT22, rvTypeFlags(RV64, RV32),
1125 isaExtsFlags()}},
1127 {"mhpmevent23", MISCREG_HPMEVENT23, rvTypeFlags(RV64, RV32),
1128 isaExtsFlags()}},
1130 {"mhpmevent24", MISCREG_HPMEVENT24, rvTypeFlags(RV64, RV32),
1131 isaExtsFlags()}},
1133 {"mhpmevent25", MISCREG_HPMEVENT25, rvTypeFlags(RV64, RV32),
1134 isaExtsFlags()}},
1136 {"mhpmevent26", MISCREG_HPMEVENT26, rvTypeFlags(RV64, RV32),
1137 isaExtsFlags()}},
1139 {"mhpmevent27", MISCREG_HPMEVENT27, rvTypeFlags(RV64, RV32),
1140 isaExtsFlags()}},
1142 {"mhpmevent28", MISCREG_HPMEVENT28, rvTypeFlags(RV64, RV32),
1143 isaExtsFlags()}},
1145 {"mhpmevent29", MISCREG_HPMEVENT29, rvTypeFlags(RV64, RV32),
1146 isaExtsFlags()}},
1148 {"mhpmevent30", MISCREG_HPMEVENT30, rvTypeFlags(RV64, RV32),
1149 isaExtsFlags()}},
1151 {"mhpmevent31", MISCREG_HPMEVENT31, rvTypeFlags(RV64, RV32),
1152 isaExtsFlags()}},
1153
1154 {CSR_TSELECT,
1155 {"tselect", MISCREG_TSELECT, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1156 {CSR_TDATA1,
1157 {"tdata1", MISCREG_TDATA1, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1158 {CSR_TDATA2,
1159 {"tdata2", MISCREG_TDATA2, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1160 {CSR_TDATA3,
1161 {"tdata3", MISCREG_TDATA3, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1162 {CSR_DCSR,
1164 {CSR_DPC,
1166 {CSR_DSCRATCH,
1167 {"dscratch", MISCREG_DSCRATCH, rvTypeFlags(RV64, RV32),
1168 isaExtsFlags()}},
1169
1170 {CSR_VSTART,
1171 {"vstart", MISCREG_VSTART, rvTypeFlags(RV64, RV32),
1172 isaExtsFlags('v')}},
1173 {CSR_VXSAT,
1174 {"vxsat", MISCREG_VXSAT, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1175 {CSR_VXRM,
1176 {"vxrm", MISCREG_VXRM, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1177 {CSR_VCSR,
1178 {"vcsr", MISCREG_VCSR, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1179 {CSR_VL,
1180 {"vl", MISCREG_VL, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1181 {CSR_VTYPE,
1182 {"vtype", MISCREG_VTYPE, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1183 {CSR_VLENB,
1184 {"VLENB", MISCREG_VLENB, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}}
1185};
1186
1195 Bitfield<63> rv64_sd;
1196 Bitfield<35, 34> sxl;
1197 Bitfield<33, 32> uxl;
1198 Bitfield<31> rv32_sd;
1199 Bitfield<22> tsr;
1200 Bitfield<21> tw;
1201 Bitfield<20> tvm;
1202 Bitfield<19> mxr;
1203 Bitfield<18> sum;
1204 Bitfield<17> mprv;
1205 Bitfield<16, 15> xs;
1206 Bitfield<14, 13> fs;
1207 Bitfield<12, 11> mpp;
1208 Bitfield<10, 9> vs;
1209 Bitfield<8> spp;
1210 Bitfield<7> mpie;
1211 Bitfield<5> spie;
1212 Bitfield<4> upie;
1213 Bitfield<3> mie;
1214 Bitfield<1> sie;
1215 Bitfield<0> uie;
1217
1218
1223BitUnion64(MISA)
1224 Bitfield<63, 62> rv64_mxl;
1225 Bitfield<31, 30> rv32_mxl;
1226 Bitfield<23> rvx;
1227 Bitfield<21> rvv;
1228 Bitfield<20> rvu;
1229 Bitfield<19> rvt;
1230 Bitfield<18> rvs;
1231 Bitfield<16> rvq;
1232 Bitfield<15> rvp;
1233 Bitfield<13> rvn;
1234 Bitfield<12> rvm;
1235 Bitfield<11> rvl;
1236 Bitfield<10> rvk;
1237 Bitfield<9> rvj;
1238 Bitfield<8> rvi;
1239 Bitfield<7> rvh;
1240 Bitfield<6> rvg;
1241 Bitfield<5> rvf;
1242 Bitfield<4> rve;
1243 Bitfield<3> rvd;
1244 Bitfield<2> rvc;
1245 Bitfield<1> rvb;
1246 Bitfield<0> rva;
1248
1256 Bitfield<63,16> local;
1257 Bitfield<11> mei;
1258 Bitfield<9> sei;
1259 Bitfield<8> uei;
1260 Bitfield<7> mti;
1261 Bitfield<5> sti;
1262 Bitfield<4> uti;
1263 Bitfield<3> msi;
1264 Bitfield<1> ssi;
1265 Bitfield<0> usi;
1267
1268
1269// From the RISCV specification version 20240411, volume 2,
1270// section 10.1.10, page 98
1271BitUnion64(SENVCFG)
1272 Bitfield<63,34> wpri_1;
1273 Bitfield<33,32> pmm;
1274 Bitfield<31,8> wpri_2;
1275 Bitfield<7> cbze;
1276 Bitfield<6> cbcfe;
1277 Bitfield<5,4> cbie;
1278 Bitfield<3,1> wpri_3;
1279 Bitfield<0> fiom;
1281
1282const off_t MXL_OFFSETS[enums::Num_RiscvType] = {
1283 [RV32] = (sizeof(uint32_t) * 8 - 2),
1284 [RV64] = (sizeof(uint64_t) * 8 - 2),
1285};
1286const off_t MBE_OFFSET[enums::Num_RiscvType] = {
1287 [RV32] = 5,
1288 [RV64] = 37,
1289};
1290const off_t SBE_OFFSET[enums::Num_RiscvType] = {
1291 [RV32] = 4,
1292 [RV64] = 36,
1293};
1294const off_t SXL_OFFSET = 34;
1295const off_t UXL_OFFSET = 32;
1296const off_t FS_OFFSET = 13;
1297const off_t VS_OFFSET = 9;
1298const off_t FRM_OFFSET = 5;
1299
1300const RegVal ISA_MXL_MASKS[enums::Num_RiscvType] = {
1301 [RV32] = 3ULL << MXL_OFFSETS[RV32],
1302 [RV64] = 3ULL << MXL_OFFSETS[RV64],
1303};
1305const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
1306const RegVal MISA_MASKS[enums::Num_RiscvType] = {
1309};
1310
1311
1312const RegVal STATUS_SD_MASKS[enums::Num_RiscvType] = {
1313 [RV32] = 1ULL << ((sizeof(uint32_t) * 8) - 1),
1314 [RV64] = 1ULL << ((sizeof(uint64_t) * 8) - 1),
1315};
1316const RegVal STATUS_MBE_MASK[enums::Num_RiscvType] = {
1317 [RV32] = 1ULL << MBE_OFFSET[RV32],
1318 [RV64] = 1ULL << MBE_OFFSET[RV64],
1319};
1320const RegVal STATUS_SBE_MASK[enums::Num_RiscvType] = {
1321 [RV32] = 1ULL << SBE_OFFSET[RV32],
1322 [RV64] = 1ULL << SBE_OFFSET[RV64],
1323};
1326const RegVal STATUS_TSR_MASK = 1ULL << 22;
1327const RegVal STATUS_TW_MASK = 1ULL << 21;
1328const RegVal STATUS_TVM_MASK = 1ULL << 20;
1329const RegVal STATUS_MXR_MASK = 1ULL << 19;
1330const RegVal STATUS_SUM_MASK = 1ULL << 18;
1331const RegVal STATUS_MPRV_MASK = 1ULL << 17;
1332const RegVal STATUS_XS_MASK = 3ULL << 15;
1334const RegVal STATUS_MPP_MASK = 3ULL << 11;
1336const RegVal STATUS_SPP_MASK = 1ULL << 8;
1337const RegVal STATUS_MPIE_MASK = 1ULL << 7;
1338const RegVal STATUS_SPIE_MASK = 1ULL << 5;
1339const RegVal STATUS_UPIE_MASK = 1ULL << 4;
1340const RegVal STATUS_MIE_MASK = 1ULL << 3;
1341const RegVal STATUS_SIE_MASK = 1ULL << 1;
1342const RegVal STATUS_UIE_MASK = 1ULL << 0;
1343const RegVal
1344MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1345 [RV32] = {
1346 [enums::M] = STATUS_SD_MASKS[RV32] |
1349 [enums::MU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK |
1353 [enums::MNU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK |
1359 [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK |
1366 [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK |
1374 },
1375 [RV64] = {
1376 [enums::M] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] |
1379 [enums::MU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] |
1383 [enums::MNU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] |
1389 [enums::MSU] = STATUS_SD_MASKS[RV64] |
1398 [enums::MNSU] = STATUS_SD_MASKS[RV64] |
1407 },
1408};
1409// rv32 only
1410const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet] = {
1411 [enums::M] = STATUS_MBE_MASK[RV32],
1412 [enums::MU] = STATUS_MBE_MASK[RV32],
1413 [enums::MNU] = STATUS_MBE_MASK[RV32],
1414 [enums::MSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32],
1415 [enums::MNSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32],
1416};
1417const RegVal
1418SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1419 [RV32] = {
1420 [enums::M] = 0ULL,
1421 [enums::MU] = 0ULL,
1422 [enums::MNU] = 0ULL,
1423 [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK |
1427 [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK |
1432 },
1433 [RV64] = {
1434 [enums::M] = 0ULL,
1435 [enums::MU] = 0ULL,
1436 [enums::MNU] = 0ULL,
1437 [enums::MSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK |
1441 [enums::MNSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK |
1446 },
1447};
1448const RegVal
1449USTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1450 [RV32] = {
1451 [enums::M] = 0ULL,
1452 [enums::MU] = 0ULL,
1453 [enums::MNU] = STATUS_SD_MASKS[RV32] |
1456 [enums::MSU] = 0ULL,
1457 [enums::MNSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK |
1461 },
1462 [RV64] = {
1463 [enums::M] = 0ULL,
1464 [enums::MU] = 0ULL,
1465 [enums::MNU] = STATUS_SD_MASKS[RV64] |
1468 [enums::MSU] = 0ULL,
1469 [enums::MNSU] = STATUS_SD_MASKS[RV64] | STATUS_MXR_MASK |
1473 },
1474};
1475
1476const RegVal LOCAL_MASK = mask(63,16);
1477const RegVal MEI_MASK = 1ULL << 11;
1478const RegVal SEI_MASK = 1ULL << 9;
1479const RegVal UEI_MASK = 1ULL << 8;
1480const RegVal MTI_MASK = 1ULL << 7;
1481const RegVal STI_MASK = 1ULL << 5;
1482const RegVal UTI_MASK = 1ULL << 4;
1483const RegVal MSI_MASK = 1ULL << 3;
1484const RegVal SSI_MASK = 1ULL << 1;
1485const RegVal USI_MASK = 1ULL << 0;
1486const RegVal MI_MASK[enums::Num_PrivilegeModeSet] = {
1487 [enums::M] = LOCAL_MASK | MEI_MASK| MTI_MASK | MSI_MASK,
1488 [enums::MU] = LOCAL_MASK | MEI_MASK| MTI_MASK | MSI_MASK,
1489 [enums::MNU] = LOCAL_MASK | MEI_MASK | UEI_MASK | MTI_MASK | UTI_MASK |
1491 [enums::MSU] = LOCAL_MASK | MEI_MASK | SEI_MASK | MTI_MASK | STI_MASK |
1493 [enums::MNSU] = LOCAL_MASK | MEI_MASK | SEI_MASK | UEI_MASK |
1496};
1497const RegVal SI_MASK[enums::Num_PrivilegeModeSet] = {
1498 [enums::M] = 0ULL,
1499 [enums::MU] = 0ULL,
1500 [enums::MNU] = UEI_MASK | UTI_MASK | USI_MASK,
1501 [enums::MSU] = SEI_MASK | STI_MASK | SSI_MASK,
1502 [enums::MNSU] = SEI_MASK | UEI_MASK |
1503 STI_MASK | UTI_MASK |
1505};
1506const RegVal UI_MASK[enums::Num_PrivilegeModeSet] = {
1507 [enums::M] = 0ULL,
1508 [enums::MU] = 0ULL,
1509 [enums::MNU] = UEI_MASK | UTI_MASK | USI_MASK,
1510 [enums::MSU] = 0ULL,
1511 [enums::MNSU] = UEI_MASK | UTI_MASK | USI_MASK,
1512};
1513const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
1514const RegVal FRM_MASK = 0x7;
1515
1516const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType] = {
1517 [RV32] = (1ULL << 31),
1518 [RV64] = (1ULL << 63),
1519};
1520
1521const std::unordered_map<int, RegVal>
1522CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1523 [RV32] = {
1524 [enums::M] = {
1525 {CSR_USTATUS, USTATUS_MASKS[RV32][enums::M]},
1526 {CSR_UIE, UI_MASK[enums::M]},
1527 {CSR_UIP, UI_MASK[enums::M]},
1529 {CSR_FRM, FRM_MASK},
1531 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::M]},
1532 {CSR_SIE, SI_MASK[enums::M]},
1533 {CSR_SIP, SI_MASK[enums::M]},
1534 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::M]},
1536 {CSR_MIE, MI_MASK[enums::M]},
1537 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::M]},
1538 {CSR_MIP, MI_MASK[enums::M]},
1539 },
1540 [enums::MU] = {
1541 {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MU]},
1542 {CSR_UIE, UI_MASK[enums::MU]},
1543 {CSR_UIP, UI_MASK[enums::MU]},
1545 {CSR_FRM, FRM_MASK},
1547 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MU]},
1548 {CSR_SIE, SI_MASK[enums::MU]},
1549 {CSR_SIP, SI_MASK[enums::MU]},
1550 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MU]},
1552 {CSR_MIE, MI_MASK[enums::MU]},
1553 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MU]},
1554 {CSR_MIP, MI_MASK[enums::MU]},
1555 },
1556 [enums::MNU] = {
1557 {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MNU]},
1558 {CSR_UIE, UI_MASK[enums::MNU]},
1559 {CSR_UIP, UI_MASK[enums::MNU]},
1561 {CSR_FRM, FRM_MASK},
1563 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MNU]},
1564 {CSR_SIE, SI_MASK[enums::MNU]},
1565 {CSR_SIP, SI_MASK[enums::MNU]},
1566 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MNU]},
1568 {CSR_MIE, MI_MASK[enums::MNU]},
1569 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MNU]},
1570 {CSR_MIP, MI_MASK[enums::MNU]},
1571 },
1572 [enums::MSU] = {
1573 {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MSU]},
1574 {CSR_UIE, UI_MASK[enums::MSU]},
1575 {CSR_UIP, UI_MASK[enums::MSU]},
1577 {CSR_FRM, FRM_MASK},
1579 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MSU]},
1580 {CSR_SIE, SI_MASK[enums::MSU]},
1581 {CSR_SIP, SI_MASK[enums::MSU]},
1582 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MSU]},
1584 {CSR_MIE, MI_MASK[enums::MSU]},
1585 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MSU]},
1586 {CSR_MIP, MI_MASK[enums::MSU]},
1587 },
1588 [enums::MNSU] = {
1589 {CSR_USTATUS, USTATUS_MASKS[RV32][enums::MNSU]},
1590 {CSR_UIE, UI_MASK[enums::MNSU]},
1591 {CSR_UIP, UI_MASK[enums::MNSU]},
1593 {CSR_FRM, FRM_MASK},
1595 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MNSU]},
1596 {CSR_SIE, SI_MASK[enums::MNSU]},
1597 {CSR_SIP, SI_MASK[enums::MNSU]},
1598 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MNSU]},
1600 {CSR_MIE, MI_MASK[enums::MNSU]},
1601 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MNSU]},
1602 {CSR_MIP, MI_MASK[enums::MNSU]},
1603 },
1604 },
1605 [RV64] = {
1606 [enums::M] = {
1607 {CSR_USTATUS, USTATUS_MASKS[RV64][enums::M]},
1608 {CSR_UIE, UI_MASK[enums::M]},
1609 {CSR_UIP, UI_MASK[enums::M]},
1611 {CSR_FRM, FRM_MASK},
1613 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::M]},
1614 {CSR_SIE, SI_MASK[enums::M]},
1615 {CSR_SIP, SI_MASK[enums::M]},
1616 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::M]},
1618 {CSR_MIE, MI_MASK[enums::M]},
1619 {CSR_MIP, MI_MASK[enums::M]},
1620 },
1621 [enums::MU] = {
1622 {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MU]},
1623 {CSR_UIE, UI_MASK[enums::MU]},
1624 {CSR_UIP, UI_MASK[enums::MU]},
1626 {CSR_FRM, FRM_MASK},
1628 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MU]},
1629 {CSR_SIE, SI_MASK[enums::MU]},
1630 {CSR_SIP, SI_MASK[enums::MU]},
1631 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MU]},
1633 {CSR_MIE, MI_MASK[enums::MU]},
1634 {CSR_MIP, MI_MASK[enums::MU]},
1635 },
1636 [enums::MNU] = {
1637 {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MNU]},
1638 {CSR_UIE, UI_MASK[enums::MNU]},
1639 {CSR_UIP, UI_MASK[enums::MNU]},
1641 {CSR_FRM, FRM_MASK},
1643 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MNU]},
1644 {CSR_SIE, SI_MASK[enums::MNU]},
1645 {CSR_SIP, SI_MASK[enums::MNU]},
1646 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MNU]},
1648 {CSR_MIE, MI_MASK[enums::MNU]},
1649 {CSR_MIP, MI_MASK[enums::MNU]},
1650 },
1651 [enums::MSU] = {
1652 {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MSU]},
1653 {CSR_UIE, UI_MASK[enums::MSU]},
1654 {CSR_UIP, UI_MASK[enums::MSU]},
1656 {CSR_FRM, FRM_MASK},
1658 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MSU]},
1659 {CSR_SIE, SI_MASK[enums::MSU]},
1660 {CSR_SIP, SI_MASK[enums::MSU]},
1661 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MSU]},
1663 {CSR_MIE, MI_MASK[enums::MSU]},
1664 {CSR_MIP, MI_MASK[enums::MSU]},
1665 },
1666 [enums::MNSU] = {
1667 {CSR_USTATUS, USTATUS_MASKS[RV64][enums::MNSU]},
1668 {CSR_UIE, UI_MASK[enums::MNSU]},
1669 {CSR_UIP, UI_MASK[enums::MNSU]},
1671 {CSR_FRM, FRM_MASK},
1673 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MNSU]},
1674 {CSR_SIE, SI_MASK[enums::MNSU]},
1675 {CSR_SIP, SI_MASK[enums::MNSU]},
1676 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MNSU]},
1678 {CSR_MIE, MI_MASK[enums::MNSU]},
1679 {CSR_MIP, MI_MASK[enums::MNSU]},
1680 },
1681 },
1682};
1683
1684} // namespace RiscvISA
1685} // namespace gem5
1686
1687#endif // __ARCH_RISCV_REGS_MISC_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
Definition bitunion.hh:494
#define EndBitUnion(name)
This closes off the class and union started by the above macro.
Definition bitunion.hh:428
constexpr RegClass miscRegClass
Definition misc.hh:2975
const RegVal STATUS_TSR_MASK
Definition misc.hh:1326
const RegVal UI_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1506
const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet]
Definition misc.hh:1410
Bitfield< 3 > rvd
Definition misc.hh:1243
const RegVal SI_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1497
Bitfield< 3 > msi
Definition misc.hh:1263
Bitfield< 0 > uie
Definition misc.hh:1215
Bitfield< 12, 11 > mpp
Definition misc.hh:1207
Bitfield< 21 > tw
Definition misc.hh:1200
constexpr uint64_t isaExtsFlags()
Definition misc.hh:534
@ CSR_MHPMEVENT19
Definition misc.hh:485
@ CSR_HPMCOUNTER18
Definition misc.hh:302
@ CSR_HPMCOUNTER05H
Definition misc.hh:323
@ CSR_HPMCOUNTER11
Definition misc.hh:295
@ CSR_HPMCOUNTER03H
Definition misc.hh:321
@ CSR_HPMCOUNTER05
Definition misc.hh:289
@ CSR_MHPMCOUNTER25H
Definition misc.hh:460
@ CSR_MHPMEVENT27
Definition misc.hh:493
@ CSR_MHPMCOUNTER07H
Definition misc.hh:442
@ CSR_HPMCOUNTER23
Definition misc.hh:307
@ CSR_MHPMCOUNTER03H
Definition misc.hh:438
@ CSR_MHPMEVENT17
Definition misc.hh:483
@ CSR_HPMCOUNTER20H
Definition misc.hh:338
@ CSR_HPMCOUNTER17
Definition misc.hh:301
@ CSR_MHPMEVENT21
Definition misc.hh:487
@ CSR_MHPMCOUNTER07
Definition misc.hh:409
@ CSR_HPMCOUNTER16
Definition misc.hh:300
@ CSR_HPMCOUNTER15
Definition misc.hh:299
@ CSR_HPMCOUNTER06H
Definition misc.hh:324
@ CSR_HPMCOUNTER07
Definition misc.hh:291
@ CSR_HPMCOUNTER27
Definition misc.hh:311
@ CSR_HPMCOUNTER08
Definition misc.hh:292
@ CSR_MHPMCOUNTER21H
Definition misc.hh:456
@ CSR_HPMCOUNTER21
Definition misc.hh:305
@ CSR_HPMCOUNTER24
Definition misc.hh:308
@ CSR_MHPMCOUNTER29H
Definition misc.hh:464
@ CSR_MHPMCOUNTER12H
Definition misc.hh:447
@ CSR_MHPMEVENT22
Definition misc.hh:488
@ CSR_MHPMCOUNTER16
Definition misc.hh:418
@ CSR_MHPMEVENT06
Definition misc.hh:472
@ CSR_MHPMCOUNTER23
Definition misc.hh:425
@ CSR_MHPMEVENT05
Definition misc.hh:471
@ CSR_MHPMCOUNTER22
Definition misc.hh:424
@ CSR_MHPMCOUNTER10H
Definition misc.hh:445
@ CSR_MHPMEVENT13
Definition misc.hh:479
@ CSR_HPMCOUNTER29
Definition misc.hh:313
@ CSR_MHPMCOUNTER06
Definition misc.hh:408
@ CSR_HPMCOUNTER04
Definition misc.hh:288
@ CSR_MHPMCOUNTER05H
Definition misc.hh:440
@ CSR_HPMCOUNTER25
Definition misc.hh:309
@ CSR_MHPMEVENT20
Definition misc.hh:486
@ CSR_HPMCOUNTER10H
Definition misc.hh:328
@ CSR_HPMCOUNTER26
Definition misc.hh:310
@ CSR_HPMCOUNTER11H
Definition misc.hh:329
@ CSR_MHPMEVENT31
Definition misc.hh:497
@ CSR_HPMCOUNTER28
Definition misc.hh:312
@ CSR_MHPMCOUNTER29
Definition misc.hh:431
@ CSR_MHPMCOUNTER15
Definition misc.hh:417
@ CSR_MHPMEVENT14
Definition misc.hh:480
@ CSR_HPMCOUNTER10
Definition misc.hh:294
@ CSR_MHPMCOUNTER28
Definition misc.hh:430
@ CSR_MHPMCOUNTER09H
Definition misc.hh:444
@ CSR_HPMCOUNTER19H
Definition misc.hh:337
@ CSR_MHPMCOUNTER13H
Definition misc.hh:448
@ CSR_MHPMCOUNTER27
Definition misc.hh:429
@ CSR_MHPMCOUNTER16H
Definition misc.hh:451
@ CSR_MHPMCOUNTER03
Definition misc.hh:405
@ CSR_HPMCOUNTER04H
Definition misc.hh:322
@ CSR_MHPMEVENT07
Definition misc.hh:473
@ CSR_MHPMCOUNTER11
Definition misc.hh:413
@ CSR_MHPMCOUNTER26H
Definition misc.hh:461
@ CSR_HPMCOUNTER07H
Definition misc.hh:325
@ CSR_MHPMCOUNTER17H
Definition misc.hh:452
@ CSR_MHPMEVENT03
Definition misc.hh:469
@ CSR_HPMCOUNTER30
Definition misc.hh:314
@ CSR_HPMCOUNTER28H
Definition misc.hh:346
@ CSR_HPMCOUNTER25H
Definition misc.hh:343
@ CSR_HPMCOUNTER17H
Definition misc.hh:335
@ CSR_HPMCOUNTER29H
Definition misc.hh:347
@ CSR_MHPMEVENT08
Definition misc.hh:474
@ CSR_MHPMEVENT25
Definition misc.hh:491
@ CSR_MHPMCOUNTER22H
Definition misc.hh:457
@ CSR_HPMCOUNTER31H
Definition misc.hh:349
@ CSR_MHPMCOUNTER19
Definition misc.hh:421
@ CSR_MHPMCOUNTER05
Definition misc.hh:407
@ CSR_MHPMCOUNTER15H
Definition misc.hh:450
@ CSR_MHPMEVENT30
Definition misc.hh:496
@ CSR_MHPMCOUNTER10
Definition misc.hh:412
@ CSR_HPMCOUNTER16H
Definition misc.hh:334
@ CSR_HPMCOUNTER30H
Definition misc.hh:348
@ CSR_HPMCOUNTER22
Definition misc.hh:306
@ CSR_MHPMEVENT16
Definition misc.hh:482
@ CSR_MHPMCOUNTER24H
Definition misc.hh:459
@ CSR_MHPMEVENT12
Definition misc.hh:478
@ CSR_HPMCOUNTER23H
Definition misc.hh:341
@ CSR_HPMCOUNTER20
Definition misc.hh:304
@ CSR_HPMCOUNTER14H
Definition misc.hh:332
@ CSR_HPMCOUNTER08H
Definition misc.hh:326
@ CSR_MHPMEVENT09
Definition misc.hh:475
@ CSR_HPMCOUNTER26H
Definition misc.hh:344
@ CSR_MHPMEVENT04
Definition misc.hh:470
@ CSR_MHPMCOUNTER18H
Definition misc.hh:453
@ CSR_MHPMEVENT29
Definition misc.hh:495
@ CSR_MHPMCOUNTER06H
Definition misc.hh:441
@ CSR_HPMCOUNTER27H
Definition misc.hh:345
@ CSR_HPMCOUNTER18H
Definition misc.hh:336
@ CSR_MHPMCOUNTER25
Definition misc.hh:427
@ CSR_MHPMCOUNTER23H
Definition misc.hh:458
@ CSR_MHPMEVENT15
Definition misc.hh:481
@ CSR_MHPMEVENT11
Definition misc.hh:477
@ CSR_HPMCOUNTER09H
Definition misc.hh:327
@ CSR_MHPMCOUNTER13
Definition misc.hh:415
@ CSR_HPMCOUNTER15H
Definition misc.hh:333
@ CSR_MHPMEVENT10
Definition misc.hh:476
@ CSR_MHPMCOUNTER11H
Definition misc.hh:446
@ CSR_MHPMEVENT18
Definition misc.hh:484
@ CSR_HPMCOUNTER06
Definition misc.hh:290
@ CSR_MHPMEVENT23
Definition misc.hh:489
@ CSR_MHPMEVENT26
Definition misc.hh:492
@ CSR_MHPMCOUNTER09
Definition misc.hh:411
@ CSR_MHPMCOUNTER24
Definition misc.hh:426
@ CSR_MHPMCOUNTER26
Definition misc.hh:428
@ CSR_HPMCOUNTER21H
Definition misc.hh:339
@ CSR_MHPMCOUNTER04H
Definition misc.hh:439
@ CSR_MHPMCOUNTER30H
Definition misc.hh:465
@ CSR_HPMCOUNTER22H
Definition misc.hh:340
@ CSR_MHPMCOUNTER17
Definition misc.hh:419
@ CSR_MHPMCOUNTER14H
Definition misc.hh:449
@ CSR_MHPMCOUNTER31H
Definition misc.hh:466
@ CSR_HPMCOUNTER13
Definition misc.hh:297
@ CSR_MHPMCOUNTER20
Definition misc.hh:422
@ CSR_MHPMCOUNTER20H
Definition misc.hh:455
@ CSR_HPMCOUNTER12
Definition misc.hh:296
@ CSR_MHPMCOUNTER21
Definition misc.hh:423
@ CSR_MHPMEVENT28
Definition misc.hh:494
@ CSR_HPMCOUNTER14
Definition misc.hh:298
@ CSR_MHPMCOUNTER31
Definition misc.hh:433
@ CSR_HPMCOUNTER31
Definition misc.hh:315
@ CSR_HPMCOUNTER13H
Definition misc.hh:331
@ CSR_MHPMCOUNTER28H
Definition misc.hh:463
@ CSR_MHPMCOUNTER14
Definition misc.hh:416
@ CSR_MHPMCOUNTER19H
Definition misc.hh:454
@ CSR_HPMCOUNTER12H
Definition misc.hh:330
@ CSR_HPMCOUNTER09
Definition misc.hh:293
@ CSR_HPMCOUNTER19
Definition misc.hh:303
@ CSR_HPMCOUNTER03
Definition misc.hh:287
@ CSR_MHPMCOUNTER18
Definition misc.hh:420
@ CSR_MHPMCOUNTER27H
Definition misc.hh:462
@ CSR_MHPMCOUNTER08H
Definition misc.hh:443
@ CSR_MHPMCOUNTER12
Definition misc.hh:414
@ CSR_MHPMCOUNTER30
Definition misc.hh:432
@ CSR_MHPMCOUNTER04
Definition misc.hh:406
@ CSR_MHPMEVENT24
Definition misc.hh:490
@ CSR_HPMCOUNTER24H
Definition misc.hh:342
@ CSR_MHPMCOUNTER08
Definition misc.hh:410
Bitfield< 1 > ssi
Definition misc.hh:1264
Bitfield< 35, 34 > sxl
Definition misc.hh:1196
Bitfield< 33, 32 > pmm
Definition misc.hh:1273
constexpr enums::RiscvType RV32
Definition pcstate.hh:56
const RegVal FRM_MASK
Definition misc.hh:1514
Bitfield< 8 > rvi
Definition misc.hh:1238
Bitfield< 21 > rvv
Definition misc.hh:1227
const RegVal STATUS_MBE_MASK[enums::Num_RiscvType]
Definition misc.hh:1316
const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType]
Definition misc.hh:1516
Bitfield< 6 > rvg
Definition misc.hh:1240
Bitfield< 0 > usi
Definition misc.hh:1265
Bitfield< 20 > rvu
Definition misc.hh:1228
Bitfield< 18 > sum
Definition misc.hh:1203
Bitfield< 8 > spp
Definition misc.hh:1209
Bitfield< 11 > mei
Definition misc.hh:1257
const RegVal STATUS_SBE_MASK[enums::Num_RiscvType]
Definition misc.hh:1320
Bitfield< 7 > rvh
Definition misc.hh:1239
Bitfield< 4 > uti
Definition misc.hh:1262
Bitfield< 0 > fiom
Definition misc.hh:1279
const RegVal MEI_MASK
Definition misc.hh:1477
Bitfield< 8 > uei
Definition misc.hh:1259
Bitfield< 4 > upie
Definition misc.hh:1212
Bitfield< 17 > mprv
Definition misc.hh:1204
const RegVal SEI_MASK
Definition misc.hh:1478
Bitfield< 23 > rvx
Definition misc.hh:1226
const RegVal SSI_MASK
Definition misc.hh:1484
const off_t UXL_OFFSET
Definition misc.hh:1295
Bitfield< 5 > sti
Definition misc.hh:1261
Bitfield< 1 > sie
Definition misc.hh:1214
Bitfield< 3, 1 > wpri_3
Definition misc.hh:1278
const RegVal UTI_MASK
Definition misc.hh:1482
Bitfield< 18 > rvs
Definition misc.hh:1230
const off_t SXL_OFFSET
Definition misc.hh:1294
const RegVal STATUS_MIE_MASK
Definition misc.hh:1340
Bitfield< 31 > rv32_sd
Definition misc.hh:1198
const RegVal STATUS_SIE_MASK
Definition misc.hh:1341
const off_t FS_OFFSET
Definition misc.hh:1296
const RegVal STATUS_TW_MASK
Definition misc.hh:1327
const RegVal STATUS_MPIE_MASK
Definition misc.hh:1337
Bitfield< 14, 13 > fs
Definition misc.hh:1206
Bitfield< 12 > rvm
Definition misc.hh:1234
const RegVal SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1418
const RegVal STATUS_VS_MASK
Definition misc.hh:1335
const off_t VS_OFFSET
Definition misc.hh:1297
const RegVal MTI_MASK
Definition misc.hh:1480
const off_t MBE_OFFSET[enums::Num_RiscvType]
Definition misc.hh:1286
Bitfield< 20 > tvm
Definition misc.hh:1201
const RegVal STATUS_XS_MASK
Definition misc.hh:1332
const RegVal STATUS_SXL_MASK
Definition misc.hh:1324
const RegVal FFLAGS_MASK
Definition misc.hh:1513
Bitfield< 7 > mti
Definition misc.hh:1260
Bitfield< 0 > rva
Definition misc.hh:1246
Bitfield< 16 > rvq
Definition misc.hh:1231
const RegVal STATUS_MPRV_MASK
Definition misc.hh:1331
Bitfield< 33, 32 > uxl
Definition misc.hh:1197
Bitfield< 15 > rvp
Definition misc.hh:1232
const RegVal MSI_MASK
Definition misc.hh:1483
Bitfield< 5 > spie
Definition misc.hh:1211
Bitfield< 3 > mie
Definition misc.hh:1213
Bitfield< 7 > mpie
Definition misc.hh:1210
const RegVal STATUS_UXL_MASK
Definition misc.hh:1325
const RegVal USI_MASK
Definition misc.hh:1485
const RegVal STATUS_MXR_MASK
Definition misc.hh:1329
const RegVal USTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1449
const std::unordered_map< int, CSRMetadata > CSRData
Definition misc.hh:538
Bitfield< 22 > tsr
Definition misc.hh:1199
const std::unordered_map< int, RegVal > CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1522
const RegVal LOCAL_MASK
Definition misc.hh:1476
Bitfield< 6 > cbcfe
Definition misc.hh:1276
const RegVal UEI_MASK
Definition misc.hh:1479
const RegVal STATUS_FS_MASK
Definition misc.hh:1333
const RegVal STATUS_SPP_MASK
Definition misc.hh:1336
const RegVal ISA_EXT_MASK
Definition misc.hh:1304
Bitfield< 5, 4 > cbie
Definition misc.hh:1277
const RegVal STATUS_SD_MASKS[enums::Num_RiscvType]
Definition misc.hh:1312
const RegVal STATUS_SPIE_MASK
Definition misc.hh:1338
const RegVal STATUS_MPP_MASK
Definition misc.hh:1334
const RegVal STATUS_UIE_MASK
Definition misc.hh:1342
Bitfield< 13 > rvn
Definition misc.hh:1233
Bitfield< 4 > rve
Definition misc.hh:1242
constexpr enums::RiscvType RV64
Definition pcstate.hh:57
const RegVal ISA_EXT_C_MASK
Definition misc.hh:1305
Bitfield< 1 > rvb
Definition misc.hh:1245
@ MISCREG_PMPADDR11
Definition misc.hh:171
@ MISCREG_HPMCOUNTER16H
Definition misc.hh:233
@ MISCREG_USTATUS
Definition misc.hh:258
@ MISCREG_HPMCOUNTER09
Definition misc.hh:88
@ MISCREG_HPMEVENT31
Definition misc.hh:139
@ MISCREG_IMPID
Definition misc.hh:74
@ MISCREG_HPMEVENT07
Definition misc.hh:115
@ MISCREG_HPMCOUNTER16
Definition misc.hh:95
@ MISCREG_HPMCOUNTER13H
Definition misc.hh:230
@ MISCREG_SENVCFG
Definition misc.hh:186
@ MISCREG_HPMCOUNTER19
Definition misc.hh:98
@ MISCREG_PMPADDR12
Definition misc.hh:172
@ MISCREG_HPMCOUNTER07
Definition misc.hh:86
@ MISCREG_HPMEVENT29
Definition misc.hh:137
@ MISCREG_HPMCOUNTER26
Definition misc.hh:105
@ MISCREG_PMPADDR05
Definition misc.hh:165
@ MISCREG_HPMCOUNTER13
Definition misc.hh:92
@ MISCREG_PMPADDR10
Definition misc.hh:170
@ MISCREG_SIDELEG
Definition misc.hh:178
@ MISCREG_PMPADDR14
Definition misc.hh:174
@ MISCREG_PMPCFG3
Definition misc.hh:159
@ NUM_PHYS_MISCREGS
Definition misc.hh:250
@ MISCREG_HPMCOUNTER22H
Definition misc.hh:239
@ MISCREG_PMPADDR09
Definition misc.hh:169
@ MISCREG_HPMEVENT06
Definition misc.hh:114
@ MISCREG_TSELECT
Definition misc.hh:140
@ MISCREG_MSCRATCH
Definition misc.hh:152
@ MISCREG_HPMCOUNTER04H
Definition misc.hh:221
@ MISCREG_HPMEVENT21
Definition misc.hh:129
@ MISCREG_HPMCOUNTER12H
Definition misc.hh:229
@ MISCREG_STATUS
Definition misc.hh:76
@ MISCREG_HPMEVENT12
Definition misc.hh:120
@ MISCREG_HPMCOUNTER25
Definition misc.hh:104
@ MISCREG_PMPADDR04
Definition misc.hh:164
@ MISCREG_INSTRETH
Definition misc.hh:219
@ MISCREG_MCOUNTEREN
Definition misc.hh:151
@ MISCREG_PMPADDR00
Definition misc.hh:160
@ MISCREG_HPMCOUNTER22
Definition misc.hh:101
@ MISCREG_HPMEVENT17
Definition misc.hh:125
@ MISCREG_HPMEVENT20
Definition misc.hh:128
@ MISCREG_HPMCOUNTER03H
Definition misc.hh:220
@ MISCREG_HPMCOUNTER15H
Definition misc.hh:232
@ MISCREG_MEDELEG
Definition misc.hh:148
@ MISCREG_USCRATCH
Definition misc.hh:189
@ MISCREG_HPMEVENT25
Definition misc.hh:133
@ MISCREG_HPMCOUNTER31H
Definition misc.hh:248
@ MISCREG_HPMCOUNTER11
Definition misc.hh:90
@ MISCREG_HPMCOUNTER17H
Definition misc.hh:234
@ MISCREG_HPMEVENT03
Definition misc.hh:111
@ MISCREG_PMPCFG1
Definition misc.hh:157
@ MISCREG_SSTATUS
Definition misc.hh:261
@ MISCREG_HPMEVENT13
Definition misc.hh:121
@ MISCREG_PMPADDR13
Definition misc.hh:173
@ MISCREG_FFLAGS_EXE
Definition misc.hh:256
@ MISCREG_HPMCOUNTER12
Definition misc.hh:91
@ MISCREG_HPMCOUNTER29H
Definition misc.hh:246
@ MISCREG_HPMEVENT04
Definition misc.hh:112
@ MISCREG_HPMEVENT08
Definition misc.hh:116
@ MISCREG_HPMEVENT19
Definition misc.hh:127
@ MISCREG_DSCRATCH
Definition misc.hh:146
@ MISCREG_HPMEVENT30
Definition misc.hh:138
@ MISCREG_SEDELEG
Definition misc.hh:177
@ MISCREG_PMPADDR06
Definition misc.hh:166
@ MISCREG_HPMCOUNTER21
Definition misc.hh:100
@ MISCREG_HPMCOUNTER21H
Definition misc.hh:238
@ MISCREG_PMPADDR03
Definition misc.hh:163
@ MISCREG_SCOUNTEREN
Definition misc.hh:180
@ MISCREG_HPMCOUNTER18H
Definition misc.hh:235
@ MISCREG_HPMCOUNTER06
Definition misc.hh:85
@ MISCREG_HPMCOUNTER20H
Definition misc.hh:237
@ MISCREG_HPMCOUNTER28
Definition misc.hh:107
@ MISCREG_PMPADDR02
Definition misc.hh:162
@ MISCREG_MIDELEG
Definition misc.hh:149
@ MISCREG_HPMCOUNTER30
Definition misc.hh:109
@ MISCREG_HPMCOUNTER14
Definition misc.hh:93
@ MISCREG_MSTATUSH
Definition misc.hh:215
@ MISCREG_HPMEVENT10
Definition misc.hh:118
@ MISCREG_HPMEVENT26
Definition misc.hh:134
@ MISCREG_HPMEVENT18
Definition misc.hh:126
@ MISCREG_HPMEVENT23
Definition misc.hh:131
@ MISCREG_INSTRET
Definition misc.hh:81
@ MISCREG_HARTID
Definition misc.hh:75
@ MISCREG_HPMCOUNTER05H
Definition misc.hh:222
@ MISCREG_HPMCOUNTER20
Definition misc.hh:99
@ MISCREG_HPMEVENT09
Definition misc.hh:117
@ MISCREG_HPMCOUNTER04
Definition misc.hh:83
@ MISCREG_HPMCOUNTER25H
Definition misc.hh:242
@ MISCREG_HPMCOUNTER27H
Definition misc.hh:244
@ MISCREG_HPMCOUNTER06H
Definition misc.hh:223
@ MISCREG_PMPADDR07
Definition misc.hh:167
@ MISCREG_HPMCOUNTER08H
Definition misc.hh:225
@ MISCREG_HPMEVENT16
Definition misc.hh:124
@ MISCREG_HPMCOUNTER18
Definition misc.hh:97
@ MISCREG_SSCRATCH
Definition misc.hh:181
@ MISCREG_HPMCOUNTER19H
Definition misc.hh:236
@ MISCREG_HPMEVENT14
Definition misc.hh:122
@ MISCREG_HPMCOUNTER10H
Definition misc.hh:227
@ MISCREG_HPMCOUNTER05
Definition misc.hh:84
@ MISCREG_HPMCOUNTER30H
Definition misc.hh:247
@ MISCREG_HPMCOUNTER17
Definition misc.hh:96
@ MISCREG_HPMCOUNTER09H
Definition misc.hh:226
@ MISCREG_HPMCOUNTER27
Definition misc.hh:106
@ MISCREG_HPMCOUNTER24
Definition misc.hh:103
@ MISCREG_HPMCOUNTER28H
Definition misc.hh:245
@ MISCREG_HPMCOUNTER14H
Definition misc.hh:231
@ MISCREG_HPMCOUNTER23
Definition misc.hh:102
@ MISCREG_CYCLE
Definition misc.hh:79
@ MISCREG_HPMCOUNTER07H
Definition misc.hh:224
@ MISCREG_HPMCOUNTER15
Definition misc.hh:94
@ MISCREG_HPMEVENT24
Definition misc.hh:132
@ MISCREG_HPMCOUNTER10
Definition misc.hh:89
@ MISCREG_HPMCOUNTER29
Definition misc.hh:108
@ MISCREG_VENDORID
Definition misc.hh:72
@ MISCREG_PMPADDR01
Definition misc.hh:161
@ MISCREG_HPMEVENT27
Definition misc.hh:135
@ MISCREG_HPMEVENT15
Definition misc.hh:123
@ MISCREG_HPMEVENT05
Definition misc.hh:113
@ MISCREG_ARCHID
Definition misc.hh:73
@ MISCREG_HPMCOUNTER24H
Definition misc.hh:241
@ MISCREG_MSTATUS
Definition misc.hh:252
@ MISCREG_HPMEVENT11
Definition misc.hh:119
@ MISCREG_HPMCOUNTER31
Definition misc.hh:110
@ MISCREG_HPMCOUNTER23H
Definition misc.hh:240
@ MISCREG_HPMCOUNTER11H
Definition misc.hh:228
@ MISCREG_PMPADDR08
Definition misc.hh:168
@ MISCREG_HPMCOUNTER03
Definition misc.hh:82
@ MISCREG_PMPADDR15
Definition misc.hh:175
@ MISCREG_HPMEVENT28
Definition misc.hh:136
@ MISCREG_HPMEVENT22
Definition misc.hh:130
@ MISCREG_PMPCFG0
Definition misc.hh:156
@ MISCREG_HPMCOUNTER08
Definition misc.hh:87
@ MISCREG_HPMCOUNTER26H
Definition misc.hh:243
@ MISCREG_PMPCFG2
Definition misc.hh:158
const RegVal MISA_MASKS[enums::Num_RiscvType]
Definition misc.hh:1306
Bitfield< 10 > rvk
Definition misc.hh:1236
Bitfield< 19 > rvt
Definition misc.hh:1229
const off_t FRM_OFFSET
Definition misc.hh:1298
Bitfield< 9, 5 > vs
Bitfield< 16, 15 > xs
Definition misc.hh:1205
const RegVal ISA_MXL_MASKS[enums::Num_RiscvType]
Definition misc.hh:1300
Bitfield< 31, 8 > wpri_2
Definition misc.hh:1274
const RegVal STI_MASK
Definition misc.hh:1481
const RegVal MI_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1486
const RegVal STATUS_SUM_MASK
Definition misc.hh:1330
Bitfield< 5 > rvf
Definition misc.hh:1241
Bitfield< 9 > rvj
Definition misc.hh:1237
Bitfield< 31, 30 > rv32_mxl
Definition misc.hh:1225
Bitfield< 2 > rvc
Definition misc.hh:1244
Bitfield< 11 > rvl
Definition misc.hh:1235
const off_t SBE_OFFSET[enums::Num_RiscvType]
Definition misc.hh:1290
Bitfield< 7 > cbze
Definition misc.hh:1275
Bitfield< 19 > mxr
Definition misc.hh:1202
const RegVal STATUS_UPIE_MASK
Definition misc.hh:1339
constexpr uint64_t rvTypeFlags(T... args)
Definition misc.hh:525
Bitfield< 9 > sei
Definition misc.hh:1258
const RegVal STATUS_TVM_MASK
Definition misc.hh:1328
const RegVal MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1344
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
constexpr char MiscRegClassName[]
Definition reg_class.hh:82
uint64_t RegVal
Definition types.hh:173
@ MiscRegClass
Control (misc) register.
Definition reg_class.hh:70
const uint64_t rvTypes
Definition misc.hh:520
const uint64_t isaExts
Definition misc.hh:521
const std::string name
Definition misc.hh:518
Vector Registers layout specification.

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