gem5  v21.1.0.2
misc.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013 ARM Limited
3  * Copyright (c) 2014-2015 Sven Karlsson
4  * Copyright (c) 2019 Yifei Liu
5  * Copyright (c) 2020 Barkhausen Institut
6  * Copyright (c) 2021 StreamComputing Corp
7  * All rights reserved
8  *
9  * The license below extends only to copyright in the software and shall
10  * not be construed as granting a license to any other intellectual
11  * property including but not limited to intellectual property relating
12  * to a hardware implementation of the functionality of the software
13  * licensed hereunder. You may use the software subject to the license
14  * terms below provided that you ensure that this notice is replicated
15  * unmodified and in its entirety in all distributions of the software,
16  * modified or unmodified, in source code or in binary form.
17  *
18  * Copyright (c) 2016 RISC-V Foundation
19  * Copyright (c) 2016 The University of Virginia
20  * All rights reserved.
21  *
22  * Redistribution and use in source and binary forms, with or without
23  * modification, are permitted provided that the following conditions are
24  * met: redistributions of source code must retain the above copyright
25  * notice, this list of conditions and the following disclaimer;
26  * redistributions in binary form must reproduce the above copyright
27  * notice, this list of conditions and the following disclaimer in the
28  * documentation and/or other materials provided with the distribution;
29  * neither the name of the copyright holders nor the names of its
30  * contributors may be used to endorse or promote products derived from
31  * this software without specific prior written permission.
32  *
33  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44  */
45 
46 #ifndef __ARCH_RISCV_REGS_MISC_HH__
47 #define __ARCH_RISCV_REGS_MISC_HH__
48 
49 #include <map>
50 #include <string>
51 
53 #include "arch/generic/vec_reg.hh"
54 #include "base/bitunion.hh"
55 #include "base/types.hh"
56 
57 namespace gem5
58 {
59 
60 namespace RiscvISA
61 {
62 
64 {
142 
152  // pmpcfg1 rv32 only
154  // pmpcfg3 rv32 only
171 
181 
189 
191 };
192 
194 {
195  CSR_USTATUS = 0x000,
196  CSR_UIE = 0x004,
197  CSR_UTVEC = 0x005,
198  CSR_USCRATCH = 0x040,
199  CSR_UEPC = 0x041,
200  CSR_UCAUSE = 0x042,
201  CSR_UTVAL = 0x043,
202  CSR_UIP = 0x044,
203  CSR_FFLAGS = 0x001,
204  CSR_FRM = 0x002,
205  CSR_FCSR = 0x003,
206  CSR_CYCLE = 0xC00,
207  CSR_TIME = 0xC01,
208  CSR_INSTRET = 0xC02,
238  // HPMCOUNTERH rv32 only
239 
240  CSR_SSTATUS = 0x100,
241  CSR_SEDELEG = 0x102,
242  CSR_SIDELEG = 0x103,
243  CSR_SIE = 0x104,
244  CSR_STVEC = 0x105,
245  CSR_SCOUNTEREN = 0x106,
246  CSR_SSCRATCH = 0x140,
247  CSR_SEPC = 0x141,
248  CSR_SCAUSE = 0x142,
249  CSR_STVAL = 0x143,
250  CSR_SIP = 0x144,
251  CSR_SATP = 0x180,
252 
253  CSR_MVENDORID = 0xF11,
254  CSR_MARCHID = 0xF12,
255  CSR_MIMPID = 0xF13,
256  CSR_MHARTID = 0xF14,
257  CSR_MSTATUS = 0x300,
258  CSR_MISA = 0x301,
259  CSR_MEDELEG = 0x302,
260  CSR_MIDELEG = 0x303,
261  CSR_MIE = 0x304,
262  CSR_MTVEC = 0x305,
263  CSR_MCOUNTEREN = 0x306,
264  CSR_MSCRATCH = 0x340,
265  CSR_MEPC = 0x341,
266  CSR_MCAUSE = 0x342,
267  CSR_MTVAL = 0x343,
268  CSR_MIP = 0x344,
269  CSR_PMPCFG0 = 0x3A0,
270  // pmpcfg1 rv32 only
271  CSR_PMPCFG2 = 0x3A2,
272  // pmpcfg3 rv32 only
273  CSR_PMPADDR00 = 0x3B0,
274  CSR_PMPADDR01 = 0x3B1,
275  CSR_PMPADDR02 = 0x3B2,
276  CSR_PMPADDR03 = 0x3B3,
277  CSR_PMPADDR04 = 0x3B4,
278  CSR_PMPADDR05 = 0x3B5,
279  CSR_PMPADDR06 = 0x3B6,
280  CSR_PMPADDR07 = 0x3B7,
281  CSR_PMPADDR08 = 0x3B8,
282  CSR_PMPADDR09 = 0x3B9,
283  CSR_PMPADDR10 = 0x3BA,
284  CSR_PMPADDR11 = 0x3BB,
285  CSR_PMPADDR12 = 0x3BC,
286  CSR_PMPADDR13 = 0x3BD,
287  CSR_PMPADDR14 = 0x3BE,
288  CSR_PMPADDR15 = 0x3BF,
289  CSR_MCYCLE = 0xB00,
290  CSR_MINSTRET = 0xB02,
320  // MHPMCOUNTERH rv32 only
350 
351  CSR_TSELECT = 0x7A0,
352  CSR_TDATA1 = 0x7A1,
353  CSR_TDATA2 = 0x7A2,
354  CSR_TDATA3 = 0x7A3,
355  CSR_DCSR = 0x7B0,
356  CSR_DPC = 0x7B1,
357  CSR_DSCRATCH = 0x7B2
358 };
359 
361 {
362  const std::string name;
363  const int physIndex;
364 };
365 
366 const std::map<int, CSRMetadata> CSRData = {
367  {CSR_USTATUS, {"ustatus", MISCREG_STATUS}},
368  {CSR_UIE, {"uie", MISCREG_IE}},
369  {CSR_UTVEC, {"utvec", MISCREG_UTVEC}},
370  {CSR_USCRATCH, {"uscratch", MISCREG_USCRATCH}},
371  {CSR_UEPC, {"uepc", MISCREG_UEPC}},
372  {CSR_UCAUSE, {"ucause", MISCREG_UCAUSE}},
373  {CSR_UTVAL, {"utval", MISCREG_UTVAL}},
374  {CSR_UIP, {"uip", MISCREG_IP}},
375  {CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
376  {CSR_FRM, {"frm", MISCREG_FRM}},
377  {CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
378  {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
379  {CSR_TIME, {"time", MISCREG_TIME}},
380  {CSR_INSTRET, {"instret", MISCREG_INSTRET}},
381  {CSR_HPMCOUNTER03, {"hpmcounter03", MISCREG_HPMCOUNTER03}},
382  {CSR_HPMCOUNTER04, {"hpmcounter04", MISCREG_HPMCOUNTER04}},
383  {CSR_HPMCOUNTER05, {"hpmcounter05", MISCREG_HPMCOUNTER05}},
384  {CSR_HPMCOUNTER06, {"hpmcounter06", MISCREG_HPMCOUNTER06}},
385  {CSR_HPMCOUNTER07, {"hpmcounter07", MISCREG_HPMCOUNTER07}},
386  {CSR_HPMCOUNTER08, {"hpmcounter08", MISCREG_HPMCOUNTER08}},
387  {CSR_HPMCOUNTER09, {"hpmcounter09", MISCREG_HPMCOUNTER09}},
388  {CSR_HPMCOUNTER10, {"hpmcounter10", MISCREG_HPMCOUNTER10}},
389  {CSR_HPMCOUNTER11, {"hpmcounter11", MISCREG_HPMCOUNTER11}},
390  {CSR_HPMCOUNTER12, {"hpmcounter12", MISCREG_HPMCOUNTER12}},
391  {CSR_HPMCOUNTER13, {"hpmcounter13", MISCREG_HPMCOUNTER13}},
392  {CSR_HPMCOUNTER14, {"hpmcounter14", MISCREG_HPMCOUNTER14}},
393  {CSR_HPMCOUNTER15, {"hpmcounter15", MISCREG_HPMCOUNTER15}},
394  {CSR_HPMCOUNTER16, {"hpmcounter16", MISCREG_HPMCOUNTER16}},
395  {CSR_HPMCOUNTER17, {"hpmcounter17", MISCREG_HPMCOUNTER17}},
396  {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
397  {CSR_HPMCOUNTER19, {"hpmcounter19", MISCREG_HPMCOUNTER19}},
398  {CSR_HPMCOUNTER20, {"hpmcounter20", MISCREG_HPMCOUNTER20}},
399  {CSR_HPMCOUNTER21, {"hpmcounter21", MISCREG_HPMCOUNTER21}},
400  {CSR_HPMCOUNTER22, {"hpmcounter22", MISCREG_HPMCOUNTER22}},
401  {CSR_HPMCOUNTER23, {"hpmcounter23", MISCREG_HPMCOUNTER23}},
402  {CSR_HPMCOUNTER24, {"hpmcounter24", MISCREG_HPMCOUNTER24}},
403  {CSR_HPMCOUNTER25, {"hpmcounter25", MISCREG_HPMCOUNTER25}},
404  {CSR_HPMCOUNTER26, {"hpmcounter26", MISCREG_HPMCOUNTER26}},
405  {CSR_HPMCOUNTER27, {"hpmcounter27", MISCREG_HPMCOUNTER27}},
406  {CSR_HPMCOUNTER28, {"hpmcounter28", MISCREG_HPMCOUNTER28}},
407  {CSR_HPMCOUNTER29, {"hpmcounter29", MISCREG_HPMCOUNTER29}},
408  {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
409  {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
410 
411  {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
412  {CSR_SEDELEG, {"sedeleg", MISCREG_SEDELEG}},
413  {CSR_SIDELEG, {"sideleg", MISCREG_SIDELEG}},
414  {CSR_SIE, {"sie", MISCREG_IE}},
415  {CSR_STVEC, {"stvec", MISCREG_STVEC}},
416  {CSR_SCOUNTEREN, {"scounteren", MISCREG_SCOUNTEREN}},
417  {CSR_SSCRATCH, {"sscratch", MISCREG_SSCRATCH}},
418  {CSR_SEPC, {"sepc", MISCREG_SEPC}},
419  {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
420  {CSR_STVAL, {"stval", MISCREG_STVAL}},
421  {CSR_SIP, {"sip", MISCREG_IP}},
422  {CSR_SATP, {"satp", MISCREG_SATP}},
423 
424  {CSR_MVENDORID, {"mvendorid", MISCREG_VENDORID}},
425  {CSR_MARCHID, {"marchid", MISCREG_ARCHID}},
426  {CSR_MIMPID, {"mimpid", MISCREG_IMPID}},
427  {CSR_MHARTID, {"mhartid", MISCREG_HARTID}},
428  {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
429  {CSR_MISA, {"misa", MISCREG_ISA}},
430  {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
431  {CSR_MIDELEG, {"mideleg", MISCREG_MIDELEG}},
432  {CSR_MIE, {"mie", MISCREG_IE}},
433  {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
434  {CSR_MCOUNTEREN, {"mcounteren", MISCREG_MCOUNTEREN}},
435  {CSR_MSCRATCH, {"mscratch", MISCREG_MSCRATCH}},
436  {CSR_MEPC, {"mepc", MISCREG_MEPC}},
437  {CSR_MCAUSE, {"mcause", MISCREG_MCAUSE}},
438  {CSR_MTVAL, {"mtval", MISCREG_MTVAL}},
439  {CSR_MIP, {"mip", MISCREG_IP}},
440  {CSR_PMPCFG0, {"pmpcfg0", MISCREG_PMPCFG0}},
441  // pmpcfg1 rv32 only
442  {CSR_PMPCFG2, {"pmpcfg2", MISCREG_PMPCFG2}},
443  // pmpcfg3 rv32 only
444  {CSR_PMPADDR00, {"pmpaddr0", MISCREG_PMPADDR00}},
445  {CSR_PMPADDR01, {"pmpaddr1", MISCREG_PMPADDR01}},
446  {CSR_PMPADDR02, {"pmpaddr2", MISCREG_PMPADDR02}},
447  {CSR_PMPADDR03, {"pmpaddr3", MISCREG_PMPADDR03}},
448  {CSR_PMPADDR04, {"pmpaddr4", MISCREG_PMPADDR04}},
449  {CSR_PMPADDR05, {"pmpaddr5", MISCREG_PMPADDR05}},
450  {CSR_PMPADDR06, {"pmpaddr6", MISCREG_PMPADDR06}},
451  {CSR_PMPADDR07, {"pmpaddr7", MISCREG_PMPADDR07}},
452  {CSR_PMPADDR08, {"pmpaddr8", MISCREG_PMPADDR08}},
453  {CSR_PMPADDR09, {"pmpaddr9", MISCREG_PMPADDR09}},
454  {CSR_PMPADDR10, {"pmpaddr10", MISCREG_PMPADDR10}},
455  {CSR_PMPADDR11, {"pmpaddr11", MISCREG_PMPADDR11}},
456  {CSR_PMPADDR12, {"pmpaddr12", MISCREG_PMPADDR12}},
457  {CSR_PMPADDR13, {"pmpaddr13", MISCREG_PMPADDR13}},
458  {CSR_PMPADDR14, {"pmpaddr14", MISCREG_PMPADDR14}},
459  {CSR_PMPADDR15, {"pmpaddr15", MISCREG_PMPADDR15}},
460  {CSR_MCYCLE, {"mcycle", MISCREG_CYCLE}},
461  {CSR_MINSTRET, {"minstret", MISCREG_INSTRET}},
462  {CSR_MHPMCOUNTER03, {"mhpmcounter03", MISCREG_HPMCOUNTER03}},
463  {CSR_MHPMCOUNTER04, {"mhpmcounter04", MISCREG_HPMCOUNTER04}},
464  {CSR_MHPMCOUNTER05, {"mhpmcounter05", MISCREG_HPMCOUNTER05}},
465  {CSR_MHPMCOUNTER06, {"mhpmcounter06", MISCREG_HPMCOUNTER06}},
466  {CSR_MHPMCOUNTER07, {"mhpmcounter07", MISCREG_HPMCOUNTER07}},
467  {CSR_MHPMCOUNTER08, {"mhpmcounter08", MISCREG_HPMCOUNTER08}},
468  {CSR_MHPMCOUNTER09, {"mhpmcounter09", MISCREG_HPMCOUNTER09}},
469  {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
470  {CSR_MHPMCOUNTER11, {"mhpmcounter11", MISCREG_HPMCOUNTER11}},
471  {CSR_MHPMCOUNTER12, {"mhpmcounter12", MISCREG_HPMCOUNTER12}},
472  {CSR_MHPMCOUNTER13, {"mhpmcounter13", MISCREG_HPMCOUNTER13}},
473  {CSR_MHPMCOUNTER14, {"mhpmcounter14", MISCREG_HPMCOUNTER14}},
474  {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
475  {CSR_MHPMCOUNTER16, {"mhpmcounter16", MISCREG_HPMCOUNTER16}},
476  {CSR_MHPMCOUNTER17, {"mhpmcounter17", MISCREG_HPMCOUNTER17}},
477  {CSR_MHPMCOUNTER18, {"mhpmcounter18", MISCREG_HPMCOUNTER18}},
478  {CSR_MHPMCOUNTER19, {"mhpmcounter19", MISCREG_HPMCOUNTER19}},
479  {CSR_MHPMCOUNTER20, {"mhpmcounter20", MISCREG_HPMCOUNTER20}},
480  {CSR_MHPMCOUNTER21, {"mhpmcounter21", MISCREG_HPMCOUNTER21}},
481  {CSR_MHPMCOUNTER22, {"mhpmcounter22", MISCREG_HPMCOUNTER22}},
482  {CSR_MHPMCOUNTER23, {"mhpmcounter23", MISCREG_HPMCOUNTER23}},
483  {CSR_MHPMCOUNTER24, {"mhpmcounter24", MISCREG_HPMCOUNTER24}},
484  {CSR_MHPMCOUNTER25, {"mhpmcounter25", MISCREG_HPMCOUNTER25}},
485  {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
486  {CSR_MHPMCOUNTER27, {"mhpmcounter27", MISCREG_HPMCOUNTER27}},
487  {CSR_MHPMCOUNTER28, {"mhpmcounter28", MISCREG_HPMCOUNTER28}},
488  {CSR_MHPMCOUNTER29, {"mhpmcounter29", MISCREG_HPMCOUNTER29}},
489  {CSR_MHPMCOUNTER30, {"mhpmcounter30", MISCREG_HPMCOUNTER30}},
490  {CSR_MHPMCOUNTER31, {"mhpmcounter31", MISCREG_HPMCOUNTER31}},
491  {CSR_MHPMEVENT03, {"mhpmevent03", MISCREG_HPMEVENT03}},
492  {CSR_MHPMEVENT04, {"mhpmevent04", MISCREG_HPMEVENT04}},
493  {CSR_MHPMEVENT05, {"mhpmevent05", MISCREG_HPMEVENT05}},
494  {CSR_MHPMEVENT06, {"mhpmevent06", MISCREG_HPMEVENT06}},
495  {CSR_MHPMEVENT07, {"mhpmevent07", MISCREG_HPMEVENT07}},
496  {CSR_MHPMEVENT08, {"mhpmevent08", MISCREG_HPMEVENT08}},
497  {CSR_MHPMEVENT09, {"mhpmevent09", MISCREG_HPMEVENT09}},
498  {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
499  {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
500  {CSR_MHPMEVENT12, {"mhpmevent12", MISCREG_HPMEVENT12}},
501  {CSR_MHPMEVENT13, {"mhpmevent13", MISCREG_HPMEVENT13}},
502  {CSR_MHPMEVENT14, {"mhpmevent14", MISCREG_HPMEVENT14}},
503  {CSR_MHPMEVENT15, {"mhpmevent15", MISCREG_HPMEVENT15}},
504  {CSR_MHPMEVENT16, {"mhpmevent16", MISCREG_HPMEVENT16}},
505  {CSR_MHPMEVENT17, {"mhpmevent17", MISCREG_HPMEVENT17}},
506  {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
507  {CSR_MHPMEVENT19, {"mhpmevent19", MISCREG_HPMEVENT19}},
508  {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
509  {CSR_MHPMEVENT21, {"mhpmevent21", MISCREG_HPMEVENT21}},
510  {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
511  {CSR_MHPMEVENT23, {"mhpmevent23", MISCREG_HPMEVENT23}},
512  {CSR_MHPMEVENT24, {"mhpmevent24", MISCREG_HPMEVENT24}},
513  {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
514  {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
515  {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
516  {CSR_MHPMEVENT28, {"mhpmevent28", MISCREG_HPMEVENT28}},
517  {CSR_MHPMEVENT29, {"mhpmevent29", MISCREG_HPMEVENT29}},
518  {CSR_MHPMEVENT30, {"mhpmevent30", MISCREG_HPMEVENT30}},
519  {CSR_MHPMEVENT31, {"mhpmevent31", MISCREG_HPMEVENT31}},
520 
521  {CSR_TSELECT, {"tselect", MISCREG_TSELECT}},
522  {CSR_TDATA1, {"tdata1", MISCREG_TDATA1}},
523  {CSR_TDATA2, {"tdata2", MISCREG_TDATA2}},
524  {CSR_TDATA3, {"tdata3", MISCREG_TDATA3}},
525  {CSR_DCSR, {"dcsr", MISCREG_DCSR}},
526  {CSR_DPC, {"dpc", MISCREG_DPC}},
527  {CSR_DSCRATCH, {"dscratch", MISCREG_DSCRATCH}}
528 };
529 
537 BitUnion64(STATUS)
538  Bitfield<63> sd;
539  Bitfield<35, 34> sxl;
540  Bitfield<33, 32> uxl;
541  Bitfield<22> tsr;
542  Bitfield<21> tw;
543  Bitfield<20> tvm;
544  Bitfield<19> mxr;
545  Bitfield<18> sum;
546  Bitfield<17> mprv;
547  Bitfield<16, 15> xs;
548  Bitfield<14, 13> fs;
549  Bitfield<12, 11> mpp;
550  Bitfield<8> spp;
551  Bitfield<7> mpie;
552  Bitfield<5> spie;
553  Bitfield<4> upie;
554  Bitfield<3> mie;
555  Bitfield<1> sie;
556  Bitfield<0> uie;
557 EndBitUnion(STATUS)
558 
559 
565 BitUnion64(INTERRUPT)
566  Bitfield<11> mei;
567  Bitfield<9> sei;
568  Bitfield<8> uei;
569  Bitfield<7> mti;
570  Bitfield<5> sti;
571  Bitfield<4> uti;
572  Bitfield<3> msi;
573  Bitfield<1> ssi;
574  Bitfield<0> usi;
575 EndBitUnion(INTERRUPT)
576 
577 const off_t MXL_OFFSET = (sizeof(uint64_t) * 8 - 2);
578 const off_t SXL_OFFSET = 34;
579 const off_t UXL_OFFSET = 32;
580 const off_t FS_OFFSET = 13;
581 const off_t FRM_OFFSET = 5;
582 
583 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
585 const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
587 
588 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
591 const RegVal STATUS_TSR_MASK = 1ULL << 22;
592 const RegVal STATUS_TW_MASK = 1ULL << 21;
593 const RegVal STATUS_TVM_MASK = 1ULL << 20;
594 const RegVal STATUS_MXR_MASK = 1ULL << 19;
595 const RegVal STATUS_SUM_MASK = 1ULL << 18;
596 const RegVal STATUS_MPRV_MASK = 1ULL << 17;
597 const RegVal STATUS_XS_MASK = 3ULL << 15;
599 const RegVal STATUS_MPP_MASK = 3ULL << 11;
600 const RegVal STATUS_SPP_MASK = 1ULL << 8;
601 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
602 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
603 const RegVal STATUS_UPIE_MASK = 1ULL << 4;
604 const RegVal STATUS_MIE_MASK = 1ULL << 3;
605 const RegVal STATUS_SIE_MASK = 1ULL << 1;
606 const RegVal STATUS_UIE_MASK = 1ULL << 0;
627 
628 const RegVal MEI_MASK = 1ULL << 11;
629 const RegVal SEI_MASK = 1ULL << 9;
630 const RegVal UEI_MASK = 1ULL << 8;
631 const RegVal MTI_MASK = 1ULL << 7;
632 const RegVal STI_MASK = 1ULL << 5;
633 const RegVal UTI_MASK = 1ULL << 4;
634 const RegVal MSI_MASK = 1ULL << 3;
635 const RegVal SSI_MASK = 1ULL << 1;
636 const RegVal USI_MASK = 1ULL << 0;
641  STI_MASK | UTI_MASK |
642  SSI_MASK | USI_MASK;
644 const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
645 const RegVal FRM_MASK = 0x7;
646 
647 const std::map<int, RegVal> CSRMasks = {
649  {CSR_UIE, UI_MASK},
650  {CSR_UIP, UI_MASK},
652  {CSR_FRM, FRM_MASK},
655  {CSR_SIE, SI_MASK},
656  {CSR_SIP, SI_MASK},
658  {CSR_MISA, MISA_MASK},
659  {CSR_MIE, MI_MASK},
660  {CSR_MIP, MI_MASK}
661 };
662 
663 } // namespace RiscvISA
664 } // namespace gem5
665 
666 #endif // __ARCH_RISCV_REGS_MISC_HH__
gem5::RiscvISA::MI_MASK
const RegVal MI_MASK
Definition: misc.hh:637
gem5::RiscvISA::CSR_MSCRATCH
@ CSR_MSCRATCH
Definition: misc.hh:264
gem5::RiscvISA::CSR_MIDELEG
@ CSR_MIDELEG
Definition: misc.hh:260
gem5::RiscvISA::MISCREG_HPMCOUNTER31
@ MISCREG_HPMCOUNTER31
Definition: misc.hh:105
gem5::RiscvISA::MISCREG_HPMEVENT11
@ MISCREG_HPMEVENT11
Definition: misc.hh:114
gem5::RiscvISA::CSR_MHPMEVENT23
@ CSR_MHPMEVENT23
Definition: misc.hh:341
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:71
gem5::RiscvISA::CSR_HPMCOUNTER04
@ CSR_HPMCOUNTER04
Definition: misc.hh:210
gem5::RiscvISA::CSR_UTVAL
@ CSR_UTVAL
Definition: misc.hh:201
gem5::RiscvISA::upie
Bitfield< 4 > upie
Definition: misc.hh:553
gem5::RiscvISA::mprv
Bitfield< 17 > mprv
Definition: misc.hh:546
gem5::RiscvISA::FRM_MASK
const RegVal FRM_MASK
Definition: misc.hh:645
gem5::RiscvISA::sxl
Bitfield< 35, 34 > sxl
Definition: misc.hh:539
gem5::RiscvISA::uie
Bitfield< 0 > uie
Definition: misc.hh:556
gem5::RiscvISA::CSR_MHPMEVENT15
@ CSR_MHPMEVENT15
Definition: misc.hh:333
gem5::RiscvISA::CSR_SIDELEG
@ CSR_SIDELEG
Definition: misc.hh:242
gem5::RiscvISA::MISCREG_HPMCOUNTER09
@ MISCREG_HPMCOUNTER09
Definition: misc.hh:83
gem5::RiscvISA::CSR_PMPADDR15
@ CSR_PMPADDR15
Definition: misc.hh:288
gem5::RiscvISA::mti
Bitfield< 7 > mti
Definition: misc.hh:569
gem5::RiscvISA::CSR_DPC
@ CSR_DPC
Definition: misc.hh:356
gem5::RiscvISA::CSR_UIP
@ CSR_UIP
Definition: misc.hh:202
gem5::RiscvISA::MISCREG_PMPADDR11
@ MISCREG_PMPADDR11
Definition: misc.hh:166
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::MISCREG_HPMEVENT16
@ MISCREG_HPMEVENT16
Definition: misc.hh:119
gem5::RiscvISA::CSR_HPMCOUNTER12
@ CSR_HPMCOUNTER12
Definition: misc.hh:218
gem5::RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: misc.hh:366
gem5::RiscvISA::MISCREG_HPMCOUNTER27
@ MISCREG_HPMCOUNTER27
Definition: misc.hh:101
gem5::RiscvISA::tsr
Bitfield< 22 > tsr
Definition: misc.hh:541
gem5::RiscvISA::MISCREG_HPMCOUNTER08
@ MISCREG_HPMCOUNTER08
Definition: misc.hh:82
gem5::RiscvISA::tw
Bitfield< 21 > tw
Definition: misc.hh:542
gem5::RiscvISA::CSR_TDATA1
@ CSR_TDATA1
Definition: misc.hh:352
gem5::RiscvISA::CSR_SIP
@ CSR_SIP
Definition: misc.hh:250
gem5::RiscvISA::CSR_TSELECT
@ CSR_TSELECT
Definition: misc.hh:351
gem5::RiscvISA::MISCREG_HPMCOUNTER12
@ MISCREG_HPMCOUNTER12
Definition: misc.hh:86
gem5::RiscvISA::mpie
Bitfield< 7 > mpie
Definition: misc.hh:551
gem5::RiscvISA::CSR_MHPMEVENT14
@ CSR_MHPMEVENT14
Definition: misc.hh:332
gem5::RiscvISA::MISCREG_SIDELEG
@ MISCREG_SIDELEG
Definition: misc.hh:173
gem5::RiscvISA::CSR_PMPADDR02
@ CSR_PMPADDR02
Definition: misc.hh:275
gem5::RiscvISA::CSR_PMPADDR06
@ CSR_PMPADDR06
Definition: misc.hh:279
gem5::RiscvISA::CSR_MHPMEVENT07
@ CSR_MHPMEVENT07
Definition: misc.hh:325
gem5::RiscvISA::CSR_MHPMCOUNTER19
@ CSR_MHPMCOUNTER19
Definition: misc.hh:307
gem5::RiscvISA::CSR_HPMCOUNTER22
@ CSR_HPMCOUNTER22
Definition: misc.hh:228
gem5::RiscvISA::CSR_USCRATCH
@ CSR_USCRATCH
Definition: misc.hh:198
gem5::RiscvISA::CSR_HPMCOUNTER24
@ CSR_HPMCOUNTER24
Definition: misc.hh:230
gem5::RiscvISA::CSR_HPMCOUNTER08
@ CSR_HPMCOUNTER08
Definition: misc.hh:214
gem5::RiscvISA::CSR_DSCRATCH
@ CSR_DSCRATCH
Definition: misc.hh:357
gem5::RiscvISA::MISA_MASK
const RegVal MISA_MASK
Definition: misc.hh:586
gem5::RiscvISA::MISCREG_SSCRATCH
@ MISCREG_SSCRATCH
Definition: misc.hh:176
gem5::RiscvISA::CSR_HPMCOUNTER07
@ CSR_HPMCOUNTER07
Definition: misc.hh:213
gem5::RiscvISA::CSR_MHPMEVENT09
@ CSR_MHPMEVENT09
Definition: misc.hh:327
gem5::RiscvISA::STATUS_UPIE_MASK
const RegVal STATUS_UPIE_MASK
Definition: misc.hh:603
gem5::RiscvISA::MISCREG_HPMEVENT19
@ MISCREG_HPMEVENT19
Definition: misc.hh:122
gem5::RiscvISA::usi
Bitfield< 0 > usi
Definition: misc.hh:574
gem5::RiscvISA::CSR_MHPMCOUNTER26
@ CSR_MHPMCOUNTER26
Definition: misc.hh:314
gem5::RiscvISA::CSR_PMPADDR01
@ CSR_PMPADDR01
Definition: misc.hh:274
gem5::RiscvISA::CSR_MHPMEVENT20
@ CSR_MHPMEVENT20
Definition: misc.hh:338
gem5::RiscvISA::MISCREG_PMPADDR09
@ MISCREG_PMPADDR09
Definition: misc.hh:164
gem5::RiscvISA::MISCREG_HPMCOUNTER26
@ MISCREG_HPMCOUNTER26
Definition: misc.hh:100
gem5::RiscvISA::CSR_MHPMEVENT19
@ CSR_MHPMEVENT19
Definition: misc.hh:337
gem5::RiscvISA::CSR_PMPADDR08
@ CSR_PMPADDR08
Definition: misc.hh:281
gem5::RiscvISA::CSR_MARCHID
@ CSR_MARCHID
Definition: misc.hh:254
gem5::RiscvISA::CSR_MHPMCOUNTER09
@ CSR_MHPMCOUNTER09
Definition: misc.hh:297
gem5::RiscvISA::CSR_MHPMEVENT21
@ CSR_MHPMEVENT21
Definition: misc.hh:339
gem5::RiscvISA::MSI_MASK
const RegVal MSI_MASK
Definition: misc.hh:634
gem5::RiscvISA::CSR_HPMCOUNTER05
@ CSR_HPMCOUNTER05
Definition: misc.hh:211
gem5::RiscvISA::MISCREG_MTVAL
@ MISCREG_MTVAL
Definition: misc.hh:150
gem5::RiscvISA::CSR_UCAUSE
@ CSR_UCAUSE
Definition: misc.hh:200
gem5::RiscvISA::sie
Bitfield< 1 > sie
Definition: misc.hh:555
gem5::RiscvISA::MISCREG_HPMEVENT15
@ MISCREG_HPMEVENT15
Definition: misc.hh:118
gem5::RiscvISA::MISCREG_HPMEVENT05
@ MISCREG_HPMEVENT05
Definition: misc.hh:108
gem5::RiscvISA::MISCREG_SEDELEG
@ MISCREG_SEDELEG
Definition: misc.hh:172
gem5::RiscvISA::CSR_MHPMEVENT04
@ CSR_MHPMEVENT04
Definition: misc.hh:322
gem5::RiscvISA::MISCREG_HPMCOUNTER07
@ MISCREG_HPMCOUNTER07
Definition: misc.hh:81
gem5::RiscvISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:190
gem5::RiscvISA::STATUS_TW_MASK
const RegVal STATUS_TW_MASK
Definition: misc.hh:592
gem5::RiscvISA::MISCREG_DPC
@ MISCREG_DPC
Definition: misc.hh:140
gem5::RiscvISA::CSRMetadata::physIndex
const int physIndex
Definition: misc.hh:363
gem5::RiscvISA::CSR_HPMCOUNTER19
@ CSR_HPMCOUNTER19
Definition: misc.hh:225
gem5::RiscvISA::MISCREG_ISA
@ MISCREG_ISA
Definition: misc.hh:66
gem5::RiscvISA::MISCREG_IE
@ MISCREG_IE
Definition: misc.hh:73
gem5::RiscvISA::MISCREG_HPMEVENT14
@ MISCREG_HPMEVENT14
Definition: misc.hh:117
gem5::RiscvISA::CSR_TDATA2
@ CSR_TDATA2
Definition: misc.hh:353
gem5::RiscvISA::STATUS_TSR_MASK
const RegVal STATUS_TSR_MASK
Definition: misc.hh:591
gem5::RiscvISA::MISCREG_CYCLE
@ MISCREG_CYCLE
Definition: misc.hh:74
gem5::RiscvISA::CSR_HPMCOUNTER25
@ CSR_HPMCOUNTER25
Definition: misc.hh:231
gem5::RiscvISA::CSR_MCOUNTEREN
@ CSR_MCOUNTEREN
Definition: misc.hh:263
gem5::RiscvISA::STATUS_SPP_MASK
const RegVal STATUS_SPP_MASK
Definition: misc.hh:600
gem5::RiscvISA::MISCREG_HPMCOUNTER14
@ MISCREG_HPMCOUNTER14
Definition: misc.hh:88
gem5::RiscvISA::CSR_PMPADDR09
@ CSR_PMPADDR09
Definition: misc.hh:282
gem5::RiscvISA::STATUS_XS_MASK
const RegVal STATUS_XS_MASK
Definition: misc.hh:597
gem5::RiscvISA::CSR_SCOUNTEREN
@ CSR_SCOUNTEREN
Definition: misc.hh:245
gem5::RiscvISA::CSR_MHPMCOUNTER11
@ CSR_MHPMCOUNTER11
Definition: misc.hh:299
gem5::RiscvISA::sei
Bitfield< 9 > sei
Definition: misc.hh:567
gem5::RiscvISA::CSR_MHPMEVENT05
@ CSR_MHPMEVENT05
Definition: misc.hh:323
gem5::RiscvISA::CSR_DCSR
@ CSR_DCSR
Definition: misc.hh:355
gem5::RiscvISA::xs
Bitfield< 16, 15 > xs
Definition: misc.hh:547
gem5::RiscvISA::STATUS_SPIE_MASK
const RegVal STATUS_SPIE_MASK
Definition: misc.hh:602
gem5::RiscvISA::CSR_SEDELEG
@ CSR_SEDELEG
Definition: misc.hh:241
gem5::RiscvISA::CSR_FFLAGS
@ CSR_FFLAGS
Definition: misc.hh:203
gem5::RiscvISA::MISCREG_HPMEVENT22
@ MISCREG_HPMEVENT22
Definition: misc.hh:125
gem5::RiscvISA::MISCREG_HPMCOUNTER13
@ MISCREG_HPMCOUNTER13
Definition: misc.hh:87
gem5::RiscvISA::CSR_MHPMCOUNTER05
@ CSR_MHPMCOUNTER05
Definition: misc.hh:293
gem5::RiscvISA::MISCREG_HPMEVENT09
@ MISCREG_HPMEVENT09
Definition: misc.hh:112
gem5::RiscvISA::CSR_MHPMCOUNTER30
@ CSR_MHPMCOUNTER30
Definition: misc.hh:318
gem5::RiscvISA::CSR_HPMCOUNTER29
@ CSR_HPMCOUNTER29
Definition: misc.hh:235
gem5::RiscvISA::STATUS_UXL_MASK
const RegVal STATUS_UXL_MASK
Definition: misc.hh:590
gem5::RiscvISA::MISCREG_PMPADDR12
@ MISCREG_PMPADDR12
Definition: misc.hh:167
gem5::RiscvISA::MISCREG_SCAUSE
@ MISCREG_SCAUSE
Definition: misc.hh:178
gem5::RiscvISA::CSR_MINSTRET
@ CSR_MINSTRET
Definition: misc.hh:290
gem5::RiscvISA::FFLAGS_MASK
const RegVal FFLAGS_MASK
Definition: misc.hh:644
gem5::RiscvISA::MISCREG_HPMCOUNTER06
@ MISCREG_HPMCOUNTER06
Definition: misc.hh:80
gem5::RiscvISA::MISCREG_MEDELEG
@ MISCREG_MEDELEG
Definition: misc.hh:143
gem5::RiscvISA::CSR_MIMPID
@ CSR_MIMPID
Definition: misc.hh:255
gem5::RiscvISA::STATUS_UIE_MASK
const RegVal STATUS_UIE_MASK
Definition: misc.hh:606
gem5::RiscvISA::MISCREG_DSCRATCH
@ MISCREG_DSCRATCH
Definition: misc.hh:141
gem5::RiscvISA::CSR_UTVEC
@ CSR_UTVEC
Definition: misc.hh:197
gem5::RiscvISA::MISCREG_HPMEVENT29
@ MISCREG_HPMEVENT29
Definition: misc.hh:132
gem5::RiscvISA::CSR_MHPMCOUNTER06
@ CSR_MHPMCOUNTER06
Definition: misc.hh:294
gem5::RiscvISA::CSR_MHPMEVENT24
@ CSR_MHPMEVENT24
Definition: misc.hh:342
gem5::RiscvISA::CSR_MHPMCOUNTER28
@ CSR_MHPMCOUNTER28
Definition: misc.hh:316
gem5::RiscvISA::CSR_HPMCOUNTER21
@ CSR_HPMCOUNTER21
Definition: misc.hh:227
gem5::RiscvISA::FS_OFFSET
const off_t FS_OFFSET
Definition: misc.hh:580
gem5::RiscvISA::MISCREG_PMPADDR01
@ MISCREG_PMPADDR01
Definition: misc.hh:156
gem5::RiscvISA::MISCREG_INSTRET
@ MISCREG_INSTRET
Definition: misc.hh:76
gem5::RiscvISA::STATUS_TVM_MASK
const RegVal STATUS_TVM_MASK
Definition: misc.hh:593
gem5::RiscvISA::MISCREG_HPMCOUNTER29
@ MISCREG_HPMCOUNTER29
Definition: misc.hh:103
gem5::RiscvISA::CSR_PMPADDR07
@ CSR_PMPADDR07
Definition: misc.hh:280
gem5::RiscvISA::CSR_PMPADDR12
@ CSR_PMPADDR12
Definition: misc.hh:285
gem5::RiscvISA::CSR_FCSR
@ CSR_FCSR
Definition: misc.hh:205
gem5::RiscvISA::mpp
Bitfield< 12, 11 > mpp
Definition: misc.hh:549
gem5::RiscvISA::CSR_MCAUSE
@ CSR_MCAUSE
Definition: misc.hh:266
gem5::RiscvISA::SSTATUS_MASK
const RegVal SSTATUS_MASK
Definition: misc.hh:617
gem5::RiscvISA::tvm
Bitfield< 20 > tvm
Definition: misc.hh:543
gem5::RiscvISA::CSR_SEPC
@ CSR_SEPC
Definition: misc.hh:247
gem5::RiscvISA::MISCREG_PMPADDR05
@ MISCREG_PMPADDR05
Definition: misc.hh:160
gem5::RiscvISA::MISCREG_HPMEVENT24
@ MISCREG_HPMEVENT24
Definition: misc.hh:127
gem5::RiscvISA::CSR_USTATUS
@ CSR_USTATUS
Definition: misc.hh:195
gem5::RiscvISA::MISCREG_HPMCOUNTER25
@ MISCREG_HPMCOUNTER25
Definition: misc.hh:99
gem5::RiscvISA::SXL_OFFSET
const off_t SXL_OFFSET
Definition: misc.hh:578
gem5::RiscvISA::CSR_HPMCOUNTER11
@ CSR_HPMCOUNTER11
Definition: misc.hh:217
gem5::RiscvISA::CSR_MHPMCOUNTER10
@ CSR_MHPMCOUNTER10
Definition: misc.hh:298
gem5::RiscvISA::CSR_MTVAL
@ CSR_MTVAL
Definition: misc.hh:267
gem5::RiscvISA::MISCREG_HPMEVENT31
@ MISCREG_HPMEVENT31
Definition: misc.hh:134
gem5::RiscvISA::CSR_MHPMEVENT17
@ CSR_MHPMEVENT17
Definition: misc.hh:335
gem5::RiscvISA::MISCREG_FRM
@ MISCREG_FRM
Definition: misc.hh:188
gem5::RiscvISA::MISCREG_SEPC
@ MISCREG_SEPC
Definition: misc.hh:177
gem5::RiscvISA::MISCREG_MSCRATCH
@ MISCREG_MSCRATCH
Definition: misc.hh:147
gem5::RiscvISA::SEI_MASK
const RegVal SEI_MASK
Definition: misc.hh:629
gem5::RiscvISA::CSR_MHPMEVENT13
@ CSR_MHPMEVENT13
Definition: misc.hh:331
gem5::RiscvISA::CSR_MIE
@ CSR_MIE
Definition: misc.hh:261
gem5::RiscvISA::CSR_MHPMEVENT31
@ CSR_MHPMEVENT31
Definition: misc.hh:349
gem5::RiscvISA::CSR_MHPMEVENT28
@ CSR_MHPMEVENT28
Definition: misc.hh:346
gem5::RiscvISA::CSR_PMPADDR05
@ CSR_PMPADDR05
Definition: misc.hh:278
gem5::RiscvISA::CSR_SCAUSE
@ CSR_SCAUSE
Definition: misc.hh:248
gem5::RiscvISA::CSR_SSCRATCH
@ CSR_SSCRATCH
Definition: misc.hh:246
gem5::RiscvISA::MISCREG_HPMCOUNTER18
@ MISCREG_HPMCOUNTER18
Definition: misc.hh:92
gem5::RiscvISA::CSR_MHPMEVENT22
@ CSR_MHPMEVENT22
Definition: misc.hh:340
gem5::RiscvISA::MISCREG_IMPID
@ MISCREG_IMPID
Definition: misc.hh:69
gem5::RiscvISA::CSR_MSTATUS
@ CSR_MSTATUS
Definition: misc.hh:257
gem5::RiscvISA::MISCREG_HPMCOUNTER17
@ MISCREG_HPMCOUNTER17
Definition: misc.hh:91
gem5::RiscvISA::MISCREG_PMPADDR00
@ MISCREG_PMPADDR00
Definition: misc.hh:155
gem5::RiscvISA::STATUS_SXL_MASK
const RegVal STATUS_SXL_MASK
Definition: misc.hh:589
gem5::RiscvISA::MISCREG_HPMCOUNTER23
@ MISCREG_HPMCOUNTER23
Definition: misc.hh:97
gem5::RiscvISA::CSR_MHPMEVENT30
@ CSR_MHPMEVENT30
Definition: misc.hh:348
gem5::RiscvISA::MISCREG_VENDORID
@ MISCREG_VENDORID
Definition: misc.hh:67
bitunion.hh
gem5::RiscvISA::CSR_FRM
@ CSR_FRM
Definition: misc.hh:204
gem5::RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: misc.hh:180
gem5::RiscvISA::CSR_HPMCOUNTER15
@ CSR_HPMCOUNTER15
Definition: misc.hh:221
gem5::RiscvISA::MISCREG_PMPADDR08
@ MISCREG_PMPADDR08
Definition: misc.hh:163
gem5::RiscvISA::CSR_MHPMCOUNTER14
@ CSR_MHPMCOUNTER14
Definition: misc.hh:302
gem5::RiscvISA::CSR_HPMCOUNTER16
@ CSR_HPMCOUNTER16
Definition: misc.hh:222
gem5::RiscvISA::MISCREG_HPMEVENT21
@ MISCREG_HPMEVENT21
Definition: misc.hh:124
gem5::RiscvISA::MISCREG_HPMEVENT08
@ MISCREG_HPMEVENT08
Definition: misc.hh:111
gem5::RiscvISA::STATUS_FS_MASK
const RegVal STATUS_FS_MASK
Definition: misc.hh:598
gem5::RiscvISA::MISCREG_MCAUSE
@ MISCREG_MCAUSE
Definition: misc.hh:149
gem5::RiscvISA::USTATUS_MASK
const RegVal USTATUS_MASK
Definition: misc.hh:623
gem5::RiscvISA::CSR_HPMCOUNTER03
@ CSR_HPMCOUNTER03
Definition: misc.hh:209
gem5::RiscvISA::CSR_MHPMCOUNTER13
@ CSR_MHPMCOUNTER13
Definition: misc.hh:301
gem5::RiscvISA::MISCREG_HPMEVENT13
@ MISCREG_HPMEVENT13
Definition: misc.hh:116
gem5::RiscvISA::STATUS_MPIE_MASK
const RegVal STATUS_MPIE_MASK
Definition: misc.hh:601
gem5::RiscvISA::ssi
Bitfield< 1 > ssi
Definition: misc.hh:573
gem5::RiscvISA::CSR_SIE
@ CSR_SIE
Definition: misc.hh:243
gem5::RiscvISA::ISA_MXL_MASK
const RegVal ISA_MXL_MASK
Definition: misc.hh:583
gem5::RiscvISA::MISCREG_HPMEVENT20
@ MISCREG_HPMEVENT20
Definition: misc.hh:123
gem5::RiscvISA::MISCREG_HPMEVENT07
@ MISCREG_HPMEVENT07
Definition: misc.hh:110
gem5::RiscvISA::mie
Bitfield< 3 > mie
Definition: misc.hh:554
gem5::RiscvISA::uti
Bitfield< 4 > uti
Definition: misc.hh:571
gem5::RiscvISA::CSR_MHPMCOUNTER27
@ CSR_MHPMCOUNTER27
Definition: misc.hh:315
gem5::RiscvISA::MISCREG_TDATA1
@ MISCREG_TDATA1
Definition: misc.hh:136
gem5::RiscvISA::MISCREG_HPMEVENT30
@ MISCREG_HPMEVENT30
Definition: misc.hh:133
gem5::RiscvISA::CSR_MCYCLE
@ CSR_MCYCLE
Definition: misc.hh:289
gem5::RiscvISA::msi
Bitfield< 3 > msi
Definition: misc.hh:572
gem5::RiscvISA::CSR_PMPADDR03
@ CSR_PMPADDR03
Definition: misc.hh:276
gem5::RiscvISA::MISCREG_PMPCFG2
@ MISCREG_PMPCFG2
Definition: misc.hh:153
gem5::RiscvISA::CSR_HPMCOUNTER10
@ CSR_HPMCOUNTER10
Definition: misc.hh:216
gem5::RiscvISA::MISCREG_TDATA3
@ MISCREG_TDATA3
Definition: misc.hh:138
gem5::RiscvISA::CSR_MHPMEVENT06
@ CSR_MHPMEVENT06
Definition: misc.hh:324
gem5::RiscvISA::MISCREG_TSELECT
@ MISCREG_TSELECT
Definition: misc.hh:135
gem5::RiscvISA::CSR_HPMCOUNTER30
@ CSR_HPMCOUNTER30
Definition: misc.hh:236
gem5::RiscvISA::MISCREG_HPMEVENT17
@ MISCREG_HPMEVENT17
Definition: misc.hh:120
gem5::RiscvISA::MISCREG_USCRATCH
@ MISCREG_USCRATCH
Definition: misc.hh:183
gem5::RiscvISA::mask
mask
Definition: pra_constants.hh:73
gem5::RiscvISA::CSR_TDATA3
@ CSR_TDATA3
Definition: misc.hh:354
vec_pred_reg.hh
gem5::RiscvISA::MISCREG_HPMCOUNTER04
@ MISCREG_HPMCOUNTER04
Definition: misc.hh:78
gem5::RiscvISA::CSR_UIE
@ CSR_UIE
Definition: misc.hh:196
gem5::RiscvISA::CSR_SATP
@ CSR_SATP
Definition: misc.hh:251
gem5::RiscvISA::CSR_STVAL
@ CSR_STVAL
Definition: misc.hh:249
gem5::RiscvISA::STATUS_SD_MASK
const RegVal STATUS_SD_MASK
Definition: misc.hh:588
gem5::RiscvISA::CSR_MHPMCOUNTER23
@ CSR_MHPMCOUNTER23
Definition: misc.hh:311
gem5::RiscvISA::STATUS_MPP_MASK
const RegVal STATUS_MPP_MASK
Definition: misc.hh:599
gem5::RiscvISA::MISCREG_PMPADDR15
@ MISCREG_PMPADDR15
Definition: misc.hh:170
gem5::RiscvISA::CSR_MHPMCOUNTER17
@ CSR_MHPMCOUNTER17
Definition: misc.hh:305
gem5::RiscvISA::CSR_HPMCOUNTER20
@ CSR_HPMCOUNTER20
Definition: misc.hh:226
gem5::RiscvISA::MISCREG_PMPADDR03
@ MISCREG_PMPADDR03
Definition: misc.hh:158
gem5::RiscvISA::CSR_MHPMEVENT25
@ CSR_MHPMEVENT25
Definition: misc.hh:343
gem5::RiscvISA::MISCREG_PMPADDR10
@ MISCREG_PMPADDR10
Definition: misc.hh:165
gem5::RiscvISA::MISCREG_HPMEVENT27
@ MISCREG_HPMEVENT27
Definition: misc.hh:130
gem5::RiscvISA::CSR_TIME
@ CSR_TIME
Definition: misc.hh:207
gem5::RiscvISA::CSR_MHPMEVENT29
@ CSR_MHPMEVENT29
Definition: misc.hh:347
gem5::RiscvISA::MISCREG_HPMEVENT12
@ MISCREG_HPMEVENT12
Definition: misc.hh:115
gem5::RiscvISA::FRM_OFFSET
const off_t FRM_OFFSET
Definition: misc.hh:581
gem5::RiscvISA::CSR_MTVEC
@ CSR_MTVEC
Definition: misc.hh:262
gem5::RiscvISA::CSR_STVEC
@ CSR_STVEC
Definition: misc.hh:244
gem5::RiscvISA::MISCREG_MEPC
@ MISCREG_MEPC
Definition: misc.hh:148
gem5::RiscvISA::CSR_MHPMCOUNTER07
@ CSR_MHPMCOUNTER07
Definition: misc.hh:295
gem5::RiscvISA::spie
Bitfield< 5 > spie
Definition: misc.hh:552
gem5::RiscvISA::CSR_CYCLE
@ CSR_CYCLE
Definition: misc.hh:206
gem5::RiscvISA::MISCREG_HARTID
@ MISCREG_HARTID
Definition: misc.hh:70
gem5::RiscvISA::MISCREG_HPMCOUNTER22
@ MISCREG_HPMCOUNTER22
Definition: misc.hh:96
gem5::RiscvISA::MISCREG_HPMCOUNTER03
@ MISCREG_HPMCOUNTER03
Definition: misc.hh:77
vec_reg.hh
gem5::RiscvISA::MISCREG_PMPADDR07
@ MISCREG_PMPADDR07
Definition: misc.hh:162
gem5::RiscvISA::CSR_MHPMCOUNTER24
@ CSR_MHPMCOUNTER24
Definition: misc.hh:312
gem5::RiscvISA::CSR_MEDELEG
@ CSR_MEDELEG
Definition: misc.hh:259
gem5::RiscvISA::CSR_MHPMCOUNTER22
@ CSR_MHPMCOUNTER22
Definition: misc.hh:310
gem5::RiscvISA::CSR_HPMCOUNTER09
@ CSR_HPMCOUNTER09
Definition: misc.hh:215
gem5::RiscvISA::CSR_MHPMEVENT11
@ CSR_MHPMEVENT11
Definition: misc.hh:329
gem5::RiscvISA::CSR_MHPMCOUNTER16
@ CSR_MHPMCOUNTER16
Definition: misc.hh:304
gem5::RiscvISA::CSR_MHPMCOUNTER21
@ CSR_MHPMCOUNTER21
Definition: misc.hh:309
gem5::RiscvISA::UI_MASK
const RegVal UI_MASK
Definition: misc.hh:643
gem5::RiscvISA::CSR_MHPMCOUNTER20
@ CSR_MHPMCOUNTER20
Definition: misc.hh:308
gem5::RiscvISA::CSR_HPMCOUNTER14
@ CSR_HPMCOUNTER14
Definition: misc.hh:220
gem5::RiscvISA::MISCREG_HPMEVENT10
@ MISCREG_HPMEVENT10
Definition: misc.hh:113
gem5::RiscvISA::spp
Bitfield< 8 > spp
Definition: misc.hh:550
gem5::RiscvISA::USI_MASK
const RegVal USI_MASK
Definition: misc.hh:636
gem5::RiscvISA::CSR_MHPMCOUNTER18
@ CSR_MHPMCOUNTER18
Definition: misc.hh:306
gem5::RiscvISA::CSR_MHPMEVENT10
@ CSR_MHPMEVENT10
Definition: misc.hh:328
gem5::RiscvISA::MISCREG_HPMEVENT26
@ MISCREG_HPMEVENT26
Definition: misc.hh:129
gem5::RiscvISA::CSR_MHPMEVENT18
@ CSR_MHPMEVENT18
Definition: misc.hh:336
gem5::RiscvISA::STATUS_MIE_MASK
const RegVal STATUS_MIE_MASK
Definition: misc.hh:604
gem5::RiscvISA::CSR_MHPMEVENT03
@ CSR_MHPMEVENT03
Definition: misc.hh:321
gem5::RiscvISA::uxl
Bitfield< 33, 32 > uxl
Definition: misc.hh:540
gem5::RiscvISA::CSR_PMPADDR13
@ CSR_PMPADDR13
Definition: misc.hh:286
gem5::RiscvISA::MISCREG_ARCHID
@ MISCREG_ARCHID
Definition: misc.hh:68
gem5::RiscvISA::CSR_PMPCFG2
@ CSR_PMPCFG2
Definition: misc.hh:271
gem5::RiscvISA::MISCREG_UTVEC
@ MISCREG_UTVEC
Definition: misc.hh:182
gem5::RiscvISA::MISCREG_HPMCOUNTER21
@ MISCREG_HPMCOUNTER21
Definition: misc.hh:95
gem5::RiscvISA::MISCREG_HPMEVENT23
@ MISCREG_HPMEVENT23
Definition: misc.hh:126
gem5::RiscvISA::sti
Bitfield< 5 > sti
Definition: misc.hh:570
gem5::RiscvISA::MISCREG_PMPADDR06
@ MISCREG_PMPADDR06
Definition: misc.hh:161
types.hh
gem5::RiscvISA::CSR_MHPMEVENT12
@ CSR_MHPMEVENT12
Definition: misc.hh:330
gem5::RiscvISA::CSRIndex
CSRIndex
Definition: misc.hh:193
gem5::RiscvISA::MISCREG_PMPCFG0
@ MISCREG_PMPCFG0
Definition: misc.hh:151
gem5::RiscvISA::CSR_SSTATUS
@ CSR_SSTATUS
Definition: misc.hh:240
gem5::RiscvISA::CSR_HPMCOUNTER31
@ CSR_HPMCOUNTER31
Definition: misc.hh:237
gem5::RiscvISA::STATUS_MXR_MASK
const RegVal STATUS_MXR_MASK
Definition: misc.hh:594
gem5::RiscvISA::CSR_MHPMEVENT16
@ CSR_MHPMEVENT16
Definition: misc.hh:334
gem5::RiscvISA::CSR_HPMCOUNTER13
@ CSR_HPMCOUNTER13
Definition: misc.hh:219
gem5::RiscvISA::mxr
Bitfield< 19 > mxr
Definition: misc.hh:544
gem5::RiscvISA::CSR_HPMCOUNTER18
@ CSR_HPMCOUNTER18
Definition: misc.hh:224
gem5::RiscvISA::MISCREG_PMPADDR04
@ MISCREG_PMPADDR04
Definition: misc.hh:159
gem5::RiscvISA::CSR_PMPADDR04
@ CSR_PMPADDR04
Definition: misc.hh:277
gem5::RiscvISA::CSR_MHPMCOUNTER03
@ CSR_MHPMCOUNTER03
Definition: misc.hh:291
gem5::RiscvISA::MISCREG_PMPADDR14
@ MISCREG_PMPADDR14
Definition: misc.hh:169
gem5::RiscvISA::CSR_PMPADDR11
@ CSR_PMPADDR11
Definition: misc.hh:284
gem5::RiscvISA::CSR_HPMCOUNTER17
@ CSR_HPMCOUNTER17
Definition: misc.hh:223
gem5::RiscvISA::MISCREG_TIME
@ MISCREG_TIME
Definition: misc.hh:75
gem5::RiscvISA::CSR_MHPMCOUNTER15
@ CSR_MHPMCOUNTER15
Definition: misc.hh:303
gem5::RiscvISA::MISCREG_UEPC
@ MISCREG_UEPC
Definition: misc.hh:184
gem5::RiscvISA::CSR_MVENDORID
@ CSR_MVENDORID
Definition: misc.hh:253
gem5::RiscvISA::UXL_OFFSET
const off_t UXL_OFFSET
Definition: misc.hh:579
gem5::RiscvISA::MISCREG_HPMEVENT25
@ MISCREG_HPMEVENT25
Definition: misc.hh:128
gem5::RiscvISA::UTI_MASK
const RegVal UTI_MASK
Definition: misc.hh:633
gem5::RiscvISA::MISCREG_MIDELEG
@ MISCREG_MIDELEG
Definition: misc.hh:144
gem5::RiscvISA::CSR_MISA
@ CSR_MISA
Definition: misc.hh:258
gem5::RiscvISA::ISA_EXT_MASK
const RegVal ISA_EXT_MASK
Definition: misc.hh:584
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:774
gem5::RiscvISA::STATUS_MPRV_MASK
const RegVal STATUS_MPRV_MASK
Definition: misc.hh:596
gem5::RiscvISA::CSRMasks
const std::map< int, RegVal > CSRMasks
Definition: misc.hh:647
gem5::RiscvISA::MISCREG_PMPADDR02
@ MISCREG_PMPADDR02
Definition: misc.hh:157
gem5::RiscvISA::CSR_MHPMEVENT08
@ CSR_MHPMEVENT08
Definition: misc.hh:326
gem5::RiscvISA::MISCREG_STVAL
@ MISCREG_STVAL
Definition: misc.hh:179
gem5::RiscvISA::sum
Bitfield< 18 > sum
Definition: misc.hh:545
gem5::RiscvISA::MISCREG_HPMCOUNTER10
@ MISCREG_HPMCOUNTER10
Definition: misc.hh:84
gem5::RiscvISA::MISCREG_UCAUSE
@ MISCREG_UCAUSE
Definition: misc.hh:185
gem5::RiscvISA::uei
Bitfield< 8 > uei
Definition: misc.hh:568
gem5::RiscvISA::MEI_MASK
const RegVal MEI_MASK
Definition: misc.hh:628
gem5::RiscvISA::MISCREG_HPMCOUNTER24
@ MISCREG_HPMCOUNTER24
Definition: misc.hh:98
gem5::RiscvISA::CSR_MHPMCOUNTER08
@ CSR_MHPMCOUNTER08
Definition: misc.hh:296
gem5::RiscvISA::STATUS_SUM_MASK
const RegVal STATUS_SUM_MASK
Definition: misc.hh:595
gem5::RiscvISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:63
gem5::RiscvISA::MISCREG_HPMCOUNTER30
@ MISCREG_HPMCOUNTER30
Definition: misc.hh:104
gem5::RiscvISA::MISCREG_UTVAL
@ MISCREG_UTVAL
Definition: misc.hh:186
gem5::RiscvISA::MISCREG_HPMCOUNTER16
@ MISCREG_HPMCOUNTER16
Definition: misc.hh:90
gem5::RiscvISA::CSR_MEPC
@ CSR_MEPC
Definition: misc.hh:265
gem5::RiscvISA::EndBitUnion
EndBitUnion(SATP) enum AddrXlateMode
Definition: pagetable.hh:49
gem5::RiscvISA::CSR_HPMCOUNTER26
@ CSR_HPMCOUNTER26
Definition: misc.hh:232
gem5::RiscvISA::SI_MASK
const RegVal SI_MASK
Definition: misc.hh:640
gem5::RiscvISA::CSR_MHARTID
@ CSR_MHARTID
Definition: misc.hh:256
gem5::RiscvISA::CSR_PMPCFG0
@ CSR_PMPCFG0
Definition: misc.hh:269
gem5::RiscvISA::CSR_MHPMCOUNTER25
@ CSR_MHPMCOUNTER25
Definition: misc.hh:313
gem5::RiscvISA::CSR_PMPADDR00
@ CSR_PMPADDR00
Definition: misc.hh:273
gem5::RiscvISA::MISCREG_MCOUNTEREN
@ MISCREG_MCOUNTEREN
Definition: misc.hh:146
gem5::RiscvISA::MISCREG_HPMEVENT28
@ MISCREG_HPMEVENT28
Definition: misc.hh:131
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::MISCREG_PRV
@ MISCREG_PRV
Definition: misc.hh:65
gem5::RiscvISA::CSR_PMPADDR10
@ CSR_PMPADDR10
Definition: misc.hh:283
gem5::RiscvISA::CSR_MHPMCOUNTER29
@ CSR_MHPMCOUNTER29
Definition: misc.hh:317
gem5::RiscvISA::MTI_MASK
const RegVal MTI_MASK
Definition: misc.hh:631
gem5::RiscvISA::CSR_MHPMEVENT27
@ CSR_MHPMEVENT27
Definition: misc.hh:345
gem5::RiscvISA::CSR_PMPADDR14
@ CSR_PMPADDR14
Definition: misc.hh:287
gem5::RiscvISA::CSR_UEPC
@ CSR_UEPC
Definition: misc.hh:199
gem5::RiscvISA::ISA_EXT_C_MASK
const RegVal ISA_EXT_C_MASK
Definition: misc.hh:585
gem5::RiscvISA::MISCREG_HPMEVENT18
@ MISCREG_HPMEVENT18
Definition: misc.hh:121
gem5::RiscvISA::CSR_MHPMEVENT26
@ CSR_MHPMEVENT26
Definition: misc.hh:344
gem5::RiscvISA::MISCREG_HPMCOUNTER19
@ MISCREG_HPMCOUNTER19
Definition: misc.hh:93
gem5::RiscvISA::MISCREG_PMPADDR13
@ MISCREG_PMPADDR13
Definition: misc.hh:168
gem5::RiscvISA::CSR_HPMCOUNTER06
@ CSR_HPMCOUNTER06
Definition: misc.hh:212
gem5::RiscvISA::fs
Bitfield< 14, 13 > fs
Definition: misc.hh:548
gem5::RiscvISA::MISCREG_TDATA2
@ MISCREG_TDATA2
Definition: misc.hh:137
gem5::RiscvISA::MISCREG_HPMEVENT04
@ MISCREG_HPMEVENT04
Definition: misc.hh:107
gem5::RiscvISA::MISCREG_FFLAGS
@ MISCREG_FFLAGS
Definition: misc.hh:187
gem5::RiscvISA::MSTATUS_MASK
const RegVal MSTATUS_MASK
Definition: misc.hh:607
gem5::RiscvISA::BitUnion64
BitUnion64(SATP) Bitfield< 63
gem5::RiscvISA::MISCREG_DCSR
@ MISCREG_DCSR
Definition: misc.hh:139
gem5::RiscvISA::MISCREG_IP
@ MISCREG_IP
Definition: misc.hh:72
gem5::RiscvISA::MISCREG_STVEC
@ MISCREG_STVEC
Definition: misc.hh:174
gem5::RiscvISA::STATUS_SIE_MASK
const RegVal STATUS_SIE_MASK
Definition: misc.hh:605
gem5::RiscvISA::MISCREG_HPMEVENT06
@ MISCREG_HPMEVENT06
Definition: misc.hh:109
gem5::RiscvISA::CSRMetadata::name
const std::string name
Definition: misc.hh:362
gem5::RiscvISA::MISCREG_HPMCOUNTER15
@ MISCREG_HPMCOUNTER15
Definition: misc.hh:89
gem5::RiscvISA::CSR_HPMCOUNTER27
@ CSR_HPMCOUNTER27
Definition: misc.hh:233
gem5::RiscvISA::MISCREG_MTVEC
@ MISCREG_MTVEC
Definition: misc.hh:145
gem5::RiscvISA::MISCREG_SCOUNTEREN
@ MISCREG_SCOUNTEREN
Definition: misc.hh:175
gem5::RiscvISA::SSI_MASK
const RegVal SSI_MASK
Definition: misc.hh:635
gem5::RiscvISA::CSR_MHPMCOUNTER04
@ CSR_MHPMCOUNTER04
Definition: misc.hh:292
gem5::RiscvISA::CSR_MHPMCOUNTER12
@ CSR_MHPMCOUNTER12
Definition: misc.hh:300
gem5::RiscvISA::UEI_MASK
const RegVal UEI_MASK
Definition: misc.hh:630
gem5::RiscvISA::CSR_HPMCOUNTER28
@ CSR_HPMCOUNTER28
Definition: misc.hh:234
gem5::RiscvISA::MISCREG_HPMCOUNTER11
@ MISCREG_HPMCOUNTER11
Definition: misc.hh:85
gem5::RiscvISA::MISCREG_HPMCOUNTER05
@ MISCREG_HPMCOUNTER05
Definition: misc.hh:79
gem5::RiscvISA::CSR_MHPMCOUNTER31
@ CSR_MHPMCOUNTER31
Definition: misc.hh:319
gem5::RiscvISA::STI_MASK
const RegVal STI_MASK
Definition: misc.hh:632
gem5::RiscvISA::CSR_MIP
@ CSR_MIP
Definition: misc.hh:268
gem5::RiscvISA::MISCREG_HPMCOUNTER28
@ MISCREG_HPMCOUNTER28
Definition: misc.hh:102
gem5::RiscvISA::MISCREG_HPMCOUNTER20
@ MISCREG_HPMCOUNTER20
Definition: misc.hh:94
gem5::RiscvISA::MISCREG_HPMEVENT03
@ MISCREG_HPMEVENT03
Definition: misc.hh:106
gem5::RiscvISA::CSR_HPMCOUNTER23
@ CSR_HPMCOUNTER23
Definition: misc.hh:229
gem5::RiscvISA::CSR_INSTRET
@ CSR_INSTRET
Definition: misc.hh:208
gem5::RiscvISA::CSRMetadata
Definition: misc.hh:360

Generated on Tue Sep 21 2021 12:24:35 for gem5 by doxygen 1.8.17