47#ifndef __ARCH_RISCV_REGS_MISC_HH__
48#define __ARCH_RISCV_REGS_MISC_HH__
51#include <unordered_map>
59#include "debug/MiscRegs.hh"
60#include "enums/RiscvType.hh"
524template <
typename... T>
526 return ((1 << args) | ...);
529template <
typename... T>
531 return ((1ULL << (isa_exts -
'a')) | ...);
538const std::unordered_map<int, CSRMetadata>
CSRData = {
1195 Bitfield<63> rv64_sd;
1282const off_t MXL_OFFSETS[enums::Num_RiscvType] = {
1283 [
RV32] = (
sizeof(uint32_t) * 8 - 2),
1284 [
RV64] = (
sizeof(uint64_t) * 8 - 2),
1301 [
RV32] = 3ULL << MXL_OFFSETS[
RV32],
1302 [
RV64] = 3ULL << MXL_OFFSETS[
RV64],
1313 [
RV32] = 1ULL << ((
sizeof(uint32_t) * 8) - 1),
1314 [
RV64] = 1ULL << ((
sizeof(uint64_t) * 8) - 1),
1422 [enums::MNU] = 0ULL,
1436 [enums::MNU] = 0ULL,
1456 [enums::MSU] = 0ULL,
1468 [enums::MSU] = 0ULL,
1510 [enums::MSU] = 0ULL,
1517 [
RV32] = (1ULL << 31),
1518 [
RV64] = (1ULL << 63),
1521const std::unordered_map<int, RegVal>
1522CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
#define EndBitUnion(name)
This closes off the class and union started by the above macro.
constexpr RegClass miscRegClass
const RegVal STATUS_TSR_MASK
const RegVal UI_MASK[enums::Num_PrivilegeModeSet]
const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet]
const RegVal SI_MASK[enums::Num_PrivilegeModeSet]
constexpr uint64_t isaExtsFlags()
constexpr enums::RiscvType RV32
const RegVal STATUS_MBE_MASK[enums::Num_RiscvType]
const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType]
const RegVal STATUS_SBE_MASK[enums::Num_RiscvType]
const RegVal STATUS_MIE_MASK
const RegVal STATUS_SIE_MASK
const RegVal STATUS_TW_MASK
const RegVal STATUS_MPIE_MASK
const RegVal SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const RegVal STATUS_VS_MASK
const off_t MBE_OFFSET[enums::Num_RiscvType]
const RegVal STATUS_XS_MASK
const RegVal STATUS_SXL_MASK
const RegVal STATUS_MPRV_MASK
const RegVal STATUS_UXL_MASK
const RegVal STATUS_MXR_MASK
const RegVal USTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const std::unordered_map< int, CSRMetadata > CSRData
const std::unordered_map< int, RegVal > CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
const RegVal STATUS_FS_MASK
const RegVal STATUS_SPP_MASK
const RegVal ISA_EXT_MASK
const RegVal STATUS_SD_MASKS[enums::Num_RiscvType]
const RegVal STATUS_SPIE_MASK
const RegVal STATUS_MPP_MASK
const RegVal STATUS_UIE_MASK
constexpr enums::RiscvType RV64
const RegVal ISA_EXT_C_MASK
const RegVal MISA_MASKS[enums::Num_RiscvType]
const RegVal ISA_MXL_MASKS[enums::Num_RiscvType]
const RegVal MI_MASK[enums::Num_PrivilegeModeSet]
const RegVal STATUS_SUM_MASK
Bitfield< 31, 30 > rv32_mxl
const off_t SBE_OFFSET[enums::Num_RiscvType]
const RegVal STATUS_UPIE_MASK
constexpr uint64_t rvTypeFlags(T... args)
const RegVal STATUS_TVM_MASK
const RegVal MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Copyright (c) 2024 Arm Limited All rights reserved.
constexpr char MiscRegClassName[]
@ MiscRegClass
Control (misc) register.
Vector Registers layout specification.