46 #ifndef __ARCH_RISCV_REGS_MISC_HH__
47 #define __ARCH_RISCV_REGS_MISC_HH__
50 #include <unordered_map>
57 #include "debug/MiscRegs.hh"
381 const std::unordered_map<int, CSRMetadata>
CSRData = {
593 const off_t MXL_OFFSET = (
sizeof(uint64_t) * 8 - 2);
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
const RegVal STATUS_TSR_MASK
const RegVal USTATUS_MASK
const RegVal STATUS_SD_MASK
const RegVal SSTATUS_MASK
const RegVal ISA_MXL_MASK
const RegVal STATUS_MIE_MASK
const RegVal STATUS_SIE_MASK
const RegVal STATUS_TW_MASK
const RegVal STATUS_MPIE_MASK
const RegVal STATUS_VS_MASK
const RegVal STATUS_XS_MASK
const RegVal STATUS_SXL_MASK
EndBitUnion(SATP) enum AddrXlateMode
const RegVal STATUS_MPRV_MASK
const RegVal STATUS_UXL_MASK
const RegVal STATUS_MXR_MASK
const std::unordered_map< int, CSRMetadata > CSRData
const std::unordered_map< int, RegVal > CSRMasks
const RegVal STATUS_FS_MASK
const RegVal STATUS_SPP_MASK
const RegVal ISA_EXT_MASK
const RegVal STATUS_SPIE_MASK
const RegVal STATUS_MPP_MASK
const RegVal STATUS_UIE_MASK
const RegVal ISA_EXT_C_MASK
const RegVal STATUS_SUM_MASK
BitUnion64(SATP) Bitfield< 63
const RegVal STATUS_UPIE_MASK
const RegVal STATUS_TVM_MASK
const RegVal MSTATUS_MASK
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
constexpr char MiscRegClassName[]
@ MiscRegClass
Control (misc) register.
Vector Registers layout specification.