gem5  v22.0.0.1
cmos.cc
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28 
29 #include "dev/x86/cmos.hh"
30 
31 #include "base/trace.hh"
32 #include "debug/CMOS.hh"
33 #include "dev/x86/intdev.hh"
34 #include "mem/packet_access.hh"
35 
36 namespace gem5
37 {
38 
39 void
41 {
42  for (auto *wire: intPin) {
43  wire->raise();
44  //XXX This is a hack.
45  wire->lower();
46  }
47 }
48 
49 Tick
51 {
52  assert(pkt->getSize() == 1);
53  switch(pkt->getAddr() - pioAddr)
54  {
55  case 0x0:
56  pkt->setLE(address);
57  break;
58  case 0x1:
59  pkt->setLE(readRegister(address.regNum));
60  break;
61  default:
62  panic("Read from undefined CMOS port.\n");
63  }
64  pkt->makeAtomicResponse();
65  return latency;
66 }
67 
68 Tick
70 {
71  assert(pkt->getSize() == 1);
72  switch(pkt->getAddr() - pioAddr)
73  {
74  case 0x0:
75  address = pkt->getLE<uint8_t>();
76  break;
77  case 0x1:
78  // Ignore the NMI mask bit since we never try to generate one anyway.
79  writeRegister(address.regNum, pkt->getLE<uint8_t>());
80  break;
81  default:
82  panic("Write to undefined CMOS port.\n");
83  }
84  pkt->makeAtomicResponse();
85  return latency;
86 }
87 
88 uint8_t
90 {
91  assert(reg < numRegs);
92  uint8_t val;
93  if (reg <= 0xD) {
94  val = rtc.readData(reg);
95  DPRINTF(CMOS,
96  "Reading CMOS RTC reg %x as %x.\n", reg, val);
97  } else {
98  val = regs[reg];
99  DPRINTF(CMOS,
100  "Reading non-volitile CMOS address %x as %x.\n", reg, val);
101  }
102  return val;
103 }
104 
105 void
107 {
108  assert(reg < numRegs);
109  if (reg <= 0xD) {
110  DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n",
111  reg, val);
112  rtc.writeData(reg, val);
113  } else {
114  DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n",
115  reg, val);
116  regs[reg] = val;
117  }
118 }
119 
120 void
122 {
123  rtc.startup();
124 }
125 
126 void
128 {
129  SERIALIZE_SCALAR(address);
131 
132  // Serialize the timer
133  rtc.serialize("rtc", cp);
134 }
135 
136 void
138 {
139  UNSERIALIZE_SCALAR(address);
141 
142  // Serialize the timer
143  rtc.unserialize("rtc", cp);
144 }
145 
146 } // namespace gem5
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::X86ISA::Cmos::X86RTC::handleEvent
void handleEvent()
Definition: cmos.cc:40
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::X86ISA::Cmos::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: cmos.cc:127
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1056
gem5::X86ISA::Cmos::writeRegister
void writeRegister(uint8_t reg, uint8_t val)
Definition: cmos.cc:106
gem5::X86ISA::Cmos::readRegister
uint8_t readRegister(uint8_t reg)
Definition: cmos.cc:89
gem5::X86ISA::Cmos::latency
Tick latency
Definition: cmos.hh:47
intdev.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::Cmos::numRegs
static const int numRegs
Definition: cmos.hh:56
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::MC146818::startup
virtual void startup()
Start ticking.
Definition: mc146818.cc:124
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::Cmos::X86RTC::intPin
std::vector< IntSourcePin< X86RTC > * > intPin
Definition: cmos.hh:66
gem5::X86ISA::Cmos::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: cmos.cc:137
cmos.hh
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::MC146818::writeData
void writeData(const uint8_t addr, const uint8_t data)
RTC write data.
Definition: mc146818.cc:136
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::X86ISA::Cmos::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: cmos.cc:50
gem5::MC146818::serialize
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
Definition: mc146818.cc:266
gem5::X86ISA::Cmos::rtc
gem5::X86ISA::Cmos::X86RTC rtc
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::X86ISA::Cmos::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: cmos.cc:121
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::X86ISA::Cmos::regs
uint8_t regs[numRegs]
Definition: cmos.hh:58
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MC146818::unserialize
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.
Definition: mc146818.cc:286
gem5::MC146818::readData
uint8_t readData(const uint8_t addr)
RTC read data.
Definition: mc146818.cc:229
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
gem5::X86ISA::Cmos::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: cmos.cc:69
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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