gem5  v21.1.0.2
cpuid.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2008 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "arch/x86/cpuid.hh"
30 
31 #include "arch/x86/isa.hh"
32 #include "base/bitfield.hh"
33 #include "cpu/thread_context.hh"
34 
35 namespace gem5
36 {
37 
38 namespace X86ISA {
40  {
50  };
51 
53  {
63 
64  /*
65  * The following are defined by the spec but not yet implemented
66  */
67 /* // Function 9 is reserved
68  SVMInfo = 10,
69  // Functions 11-24 are reserved
70  TLB1GBPageInfo = 25,
71  PerformanceInfo,*/
72 
74  };
75 
76  static const int nameStringSize = 48;
77  static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
78 
79  uint64_t
80  stringToRegister(const char *str)
81  {
82  uint64_t reg = 0;
83  for (int pos = 3; pos >=0; pos--) {
84  reg <<= 8;
85  reg |= str[pos];
86  }
87  return reg;
88  }
89 
90  bool
91  doCpuid(ThreadContext * tc, uint32_t function,
92  uint32_t index, CpuidResult &result)
93  {
94  uint16_t family = bits(function, 31, 16);
95  uint16_t funcNum = bits(function, 15, 0);
96  if (family == 0x8000) {
97  // The extended functions
98  switch (funcNum) {
100  {
101  ISA *isa = dynamic_cast<ISA *>(tc->getIsaPtr());
102  auto vendor_string = isa->getVendorString();
103  result = CpuidResult(
104  0x80000000 + NumExtendedCpuidFuncs - 1,
105  stringToRegister(vendor_string.c_str()),
106  stringToRegister(vendor_string.c_str() + 4),
107  stringToRegister(vendor_string.c_str() + 8));
108  }
109  break;
111  result = CpuidResult(0x00020f51, 0x00000405,
112  0xebd3fbff, 0x00000001);
113  break;
114  case NameString1:
115  case NameString2:
116  case NameString3:
117  {
118  // Zero fill anything beyond the end of the string. This
119  // should go away once the string is a vetted parameter.
120  char cleanName[nameStringSize];
121  memset(cleanName, '\0', nameStringSize);
122  strncpy(cleanName, nameString, nameStringSize);
123 
124  int offset = (funcNum - NameString1) * 16;
125  assert(nameStringSize >= offset + 16);
126  result = CpuidResult(
127  stringToRegister(cleanName + offset + 0),
128  stringToRegister(cleanName + offset + 4),
129  stringToRegister(cleanName + offset + 12),
130  stringToRegister(cleanName + offset + 8));
131  }
132  break;
133  case L1CacheAndTLB:
134  result = CpuidResult(0xff08ff08, 0xff20ff20,
135  0x40020140, 0x40020140);
136  break;
137  case L2L3CacheAndL2TLB:
138  result = CpuidResult(0x00000000, 0x42004200,
139  0x00000000, 0x04008140);
140  break;
141  case APMInfo:
142  result = CpuidResult(0x80000018, 0x68747541,
143  0x69746e65, 0x444d4163);
144  break;
145  case LongModeAddressSize:
146  result = CpuidResult(0x00003030, 0x00000000,
147  0x00000000, 0x00000000);
148  break;
149 /* case SVMInfo:
150  case TLB1GBPageInfo:
151  case PerformanceInfo:*/
152  default:
153  warn("x86 cpuid family 0x8000: unimplemented function %u",
154  funcNum);
155  return false;
156  }
157  } else if (family == 0x0000) {
158  // The standard functions
159  switch (funcNum) {
161  {
162  ISA *isa = dynamic_cast<ISA *>(tc->getIsaPtr());
163  auto vendor_string = isa->getVendorString();
164  result = CpuidResult(
166  stringToRegister(vendor_string.c_str()),
167  stringToRegister(vendor_string.c_str() + 4),
168  stringToRegister(vendor_string.c_str() + 8));
169  }
170  break;
171  case FamilyModelStepping:
172  result = CpuidResult(0x00020f51, 0x00000805,
173  0xefdbfbff, 0x00000209);
174  break;
175  case ExtendedFeatures:
176  result = CpuidResult(0x00000000, 0x01800000,
177  0x00000000, 0x00000000);
178  break;
179  default:
180  warn("x86 cpuid family 0x0000: unimplemented function %u",
181  funcNum);
182  return false;
183  }
184  } else {
185  warn("x86 cpuid: unknown family %#x", family);
186  return false;
187  }
188 
189  return true;
190  }
191 } // namespace X86ISA
192 } // namespace gem5
gem5::X86ISA::ExtendedFeatures
@ ExtendedFeatures
Definition: cpuid.cc:48
gem5::X86ISA::NameString3
@ NameString3
Definition: cpuid.cc:58
warn
#define warn(...)
Definition: logging.hh:245
gem5::X86ISA::FamilyModelStepping
@ FamilyModelStepping
Definition: cpuid.cc:42
gem5::X86ISA::ISA
Definition: isa.hh:50
gem5::X86ISA::APMInfo
@ APMInfo
Definition: cpuid.cc:61
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
gem5::X86ISA::ExtendedCpuidFunctions
ExtendedCpuidFunctions
Definition: cpuid.cc:52
gem5::X86ISA::L1CacheAndTLB
@ L1CacheAndTLB
Definition: cpuid.cc:59
gem5::X86ISA::StandardCpuidFunction
StandardCpuidFunction
Definition: cpuid.cc:39
gem5::X86ISA::L2L3CacheAndL2TLB
@ L2L3CacheAndL2TLB
Definition: cpuid.cc:60
gem5::X86ISA::CpuidResult
Definition: cpuid.hh:41
gem5::X86ISA::stringToRegister
uint64_t stringToRegister(const char *str)
Definition: cpuid.cc:80
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::SerialNumber
@ SerialNumber
Definition: cpuid.cc:44
gem5::X86ISA::NameString2
@ NameString2
Definition: cpuid.cc:57
gem5::X86ISA::NumExtendedCpuidFuncs
@ NumExtendedCpuidFuncs
Definition: cpuid.cc:73
gem5::X86ISA::CacheParams
@ CacheParams
Definition: cpuid.cc:45
gem5::X86ISA::ThermalPowerMgmt
@ ThermalPowerMgmt
Definition: cpuid.cc:47
gem5::X86ISA::VendorAndLargestExtFunc
@ VendorAndLargestExtFunc
Definition: cpuid.cc:54
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::FamilyModelSteppingBrandFeatures
@ FamilyModelSteppingBrandFeatures
Definition: cpuid.cc:55
gem5::X86ISA::MonitorMwait
@ MonitorMwait
Definition: cpuid.cc:46
gem5::X86ISA::nameStringSize
static const int nameStringSize
Definition: cpuid.cc:76
gem5::X86ISA::ISA::getVendorString
std::string getVendorString() const
Definition: isa.cc:486
isa.hh
gem5::X86ISA::doCpuid
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition: cpuid.cc:91
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::NumStandardCpuidFuncs
@ NumStandardCpuidFuncs
Definition: cpuid.cc:49
gem5::X86ISA::LongModeAddressSize
@ LongModeAddressSize
Definition: cpuid.cc:62
gem5::X86ISA::CacheAndTLB
@ CacheAndTLB
Definition: cpuid.cc:43
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
cpuid.hh
gem5::X86ISA::NameString1
@ NameString1
Definition: cpuid.cc:56
gem5::X86ISA::VendorAndLargestStdFunc
@ VendorAndLargestStdFunc
Definition: cpuid.cc:41
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
thread_context.hh
gem5::X86ISA::nameString
static const char nameString[nameStringSize]
Definition: cpuid.cc:77

Generated on Tue Sep 21 2021 12:24:51 for gem5 by doxygen 1.8.17