gem5  v21.1.0.2
cpuid.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2008 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #ifndef __ARCH_X86_CPUID_HH__
30 #define __ARCH_X86_CPUID_HH__
31 
32 #include "base/types.hh"
33 
34 namespace gem5
35 {
36 
37 class ThreadContext;
38 
39 namespace X86ISA
40 {
41  struct CpuidResult
42  {
43  uint64_t rax;
44  uint64_t rbx;
45  uint64_t rcx;
46  uint64_t rdx;
47 
48  // These are not in alphebetical order on purpose. The order reflects
49  // how the CPUID orders the registers when it returns results.
50  CpuidResult(uint64_t _rax, uint64_t _rbx,
51  uint64_t _rdx, uint64_t _rcx) :
52  rax(_rax), rbx(_rbx), rcx(_rcx), rdx(_rdx)
53  {}
54 
56  {}
57  };
58 
59  uint64_t stringToRegister(const char *str);
60 
61  bool doCpuid(ThreadContext * tc, uint32_t function,
62  uint32_t index, CpuidResult &result);
63 
64 } // namespace X86ISA
65 } // namespace gem5
66 
67 #endif
gem5::X86ISA::CpuidResult::CpuidResult
CpuidResult()
Definition: cpuid.hh:55
gem5::X86ISA::CpuidResult
Definition: cpuid.hh:41
gem5::X86ISA::CpuidResult::CpuidResult
CpuidResult(uint64_t _rax, uint64_t _rbx, uint64_t _rdx, uint64_t _rcx)
Definition: cpuid.hh:50
gem5::X86ISA::stringToRegister
uint64_t stringToRegister(const char *str)
Definition: cpuid.cc:80
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::CpuidResult::rdx
uint64_t rdx
Definition: cpuid.hh:46
gem5::X86ISA::CpuidResult::rcx
uint64_t rcx
Definition: cpuid.hh:45
gem5::X86ISA::doCpuid
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition: cpuid.cc:91
types.hh
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::CpuidResult::rbx
uint64_t rbx
Definition: cpuid.hh:44
gem5::X86ISA::CpuidResult::rax
uint64_t rax
Definition: cpuid.hh:43
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

Generated on Tue Sep 21 2021 12:24:51 for gem5 by doxygen 1.8.17