gem5
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arch
x86
cpuid.hh
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/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_CPUID_HH__
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#define __ARCH_X86_CPUID_HH__
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#include <unordered_map>
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#include "
base/types.hh
"
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#include "params/X86ISA.hh"
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namespace
gem5
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{
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class
ThreadContext;
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namespace
X86ISA
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{
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enum
StandardCpuidFunction
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{
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VendorAndLargestStdFunc
,
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FamilyModelStepping
,
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CacheAndTLB
,
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SerialNumber
,
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CacheParams
,
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MonitorMwait
,
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ThermalPowerMgmt
,
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ExtendedFeatures
,
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ExtendedState
= 0xD,
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NumStandardCpuidFuncs
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};
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enum
ExtendedCpuidFunctions
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{
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VendorAndLargestExtFunc
,
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FamilyModelSteppingBrandFeatures
,
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NameString1
,
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NameString2
,
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NameString3
,
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L1CacheAndTLB
,
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L2L3CacheAndL2TLB
,
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APMInfo
,
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LongModeAddressSize
,
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NumExtendedCpuidFuncs
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};
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constexpr
int
nameStringSize
= 48;
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struct
CpuidResult
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{
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uint64_t
rax
;
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uint64_t
rbx
;
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uint64_t
rcx
;
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uint64_t
rdx
;
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// These are not in alphebetical order on purpose. The order reflects
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// how the CPUID orders the registers when it returns results.
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CpuidResult
(uint64_t _rax, uint64_t _rbx,
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uint64_t _rdx, uint64_t _rcx) :
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rax
(_rax),
rbx
(_rbx),
rcx
(_rcx),
rdx
(_rdx)
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{}
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CpuidResult
()
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{}
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};
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class
X86CPUID
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{
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public
:
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X86CPUID
(
const
std::string& vendor,
const
std::string&
name
);
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void
addStandardFunc
(uint32_t func,
std::vector<uint32_t>
values);
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void
addExtendedFunc
(uint32_t func,
std::vector<uint32_t>
values);
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bool
doCpuid
(
ThreadContext
* tc, uint32_t function,
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uint32_t
index
,
CpuidResult
&result);
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bool
hasSignificantIndex
(uint32_t function);
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private
:
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const
std::string
vendorString
;
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const
std::string
nameString
;
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std::unordered_map<uint32_t, std::vector<uint32_t>>
capabilities
;
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uint64_t
stringToRegister
(
const
char
*str);
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};
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}
// namespace X86ISA
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}
// namespace gem5
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#endif
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::X86ISA::X86CPUID
Definition
cpuid.hh:94
gem5::X86ISA::X86CPUID::hasSignificantIndex
bool hasSignificantIndex(uint32_t function)
Definition
cpuid.cc:147
gem5::X86ISA::X86CPUID::capabilities
std::unordered_map< uint32_t, std::vector< uint32_t > > capabilities
Definition
cpuid.hh:108
gem5::X86ISA::X86CPUID::addStandardFunc
void addStandardFunc(uint32_t func, std::vector< uint32_t > values)
Definition
cpuid.cc:50
gem5::X86ISA::X86CPUID::addExtendedFunc
void addExtendedFunc(uint32_t func, std::vector< uint32_t > values)
Definition
cpuid.cc:56
gem5::X86ISA::X86CPUID::nameString
const std::string nameString
Definition
cpuid.hh:107
gem5::X86ISA::X86CPUID::doCpuid
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition
cpuid.cc:64
gem5::X86ISA::X86CPUID::vendorString
const std::string vendorString
Definition
cpuid.hh:106
gem5::X86ISA::X86CPUID::stringToRegister
uint64_t stringToRegister(const char *str)
Definition
cpuid.cc:134
gem5::X86ISA::X86CPUID::X86CPUID
X86CPUID(const std::string &vendor, const std::string &name)
Definition
cpuid.cc:42
std::vector
STL vector class.
Definition
stl.hh:37
gem5::X86ISA::ExtendedCpuidFunctions
ExtendedCpuidFunctions
Definition
cpuid.hh:60
gem5::X86ISA::NameString3
@ NameString3
Definition
cpuid.hh:65
gem5::X86ISA::LongModeAddressSize
@ LongModeAddressSize
Definition
cpuid.hh:69
gem5::X86ISA::VendorAndLargestExtFunc
@ VendorAndLargestExtFunc
Definition
cpuid.hh:61
gem5::X86ISA::NameString1
@ NameString1
Definition
cpuid.hh:63
gem5::X86ISA::NumExtendedCpuidFuncs
@ NumExtendedCpuidFuncs
Definition
cpuid.hh:70
gem5::X86ISA::NameString2
@ NameString2
Definition
cpuid.hh:64
gem5::X86ISA::FamilyModelSteppingBrandFeatures
@ FamilyModelSteppingBrandFeatures
Definition
cpuid.hh:62
gem5::X86ISA::L1CacheAndTLB
@ L1CacheAndTLB
Definition
cpuid.hh:66
gem5::X86ISA::L2L3CacheAndL2TLB
@ L2L3CacheAndL2TLB
Definition
cpuid.hh:67
gem5::X86ISA::APMInfo
@ APMInfo
Definition
cpuid.hh:68
gem5::X86ISA::StandardCpuidFunction
StandardCpuidFunction
Definition
cpuid.hh:46
gem5::X86ISA::CacheAndTLB
@ CacheAndTLB
Definition
cpuid.hh:49
gem5::X86ISA::FamilyModelStepping
@ FamilyModelStepping
Definition
cpuid.hh:48
gem5::X86ISA::ThermalPowerMgmt
@ ThermalPowerMgmt
Definition
cpuid.hh:53
gem5::X86ISA::ExtendedFeatures
@ ExtendedFeatures
Definition
cpuid.hh:54
gem5::X86ISA::CacheParams
@ CacheParams
Definition
cpuid.hh:51
gem5::X86ISA::VendorAndLargestStdFunc
@ VendorAndLargestStdFunc
Definition
cpuid.hh:47
gem5::X86ISA::ExtendedState
@ ExtendedState
Definition
cpuid.hh:55
gem5::X86ISA::NumStandardCpuidFuncs
@ NumStandardCpuidFuncs
Definition
cpuid.hh:56
gem5::X86ISA::SerialNumber
@ SerialNumber
Definition
cpuid.hh:50
gem5::X86ISA::MonitorMwait
@ MonitorMwait
Definition
cpuid.hh:52
gem5::X86ISA::nameStringSize
constexpr int nameStringSize
Definition
cpuid.hh:73
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition
types.hh:98
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::X86ISA::CpuidResult
Definition
cpuid.hh:76
gem5::X86ISA::CpuidResult::rbx
uint64_t rbx
Definition
cpuid.hh:78
gem5::X86ISA::CpuidResult::CpuidResult
CpuidResult()
Definition
cpuid.hh:89
gem5::X86ISA::CpuidResult::rdx
uint64_t rdx
Definition
cpuid.hh:80
gem5::X86ISA::CpuidResult::rax
uint64_t rax
Definition
cpuid.hh:77
gem5::X86ISA::CpuidResult::CpuidResult
CpuidResult(uint64_t _rax, uint64_t _rbx, uint64_t _rdx, uint64_t _rcx)
Definition
cpuid.hh:84
gem5::X86ISA::CpuidResult::rcx
uint64_t rcx
Definition
cpuid.hh:79
name
const std::string & name()
Definition
trace.cc:48
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