cpuid.cc File Reference

#include "arch/x86/cpuid.hh"
#include "arch/x86/isa.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::X86ISA
	This is exposed globally, independent of the ISA.

Enumerations
enum	gem5::X86ISA::StandardCpuidFunction {   gem5::X86ISA::VendorAndLargestStdFunc , gem5::X86ISA::FamilyModelStepping , gem5::X86ISA::CacheAndTLB , gem5::X86ISA::SerialNumber ,   gem5::X86ISA::CacheParams , gem5::X86ISA::MonitorMwait , gem5::X86ISA::ThermalPowerMgmt , gem5::X86ISA::ExtendedFeatures ,   gem5::X86ISA::NumStandardCpuidFuncs }
enum	gem5::X86ISA::ExtendedCpuidFunctions {   gem5::X86ISA::VendorAndLargestExtFunc , gem5::X86ISA::FamilyModelSteppingBrandFeatures , gem5::X86ISA::NameString1 , gem5::X86ISA::NameString2 ,   gem5::X86ISA::NameString3 , gem5::X86ISA::L1CacheAndTLB , gem5::X86ISA::L2L3CacheAndL2TLB , gem5::X86ISA::APMInfo ,   gem5::X86ISA::LongModeAddressSize , gem5::X86ISA::NumExtendedCpuidFuncs }

Functions
uint64_t	gem5::X86ISA::stringToRegister (const char *str)
bool	gem5::X86ISA::doCpuid (ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)

Variables
static const int	gem5::X86ISA::nameStringSize = 48
static const char	gem5::X86ISA::nameString [nameStringSize] = "Fake M5 x86_64 CPU"