gem5  v22.0.0.1
dramsim3.hh
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38 
43 #ifndef __MEM_DRAMSIM3_HH__
44 #define __MEM_DRAMSIM3_HH__
45 
46 #include <functional>
47 #include <queue>
48 #include <unordered_map>
49 
50 #include "mem/abstract_mem.hh"
51 #include "mem/dramsim3_wrapper.hh"
52 #include "mem/qport.hh"
53 #include "params/DRAMsim3.hh"
54 
55 namespace gem5
56 {
57 
58 namespace memory
59 {
60 
61 class DRAMsim3 : public AbstractMemory
62 {
63  private:
64 
70  class MemoryPort : public ResponsePort
71  {
72 
73  private:
74 
76 
77  public:
78 
79  MemoryPort(const std::string& _name, DRAMsim3& _memory);
80 
81  protected:
82 
84 
85  void recvFunctional(PacketPtr pkt);
86 
87  bool recvTimingReq(PacketPtr pkt);
88 
89  void recvRespRetry();
90 
92 
93  };
94 
96 
100  std::function<void(uint64_t)> read_cb;
101  std::function<void(uint64_t)> write_cb;
102 
107 
111  bool retryReq;
112 
116  bool retryResp;
117 
122 
129  std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
130  std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
131 
137  unsigned int nbrOutstandingReads;
138  unsigned int nbrOutstandingWrites;
139 
146 
147 
148  unsigned int nbrOutstanding() const;
149 
157  void accessAndRespond(PacketPtr pkt);
158 
159  void sendResponse();
160 
165 
169  void tick();
170 
175 
180  std::unique_ptr<Packet> pendingDelete;
181 
182  public:
183 
184  typedef DRAMsim3Params Params;
185  DRAMsim3(const Params &p);
186 
194  void readComplete(unsigned id, uint64_t addr);
195 
203  void writeComplete(unsigned id, uint64_t addr);
204 
205  DrainState drain() override;
206 
207  virtual Port& getPort(const std::string& if_name,
208  PortID idx = InvalidPortID) override;
209 
210  void init() override;
211  void startup() override;
212 
213  void resetStats() override;
214 
215  protected:
216 
218  void recvFunctional(PacketPtr pkt);
219  bool recvTimingReq(PacketPtr pkt);
220  void recvRespRetry();
221 
222 };
223 
224 } // namespace memory
225 } // namespace gem5
226 
227 #endif // __MEM_DRAMSIM3_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::memory::DRAMsim3::MemoryPort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: dramsim3.cc:364
gem5::memory::DRAMsim3::nbrOutstandingWrites
unsigned int nbrOutstandingWrites
Definition: dramsim3.hh:138
gem5::memory::DRAMsim3::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: dramsim3.hh:180
gem5::memory::DRAMsim3::outstandingWrites
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingWrites
Definition: dramsim3.hh:130
gem5::memory::DRAMsim3::resetStats
void resetStats() override
Callback to reset stats.
Definition: dramsim3.cc:100
gem5::memory::DRAMsim3::outstandingReads
std::unordered_map< Addr, std::queue< PacketPtr > > outstandingReads
Keep track of what packets are outstanding per address, and do so separately for reads and writes.
Definition: dramsim3.hh:129
memory
Definition: mem.h:38
abstract_mem.hh
gem5::memory::DRAMsim3::MemoryPort::recvRespRetry
void recvRespRetry()
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: dramsim3.cc:391
gem5::memory::DRAMsim3::read_cb
std::function< void(uint64_t)> read_cb
Callback functions.
Definition: dramsim3.hh:100
gem5::memory::DRAMsim3::tick
void tick()
Progress the controller one clock cycle.
Definition: dramsim3.cc:141
gem5::memory::DRAMsim3::retryResp
bool retryResp
Are we waiting for a retry for sending a response.
Definition: dramsim3.hh:116
gem5::memory::DRAMsim3::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: dramsim3.cc:160
gem5::memory::DRAMsim3::nbrOutstandingReads
unsigned int nbrOutstandingReads
Count the number of outstanding transactions so that we can block any further requests until there is...
Definition: dramsim3.hh:137
gem5::memory::DRAMsim3::MemoryPort::MemoryPort
MemoryPort(const std::string &_name, DRAMsim3 &_memory)
Definition: dramsim3.cc:358
gem5::memory::DRAMsim3::MemoryPort
The memory port has to deal with its own flow control to avoid having unbounded storage that is impli...
Definition: dramsim3.hh:70
gem5::memory::DRAMsim3::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: dramsim3.cc:341
gem5::memory::DRAMsim3::sendResponse
void sendResponse()
Definition: dramsim3.cc:105
gem5::memory::DRAMsim3::MemoryPort::recvFunctional
void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: dramsim3.cc:378
gem5::memory::DRAMsim3::writeComplete
void writeComplete(unsigned id, uint64_t addr)
Write completion callback.
Definition: dramsim3.cc:318
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::memory::DRAMsim3::write_cb
std::function< void(uint64_t)> write_cb
Definition: dramsim3.hh:101
gem5::memory::DRAMsim3::nbrOutstanding
unsigned int nbrOutstanding() const
Definition: dramsim3.cc:135
gem5::memory::DRAMsim3::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: dramsim3.cc:91
gem5::memory::DRAMsim3::retryReq
bool retryReq
Is the connected port waiting for a retry from us.
Definition: dramsim3.hh:111
gem5::memory::DRAMsim3
Definition: dramsim3.hh:61
gem5::memory::DRAMsim3::startTick
Tick startTick
Keep track of when the wrapper is started.
Definition: dramsim3.hh:121
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::memory::DRAMsim3::recvRespRetry
void recvRespRetry()
Definition: dramsim3.cc:246
gem5::memory::DRAMsim3::wrapper
DRAMsim3Wrapper wrapper
The actual DRAMsim3 wrapper.
Definition: dramsim3.hh:106
gem5::memory::DRAMsim3::DRAMsim3
DRAMsim3(const Params &p)
Definition: dramsim3.cc:52
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
dramsim3_wrapper.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::memory::DRAMsim3::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: dramsim3.cc:75
gem5::memory::DRAMsim3::MemoryPort::mem
DRAMsim3 & mem
Definition: dramsim3.hh:75
gem5::memory::DRAMsim3::responseQueue
std::deque< PacketPtr > responseQueue
Queue to hold response packets until we can send them back.
Definition: dramsim3.hh:145
gem5::memory::DRAMsim3::tickEvent
EventFunctionWrapper tickEvent
Event to schedule clock ticks.
Definition: dramsim3.hh:174
gem5::memory::DRAMsim3::readComplete
void readComplete(unsigned id, uint64_t addr)
Read completion callback.
Definition: dramsim3.cc:292
gem5::memory::DRAMsim3::accessAndRespond
void accessAndRespond(PacketPtr pkt)
When a packet is ready, use the "access()" method in AbstractMemory to actually create the response p...
Definition: dramsim3.cc:256
gem5::memory::DRAMsim3::Params
DRAMsim3Params Params
Definition: dramsim3.hh:184
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::memory::DRAMsim3Wrapper
Wrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world...
Definition: dramsim3_wrapper.hh:73
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
qport.hh
gem5::memory::DRAMsim3::recvFunctional
void recvFunctional(PacketPtr pkt)
Definition: dramsim3.cc:169
gem5::memory::DRAMsim3::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: dramsim3.cc:183
std::deque
STL deque class.
Definition: stl.hh:44
gem5::memory::DRAMsim3::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: dramsim3.cc:351
std::list< AddrRange >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::memory::DRAMsim3::MemoryPort::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: dramsim3.cc:372
gem5::memory::DRAMsim3::sendResponseEvent
EventFunctionWrapper sendResponseEvent
Event to schedule sending of responses.
Definition: dramsim3.hh:164
gem5::memory::DRAMsim3::port
MemoryPort port
Definition: dramsim3.hh:95
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::memory::DRAMsim3::MemoryPort::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the peer.
Definition: dramsim3.cc:384

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