fp16_e5m10.hh

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#ifndef __ARCH_AMDGPU_COMMON_DTYPE_FP16_E5M10_HH__
#define __ARCH_AMDGPU_COMMON_DTYPE_FP16_E5M10_HH__
 
#include <cassert>
 
namespace gem5
{
 
namespace AMDGPU
{
 
typedef union
{
    enum bitSizes
    {
        ebits = 5,
        mbits = 10,
        sbits = 1,
        zbits = 16,
        bias = 15,
 
        inf = 0x7c000000,
        nan = 0x7c100000,
        max = 0x7bff0000
    };
 
    uint32_t storage;
    struct
    {
        unsigned zero : zbits;
        unsigned mant : mbits;
        unsigned exp  : ebits;
        unsigned sign : sbits;
    };
} fp16_e5m10_info;
static_assert(sizeof(fp16_e5m10_info) == 4);
 
} // namespace AMDGPU
 
} // namespace gem5
 
 
// std library cmath definitions
namespace std
{
 
constexpr bool isinf(gem5::AMDGPU::fp16_e5m10_info a)
{
    return a.exp == 0x1F && a.mant == 0;
}
 
constexpr bool isnan(gem5::AMDGPU::fp16_e5m10_info a)
{
    return a.exp == 0x1F && a.mant != 0;
}
 
constexpr bool isnormal(gem5::AMDGPU::fp16_e5m10_info a)
{
    return !(a.exp == 0 && a.mant != 0);
}
 
template<>
class numeric_limits<gem5::AMDGPU::fp16_e5m10_info>
{
  public:
    static constexpr bool has_quiet_NaN = true;
    static gem5::AMDGPU::fp16_e5m10_info quiet_NaN()
    {
        assert(has_quiet_NaN);
        gem5::AMDGPU::fp16_e5m10_info tmp;
        tmp.storage = gem5::AMDGPU::fp16_e5m10_info::nan;
        return tmp;
    }
 
    static constexpr bool has_infinity = true;
    static gem5::AMDGPU::fp16_e5m10_info infinity()
    {
        assert(has_infinity);
        gem5::AMDGPU::fp16_e5m10_info tmp;
        tmp.storage = gem5::AMDGPU::fp16_e5m10_info::inf;
        return tmp;
    }
 
    static gem5::AMDGPU::fp16_e5m10_info max()
    {
        gem5::AMDGPU::fp16_e5m10_info tmp;
        tmp.storage = gem5::AMDGPU::fp16_e5m10_info::max;
        return tmp;
    }
};
 
} // namespace std
 
#endif // __ARCH_AMDGPU_COMMON_DTYPE_FP16_E5M10_HH__