gem5
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sim
globals.hh
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/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* Copyright (c) 2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SIM_GLOBALS_HH__
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#define __SIM_GLOBALS_HH__
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#include "
base/types.hh
"
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#include "
sim/serialize.hh
"
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namespace
gem5
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{
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class
Globals
:
public
Serializable
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{
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public
:
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Globals
() :
unserializedCurTick
(0) {}
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~Globals
() =
default
;
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void
serialize
(
CheckpointOut
&cp)
const override
;
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void
unserialize
(
CheckpointIn
&cp)
override
;
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Tick
unserializedCurTick
;
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};
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}
// namespace gem5
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#endif
// __SIM_GLOBALS_HH__
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
gem5::CheckpointIn
Definition
serialize.hh:69
gem5::Globals
Container for serializing global variables (not associated with any serialized object).
Definition
globals.hh:55
gem5::Globals::~Globals
~Globals()=default
gem5::Globals::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition
globals.cc:59
gem5::Globals::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition
globals.cc:66
gem5::Globals::Globals
Globals()
Definition
globals.hh:57
gem5::Globals::unserializedCurTick
Tick unserializedCurTick
Definition
globals.hh:63
gem5::Serializable
Basic support for object serialization.
Definition
serialize.hh:170
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::CheckpointOut
std::ostream CheckpointOut
Definition
serialize.hh:66
gem5::Tick
uint64_t Tick
Tick count type.
Definition
types.hh:58
serialize.hh
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