hw_scheduler.hh

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/*
 * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
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 * this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright notice,
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#ifndef __DEV_HSA_HW_SCHEDULER_HH__
#define __DEV_HSA_HW_SCHEDULER_HH__
 
#include <cstdint>
#include <map>
 
#include "base/types.hh"
#include "dev/hsa/hsa_packet_processor.hh"
#include "enums/GfxVersion.hh"
#include "sim/eventq.hh"
 
// We allocate one PIO page for doorbells and each
// address is 8 bytes
#define MAX_ACTIVE_QUEUES (PAGE_SIZE/8)
 
namespace gem5
{
 
class HWScheduler
{
  public:
    HWScheduler(HSAPacketProcessor* hsa_pp, Tick wakeup_delay)
               : hsaPP(hsa_pp), nextALId(0), nextRLId(0),
                 wakeupDelay(wakeup_delay), schedWakeupEvent(this)
    {}
    void write(Addr db_addr, uint64_t doorbell_reg);
    void registerNewQueue(uint64_t hostReadIndexPointer,
                          uint64_t basePointer,
                          uint64_t queue_id,
                          uint32_t size, int doorbellSize,
                          GfxVersion gfxVersion,
                          Addr offset = 0, uint64_t rd_idx = 0);
    void unregisterQueue(uint64_t queue_id, int doorbellSize);
    void wakeup();
    void schedWakeup();
    class SchedulerWakeupEvent : public Event
    {
      private:
        HWScheduler *hwSchdlr;
      public:
        SchedulerWakeupEvent(HWScheduler *hw_schdlr) : hwSchdlr(hw_schdlr) {}
        virtual void process();
        virtual const char *description() const;
    };
    bool isRLQIdle(uint32_t rl_idx);
    bool findNextActiveALQ();
    bool findNextIdleRLQ();
    bool unmapQFromRQ();
    bool contextSwitchQ();
    bool findEmptyHWQ();
    bool mapQIfSlotAvlbl(uint32_t al_idx, AQLRingBuffer* aql_buf,
                         HSAQueueDescriptor* q_desc);
    void addQCntxt(uint32_t al_idx, AQLRingBuffer* aql_buf,
                   HSAQueueDescriptor* q_desc);
    void removeQCntxt();
    void scheduleAndWakeupMappedQ();
    void updateRRVars(uint32_t al_idx, uint32_t rl_idx);
 
  private:
    // Active list keeps track of all queues created
    std::map<uint32_t, QCntxt> activeList;
    //TODO: Modify this to support multi-process in the future.
    // doorbell map, maps doorbell offsets to queue ID
    std::map<Addr, uint32_t> dbMap;
    // Reverse of doorbell map, maps queue ID to doorbell offset
    std::map<uint64_t, Addr> qidMap;
    // regdListMap keeps track of the mapping of queues to
    // registered list. regdListMap is indexed with active
    // list index (which is same as queue ID)
    std::map<uint32_t, uint32_t> regdListMap;
    HSAPacketProcessor* hsaPP;
 
    // Scheduling information.
    // For now, this is simple round robin but
    // this will be changed to a sophisticated logic
    // in the future. So, in the future, we will
    // move these variables into a scheduler class
    uint32_t nextALId;
    uint32_t nextRLId;
    const Tick wakeupDelay;
    SchedulerWakeupEvent schedWakeupEvent;
};
 
} // namespace gem5
 
#endif // __DEV_HSA_HW_SCHEDULER_HH__