gem5  v22.0.0.1
hw_scheduler.hh
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31 
32 #ifndef __DEV_HSA_HW_SCHEDULER_HH__
33 #define __DEV_HSA_HW_SCHEDULER_HH__
34 
35 #include <cstdint>
36 #include <map>
37 
38 #include "base/types.hh"
40 #include "enums/GfxVersion.hh"
41 #include "sim/eventq.hh"
42 
43 // We allocate one PIO page for doorbells and each
44 // address is 8 bytes
45 #define MAX_ACTIVE_QUEUES (PAGE_SIZE/8)
46 
47 namespace gem5
48 {
49 
51 {
52  public:
53  HWScheduler(HSAPacketProcessor* hsa_pp, Tick wakeup_delay)
54  : hsaPP(hsa_pp), nextALId(0), nextRLId(0),
55  wakeupDelay(wakeup_delay), schedWakeupEvent(this)
56  {}
57  void write(Addr db_addr, uint64_t doorbell_reg);
58  void registerNewQueue(uint64_t hostReadIndexPointer,
59  uint64_t basePointer,
60  uint64_t queue_id,
61  uint32_t size, int doorbellSize,
62  GfxVersion gfxVersion,
63  Addr offset = 0, uint64_t rd_idx = 0);
64  void unregisterQueue(uint64_t queue_id, int doorbellSize);
65  void wakeup();
66  void schedWakeup();
67  class SchedulerWakeupEvent : public Event
68  {
69  private:
71  public:
72  SchedulerWakeupEvent(HWScheduler *hw_schdlr) : hwSchdlr(hw_schdlr) {}
73  virtual void process();
74  virtual const char *description() const;
75  };
76  bool isRLQIdle(uint32_t rl_idx);
77  bool findNextActiveALQ();
78  bool findNextIdleRLQ();
79  bool unmapQFromRQ();
80  bool contextSwitchQ();
81  bool findEmptyHWQ();
82  bool mapQIfSlotAvlbl(uint32_t al_idx, AQLRingBuffer* aql_buf,
83  HSAQueueDescriptor* q_desc);
84  void addQCntxt(uint32_t al_idx, AQLRingBuffer* aql_buf,
85  HSAQueueDescriptor* q_desc);
86  void removeQCntxt();
88  void updateRRVars(uint32_t al_idx, uint32_t rl_idx);
89 
90  private:
91  // Active list keeps track of all queues created
92  std::map<uint32_t, QCntxt> activeList;
93  //TODO: Modify this to support multi-process in the future.
94  // doorbell map, maps doorbell offsets to queue ID
95  std::map<Addr, uint32_t> dbMap;
96  // Reverse of doorbell map, maps queue ID to doorbell offset
97  std::map<uint64_t, Addr> qidMap;
98  // regdListMap keeps track of the mapping of queues to
99  // registered list. regdListMap is indexed with active
100  // list index (which is same as queue ID)
101  std::map<uint32_t, uint32_t> regdListMap;
103 
104  // Scheduling information.
105  // For now, this is simple round robin but
106  // this will be changed to a sophisticated logic
107  // in the future. So, in the future, we will
108  // move these variables into a scheduler class
109  uint32_t nextALId;
110  uint32_t nextRLId;
113 };
114 
115 } // namespace gem5
116 
117 #endif // __DEV_HSA_HW_SCHEDULER_HH__
gem5::HWScheduler::SchedulerWakeupEvent::process
virtual void process()
Definition: hw_scheduler.cc:52
gem5::HWScheduler::nextRLId
uint32_t nextRLId
Definition: hw_scheduler.hh:110
gem5::HWScheduler::SchedulerWakeupEvent::description
virtual const char * description() const
Return a C string describing the event.
gem5::HWScheduler::removeQCntxt
void removeQCntxt()
Definition: hw_scheduler.cc:250
gem5::HWScheduler::SchedulerWakeupEvent::SchedulerWakeupEvent
SchedulerWakeupEvent(HWScheduler *hw_schdlr)
Definition: hw_scheduler.hh:72
gem5::HWScheduler::dbMap
std::map< Addr, uint32_t > dbMap
Definition: hw_scheduler.hh:95
gem5::HWScheduler::findEmptyHWQ
bool findEmptyHWQ()
Definition: hw_scheduler.cc:138
gem5::HWScheduler::wakeup
void wakeup()
Definition: hw_scheduler.cc:58
gem5::HWScheduler::unmapQFromRQ
bool unmapQFromRQ()
Definition: hw_scheduler.cc:238
hsa_packet_processor.hh
gem5::HWScheduler::findNextActiveALQ
bool findNextActiveALQ()
Definition: hw_scheduler.cc:270
gem5::HWScheduler::isRLQIdle
bool isRLQIdle(uint32_t rl_idx)
Definition: hw_scheduler.cc:306
gem5::HWScheduler::contextSwitchQ
bool contextSwitchQ()
Definition: hw_scheduler.cc:201
gem5::HWScheduler::schedWakeup
void schedWakeup()
Definition: hw_scheduler.cc:72
gem5::HSAPacketProcessor
Definition: hsa_packet_processor.hh:252
gem5::Event
Definition: eventq.hh:251
gem5::HWScheduler::registerNewQueue
void registerNewQueue(uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size, int doorbellSize, GfxVersion gfxVersion, Addr offset=0, uint64_t rd_idx=0)
Definition: hw_scheduler.cc:85
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::HWScheduler::SchedulerWakeupEvent
Definition: hw_scheduler.hh:67
gem5::HSAQueueDescriptor
Definition: hsa_packet_processor.hh:78
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::HWScheduler::unregisterQueue
void unregisterQueue(uint64_t queue_id, int doorbellSize)
Definition: hw_scheduler.cc:353
gem5::HWScheduler::mapQIfSlotAvlbl
bool mapQIfSlotAvlbl(uint32_t al_idx, AQLRingBuffer *aql_buf, HSAQueueDescriptor *q_desc)
Definition: hw_scheduler.cc:160
gem5::HWScheduler::qidMap
std::map< uint64_t, Addr > qidMap
Definition: hw_scheduler.hh:97
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::HWScheduler
Definition: hw_scheduler.hh:50
gem5::HWScheduler::findNextIdleRLQ
bool findNextIdleRLQ()
Definition: hw_scheduler.cc:292
gem5::HWScheduler::activeList
std::map< uint32_t, QCntxt > activeList
Definition: hw_scheduler.hh:92
gem5::HWScheduler::addQCntxt
void addQCntxt(uint32_t al_idx, AQLRingBuffer *aql_buf, HSAQueueDescriptor *q_desc)
Definition: hw_scheduler.cc:186
gem5::HWScheduler::HWScheduler
HWScheduler(HSAPacketProcessor *hsa_pp, Tick wakeup_delay)
Definition: hw_scheduler.hh:53
gem5::HWScheduler::nextALId
uint32_t nextALId
Definition: hw_scheduler.hh:109
types.hh
gem5::HWScheduler::hsaPP
HSAPacketProcessor * hsaPP
Definition: hw_scheduler.hh:102
gem5::HWScheduler::scheduleAndWakeupMappedQ
void scheduleAndWakeupMappedQ()
Definition: hw_scheduler.cc:175
gem5::AQLRingBuffer
Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer.
Definition: hsa_packet_processor.hh:156
gem5::HWScheduler::wakeupDelay
const Tick wakeupDelay
Definition: hw_scheduler.hh:111
gem5::HWScheduler::updateRRVars
void updateRRVars(uint32_t al_idx, uint32_t rl_idx)
Definition: hw_scheduler.cc:231
gem5::HWScheduler::SchedulerWakeupEvent::hwSchdlr
HWScheduler * hwSchdlr
Definition: hw_scheduler.hh:70
gem5::HWScheduler::schedWakeupEvent
SchedulerWakeupEvent schedWakeupEvent
Definition: hw_scheduler.hh:112
gem5::HWScheduler::write
void write(Addr db_addr, uint64_t doorbell_reg)
Definition: hw_scheduler.cc:329
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::HWScheduler::regdListMap
std::map< uint32_t, uint32_t > regdListMap
Definition: hw_scheduler.hh:101
eventq.hh

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