gem5  v22.1.0.0
hw_scheduler.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef __DEV_HSA_HW_SCHEDULER_HH__
33 #define __DEV_HSA_HW_SCHEDULER_HH__
34 
35 #include <cstdint>
36 #include <map>
37 
38 #include "base/types.hh"
40 #include "enums/GfxVersion.hh"
41 #include "sim/eventq.hh"
42 
43 // We allocate one PIO page for doorbells and each
44 // address is 8 bytes
45 #define MAX_ACTIVE_QUEUES (PAGE_SIZE/8)
46 
47 namespace gem5
48 {
49 
51 {
52  public:
53  HWScheduler(HSAPacketProcessor* hsa_pp, Tick wakeup_delay)
54  : hsaPP(hsa_pp), nextALId(0), nextRLId(0),
55  wakeupDelay(wakeup_delay), schedWakeupEvent(this)
56  {}
57  void write(Addr db_addr, uint64_t doorbell_reg);
58  void registerNewQueue(uint64_t hostReadIndexPointer,
59  uint64_t basePointer,
60  uint64_t queue_id,
61  uint32_t size, int doorbellSize,
62  GfxVersion gfxVersion,
63  Addr offset = 0, uint64_t rd_idx = 0);
64  void unregisterQueue(uint64_t queue_id, int doorbellSize);
65  void wakeup();
66  void schedWakeup();
67  class SchedulerWakeupEvent : public Event
68  {
69  private:
71  public:
72  SchedulerWakeupEvent(HWScheduler *hw_schdlr) : hwSchdlr(hw_schdlr) {}
73  virtual void process();
74  virtual const char *description() const;
75  };
76  bool isRLQIdle(uint32_t rl_idx);
77  bool findNextActiveALQ();
78  bool findNextIdleRLQ();
79  bool unmapQFromRQ();
80  bool contextSwitchQ();
81  bool findEmptyHWQ();
82  bool mapQIfSlotAvlbl(uint32_t al_idx, AQLRingBuffer* aql_buf,
83  HSAQueueDescriptor* q_desc);
84  void addQCntxt(uint32_t al_idx, AQLRingBuffer* aql_buf,
85  HSAQueueDescriptor* q_desc);
86  void removeQCntxt();
88  void updateRRVars(uint32_t al_idx, uint32_t rl_idx);
89 
90  private:
91  // Active list keeps track of all queues created
92  std::map<uint32_t, QCntxt> activeList;
93  //TODO: Modify this to support multi-process in the future.
94  // doorbell map, maps doorbell offsets to queue ID
95  std::map<Addr, uint32_t> dbMap;
96  // Reverse of doorbell map, maps queue ID to doorbell offset
97  std::map<uint64_t, Addr> qidMap;
98  // regdListMap keeps track of the mapping of queues to
99  // registered list. regdListMap is indexed with active
100  // list index (which is same as queue ID)
101  std::map<uint32_t, uint32_t> regdListMap;
103 
104  // Scheduling information.
105  // For now, this is simple round robin but
106  // this will be changed to a sophisticated logic
107  // in the future. So, in the future, we will
108  // move these variables into a scheduler class
109  uint32_t nextALId;
110  uint32_t nextRLId;
113 };
114 
115 } // namespace gem5
116 
117 #endif // __DEV_HSA_HW_SCHEDULER_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer.
SchedulerWakeupEvent(HWScheduler *hw_schdlr)
Definition: hw_scheduler.hh:72
virtual const char * description() const
Return a C string describing the event.
HWScheduler(HSAPacketProcessor *hsa_pp, Tick wakeup_delay)
Definition: hw_scheduler.hh:53
void unregisterQueue(uint64_t queue_id, int doorbellSize)
SchedulerWakeupEvent schedWakeupEvent
void addQCntxt(uint32_t al_idx, AQLRingBuffer *aql_buf, HSAQueueDescriptor *q_desc)
void updateRRVars(uint32_t al_idx, uint32_t rl_idx)
void registerNewQueue(uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size, int doorbellSize, GfxVersion gfxVersion, Addr offset=0, uint64_t rd_idx=0)
Definition: hw_scheduler.cc:85
std::map< uint32_t, uint32_t > regdListMap
void scheduleAndWakeupMappedQ()
std::map< Addr, uint32_t > dbMap
Definition: hw_scheduler.hh:95
std::map< uint32_t, QCntxt > activeList
Definition: hw_scheduler.hh:92
bool isRLQIdle(uint32_t rl_idx)
const Tick wakeupDelay
void write(Addr db_addr, uint64_t doorbell_reg)
HSAPacketProcessor * hsaPP
std::map< uint64_t, Addr > qidMap
Definition: hw_scheduler.hh:97
bool mapQIfSlotAvlbl(uint32_t al_idx, AQLRingBuffer *aql_buf, HSAQueueDescriptor *q_desc)
Bitfield< 23, 0 > offset
Definition: types.hh:144
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
uint64_t Tick
Tick count type.
Definition: types.hh:58

Generated on Wed Dec 21 2022 10:22:33 for gem5 by doxygen 1.9.1