gem5  v21.1.0.2
hsa_packet_processor.hh
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33 
34 #ifndef __DEV_HSA_HSA_PACKET_PROCESSOR__
35 #define __DEV_HSA_HSA_PACKET_PROCESSOR__
36 
37 #include <algorithm>
38 #include <cstdint>
39 #include <vector>
40 
41 #include "base/types.hh"
42 #include "dev/dma_virt_device.hh"
43 #include "dev/hsa/hsa.h"
44 #include "dev/hsa/hsa_queue.hh"
45 #include "params/HSAPacketProcessor.hh"
46 #include "sim/eventq.hh"
47 
48 #define AQL_PACKET_SIZE 64
49 #define PAGE_SIZE 4096
50 #define NUM_DMA_BUFS 16
51 #define DMA_BUF_SIZE (AQL_PACKET_SIZE * NUM_DMA_BUFS)
52 // HSA runtime supports only 5 signals per barrier packet
53 #define NumSignalsPerBarrier 5
54 
55 namespace gem5
56 {
57 
58 // Ideally, each queue should store this status and
59 // the processPkt() should make decisions based on that
60 // status variable.
61 enum Q_STATE
62 {
63  UNBLOCKED = 0, // Unblocked queue, can submit packets.
64  BLOCKED_BBIT, // Queue blocked by barrier bit.
65  // Can submit packet packets after
66  // previous packet completes.
67  BLOCKED_BPKT, // Queue blocked by barrier packet.
68  // Can submit packet packets after
69  // barrier packet completes.
70 };
71 
72 class GPUCommandProcessor;
73 class HWScheduler;
74 
75 // Our internal representation of an HSA queue
77 {
78  public:
79  uint64_t basePointer;
80  uint64_t doorbellPointer;
81  uint64_t writeIndex;
82  uint64_t readIndex;
83  uint32_t numElts;
84  uint64_t hostReadIndexPtr;
87 
88  HSAQueueDescriptor(uint64_t base_ptr, uint64_t db_ptr,
89  uint64_t hri_ptr, uint32_t size)
90  : basePointer(base_ptr), doorbellPointer(db_ptr),
91  writeIndex(0), readIndex(0),
92  numElts(size / AQL_PACKET_SIZE), hostReadIndexPtr(hri_ptr),
94  dmaInProgress(false)
95  { }
96  uint64_t spaceRemaining() { return numElts - (writeIndex - readIndex); }
97  uint64_t spaceUsed() { return writeIndex - readIndex; }
98  uint32_t objSize() { return AQL_PACKET_SIZE; }
99  uint32_t numObjs() { return numElts; }
100  bool isFull() { return spaceRemaining() == 0; }
101  bool isEmpty() { return spaceRemaining() == numElts; }
102 
103  uint64_t ptr(uint64_t ix)
104  {
111  assert(ix % numElts < 0x1000);
112  return basePointer +
113  ((ix % numElts) * objSize());
114  }
115 };
116 
130 {
131  private:
133  std::string _name;
136  uint64_t _wrIdx; // Points to next write location
137  uint64_t _rdIdx; // Read pointer of AQL buffer
138  uint64_t _dispIdx; // Dispatch pointer of AQL buffer
139 
140  public:
141  std::string name() {return _name;}
142  AQLRingBuffer(uint32_t size, const std::string name);
143  int allocEntry(uint32_t nBufReq);
144  bool freeEntry(void *pkt);
145 
155  void
156  saveHostDispAddr(Addr host_pkt_addr, int num_pkts, int ix)
157  {
158  for (int i = 0; i < num_pkts; ++i) {
159  _hostDispAddresses[ix % numObjs()] = host_pkt_addr + i * objSize();
160  ++ix;
161  }
162  }
163 
164  Addr
165  hostDispAddr() const
166  {
167  return _hostDispAddresses[dispIdx() % numObjs()];
168  }
169 
170  bool
171  dispPending() const
172  {
173  int packet_type = (_aqlBuf[_dispIdx % _aqlBuf.size()].header
175  ((1 << HSA_PACKET_HEADER_WIDTH_TYPE) - 1);
176  return (_dispIdx < _wrIdx) && packet_type != HSA_PACKET_TYPE_INVALID;
177  }
178 
187  bool
189  {
190  for (int i = _rdIdx + 1; i < _dispIdx; i++) {
191  if (!_aqlComplete[i % _aqlBuf.size()]) {
192  return false;
193  }
194  }
195  return !_aqlComplete[_rdIdx % _aqlBuf.size()] && _rdIdx != _dispIdx;
196  }
197 
198  uint32_t nFree() const { return _aqlBuf.size() - (_wrIdx - _rdIdx); }
199  void *ptr(uint32_t ix) { return _aqlBuf.data() + (ix % _aqlBuf.size()); }
200  uint32_t numObjs() const { return _aqlBuf.size(); };
201  uint32_t objSize() const { return AQL_PACKET_SIZE; }
202  uint64_t dispIdx() const { return _dispIdx; }
203  uint64_t wrIdx() const { return _wrIdx; }
204  uint64_t rdIdx() const { return _rdIdx; }
205  uint64_t* rdIdxPtr() { return &_rdIdx; }
206  void incRdIdx(uint64_t value) { _rdIdx += value; }
207  void incWrIdx(uint64_t value) { _wrIdx += value; }
208  void incDispIdx(uint64_t value) { _dispIdx += value; }
209  uint64_t compltnPending() { return (_dispIdx - _rdIdx); }
210 };
211 
212 struct QCntxt
213 {
216  // used for HSA packets that enforce synchronization with barrier bit
219  qDesc(q_desc), aqlBuf(aql_buf), barrierBit(false)
220  {}
221  QCntxt() : qDesc(NULL), aqlBuf(NULL), barrierBit(false) {}
222 };
223 
225 {
226  friend class HWScheduler;
227  protected:
228  typedef void (DmaDevice::*DmaFnPtr)(Addr, int, Event*, uint8_t*, Tick);
231 
232  // Structure to store the read values of dependency signals
233  // from shared memory. Also used for tracking the status of
234  // those reads while they are in progress
236  {
237  public:
239  : pendingReads(0), allRead(false), discardRead(false)
240  {
242  }
243  void handleReadDMA();
245  bool allRead;
246  // If this queue is unmapped when there are pending reads, then
247  // the pending reads has to be discarded.
249  // values stores the value of already read dependency signal
251  void
253  {
254  std::fill(values.begin(), values.end(), 1);
255  }
256  };
257 
258  class QueueProcessEvent : public Event
259  {
260  private:
262  uint32_t rqIdx;
263  public:
264  QueueProcessEvent(HSAPacketProcessor *_hsaPP, uint32_t _rqIdx)
265  : Event(Default_Pri), hsaPP(_hsaPP), rqIdx(_rqIdx)
266  {}
267  virtual void process();
268  virtual const char *description() const;
269  };
270 
271  // Registered queue list entry; each entry has one queueDescriptor and
272  // associated AQL buffer
273  class RQLEntry
274  {
275  public:
276  RQLEntry(HSAPacketProcessor *hsaPP, uint32_t rqIdx)
277  : aqlProcessEvent(hsaPP, rqIdx) {}
279  bool dispPending() { return qCntxt.aqlBuf->dispPending() > 0; }
280  uint64_t compltnPending() { return qCntxt.aqlBuf->compltnPending(); }
283  void setBarrierBit(bool set_val) { qCntxt.barrierBit = set_val; }
284  bool getBarrierBit() const { return qCntxt.barrierBit; }
285  bool isLastOutstandingPkt() const
286  {
288  }
289  };
290  // Keeps track of queueDescriptors of registered queues
292 
293  Q_STATE processPkt(void* pkt, uint32_t rl_idx, Addr host_pkt_addr);
294  void displayQueueDescriptor(int pid, uint32_t rl_idx);
295 
296  public:
298  getQueueDesc(uint32_t queId)
299  {
300  return regdQList.at(queId)->qCntxt.qDesc;
301  }
302  class RQLEntry*
303  getRegdListEntry(uint32_t queId)
304  {
305  return regdQList.at(queId);
306  }
307 
308  uint64_t
309  inFlightPkts(uint32_t queId)
310  {
311  auto aqlBuf = regdQList.at(queId)->qCntxt.aqlBuf;
312  return aqlBuf->dispIdx() - aqlBuf->rdIdx();
313  }
314 
320 
321  typedef HSAPacketProcessorParams Params;
322  HSAPacketProcessor(const Params &p);
324  void translateOrDie(Addr vaddr, Addr &paddr) override;
325  void setDeviceQueueDesc(uint64_t hostReadIndexPointer,
326  uint64_t basePointer,
327  uint64_t queue_id,
328  uint32_t size, int doorbellSize);
329  void unsetDeviceQueueDesc(uint64_t queue_id, int doorbellSize);
330  void setDevice(GPUCommandProcessor * dev);
331  void updateReadIndex(int, uint32_t);
332  void getCommandsFromHost(int pid, uint32_t rl_idx);
333 
334  // PIO interface
335  virtual Tick read(Packet*) override;
336  virtual Tick write(Packet*) override;
337  virtual AddrRangeList getAddrRanges() const override;
338  void finishPkt(void *pkt, uint32_t rl_idx);
339  void finishPkt(void *pkt) { finishPkt(pkt, 0); }
340  void schedAQLProcessing(uint32_t rl_idx);
341  void schedAQLProcessing(uint32_t rl_idx, Tick delay);
342 
343  void sendAgentDispatchCompletionSignal(void *pkt,
344  hsa_signal_value_t signal);
346 
351  {
352  // deal with the fact dma ops can complete out of issue order
353  uint32_t pkts_ttl;
354  uint32_t pkts_2_go;
355  uint32_t start_ix;
356  uint32_t rl_idx;
357 
358  dma_series_ctx(uint32_t _pkts_ttl,
359  uint32_t _pkts_2_go,
360  uint32_t _start_ix,
361  uint32_t _rl_idx)
362  : pkts_ttl(_pkts_2_go), pkts_2_go(_pkts_2_go),
363  start_ix(_start_ix), rl_idx(_rl_idx)
364  {};
366  };
367 
368  void updateReadDispIdDma();
369  void cmdQueueCmdDma(HSAPacketProcessor *hsaPP, int pid, bool isRead,
370  uint32_t ix_start, unsigned num_pkts,
371  dma_series_ctx *series_ctx, void *dest_4debug);
372  void handleReadDMA();
373 };
374 
375 } // namespace gem5
376 
377 #endif // __DEV_HSA_HSA_PACKET_PROCESSOR__
gem5::HSAPacketProcessor::pioDelay
Tick pioDelay
Definition: hsa_packet_processor.hh:318
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::HSAPacketProcessor::dma_series_ctx::~dma_series_ctx
~dma_series_ctx()
Definition: hsa_packet_processor.hh:365
gem5::HSAPacketProcessor::pioAddr
Addr pioAddr
Definition: hsa_packet_processor.hh:316
gem5::AQLRingBuffer::AQLRingBuffer
AQLRingBuffer(uint32_t size, const std::string name)
Definition: hsa_packet_processor.cc:571
gem5::HSAPacketProcessor::schedAQLProcessing
void schedAQLProcessing(uint32_t rl_idx)
Definition: hsa_packet_processor.cc:255
gem5::AQLRingBuffer::name
std::string name()
Definition: hsa_packet_processor.hh:141
gem5::AQLRingBuffer::allocEntry
int allocEntry(uint32_t nBufReq)
Definition: hsa_packet_processor.cc:611
gem5::HSAPacketProcessor::QueueProcessEvent::hsaPP
HSAPacketProcessor * hsaPP
Definition: hsa_packet_processor.hh:261
gem5::HSAPacketProcessor::processPkt
Q_STATE processPkt(void *pkt, uint32_t rl_idx, Addr host_pkt_addr)
Definition: hsa_packet_processor.cc:261
gem5::HSAPacketProcessor::SignalState::SignalState
SignalState()
Definition: hsa_packet_processor.hh:238
gem5::HSAQueueDescriptor::readIndex
uint64_t readIndex
Definition: hsa_packet_processor.hh:82
gem5::HSAPacketProcessor::RQLEntry::qCntxt
QCntxt qCntxt
Definition: hsa_packet_processor.hh:278
gem5::HSAPacketProcessor::SignalState::resetSigVals
void resetSigVals()
Definition: hsa_packet_processor.hh:252
gem5::HSAQueueDescriptor::hostReadIndexPtr
uint64_t hostReadIndexPtr
Definition: hsa_packet_processor.hh:84
gem5::AQLRingBuffer::_wrIdx
uint64_t _wrIdx
Definition: hsa_packet_processor.hh:136
gem5::AQLRingBuffer::numObjs
uint32_t numObjs() const
Definition: hsa_packet_processor.hh:200
gem5::HSAPacketProcessor::dma_series_ctx::start_ix
uint32_t start_ix
Definition: hsa_packet_processor.hh:355
hsa_signal_value_t
int32_t hsa_signal_value_t
Signal value.
Definition: hsa.h:1322
gem5::HSAPacketProcessor::QueueProcessEvent
Definition: hsa_packet_processor.hh:258
gem5::HSAPacketProcessor::RQLEntry::compltnPending
uint64_t compltnPending()
Definition: hsa_packet_processor.hh:280
gem5::HSAPacketProcessor::unsetDeviceQueueDesc
void unsetDeviceQueueDesc(uint64_t queue_id, int doorbellSize)
Definition: hsa_packet_processor.cc:94
gem5::HSAQueueDescriptor::isEmpty
bool isEmpty()
Definition: hsa_packet_processor.hh:101
gem5::HSAQueueDescriptor::numObjs
uint32_t numObjs()
Definition: hsa_packet_processor.hh:99
gem5::HSAPacketProcessor::getQueueDesc
HSAQueueDescriptor * getQueueDesc(uint32_t queId)
Definition: hsa_packet_processor.hh:298
gem5::HSAQueueDescriptor::basePointer
uint64_t basePointer
Definition: hsa_packet_processor.hh:79
gem5::AQLRingBuffer::saveHostDispAddr
void saveHostDispAddr(Addr host_pkt_addr, int num_pkts, int ix)
the kernel may try to read from the dispatch packet, so we need to keep the host address that corresp...
Definition: hsa_packet_processor.hh:156
NumSignalsPerBarrier
#define NumSignalsPerBarrier
Definition: hsa_packet_processor.hh:53
gem5::HSAPacketProcessor::inFlightPkts
uint64_t inFlightPkts(uint32_t queId)
Definition: hsa_packet_processor.hh:309
gem5::HSAPacketProcessor::RQLEntry::setBarrierBit
void setBarrierBit(bool set_val)
Definition: hsa_packet_processor.hh:283
gem5::HSAPacketProcessor::QueueProcessEvent::rqIdx
uint32_t rqIdx
Definition: hsa_packet_processor.hh:262
std::vector
STL vector class.
Definition: stl.hh:37
AQL_PACKET_SIZE
#define AQL_PACKET_SIZE
Definition: hsa_packet_processor.hh:48
gem5::HSAQueueDescriptor::ptr
uint64_t ptr(uint64_t ix)
Definition: hsa_packet_processor.hh:103
gem5::AQLRingBuffer::hostDispAddr
Addr hostDispAddr() const
Definition: hsa_packet_processor.hh:165
gem5::Q_STATE
Q_STATE
Definition: hsa_packet_processor.hh:61
gem5::HSAPacketProcessor::SignalState::discardRead
bool discardRead
Definition: hsa_packet_processor.hh:248
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::HSAPacketProcessor::pioSize
Addr pioSize
Definition: hsa_packet_processor.hh:317
gem5::HSAPacketProcessor::getCommandsFromHost
void getCommandsFromHost(int pid, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:478
gem5::HSAPacketProcessor::dma_series_ctx::pkts_2_go
uint32_t pkts_2_go
Definition: hsa_packet_processor.hh:354
hsa_queue.hh
gem5::HSAPacketProcessor::setDeviceQueueDesc
void setDeviceQueueDesc(uint64_t hostReadIndexPointer, uint64_t basePointer, uint64_t queue_id, uint32_t size, int doorbellSize)
Definition: hsa_packet_processor.cc:100
hsa.h
gem5::HSAPacketProcessor::RQLEntry::isLastOutstandingPkt
bool isLastOutstandingPkt() const
Definition: hsa_packet_processor.hh:285
gem5::HSAPacketProcessor::SignalState::pendingReads
int pendingReads
Definition: hsa_packet_processor.hh:244
HSA_PACKET_HEADER_WIDTH_TYPE
@ HSA_PACKET_HEADER_WIDTH_TYPE
Definition: hsa.h:2858
gem5::HSAQueueDescriptor::spaceUsed
uint64_t spaceUsed()
Definition: hsa_packet_processor.hh:97
gem5::HSAQueueDescriptor::HSAQueueDescriptor
HSAQueueDescriptor(uint64_t base_ptr, uint64_t db_ptr, uint64_t hri_ptr, uint32_t size)
Definition: hsa_packet_processor.hh:88
gem5::AQLRingBuffer::freeEntry
bool freeEntry(void *pkt)
Definition: hsa_packet_processor.cc:585
gem5::HSAPacketProcessor::gpu_device
GPUCommandProcessor * gpu_device
Definition: hsa_packet_processor.hh:229
gem5::QCntxt::barrierBit
bool barrierBit
Definition: hsa_packet_processor.hh:217
gem5::HSAPacketProcessor::cmdQueueCmdDma
void cmdQueueCmdDma(HSAPacketProcessor *hsaPP, int pid, bool isRead, uint32_t ix_start, unsigned num_pkts, dma_series_ctx *series_ctx, void *dest_4debug)
Definition: hsa_packet_processor.cc:210
gem5::HSAPacketProcessor::read
virtual Tick read(Packet *) override
Definition: hsa_packet_processor.cc:155
gem5::AQLRingBuffer::compltnPending
uint64_t compltnPending()
Definition: hsa_packet_processor.hh:209
gem5::AQLRingBuffer::ptr
void * ptr(uint32_t ix)
Definition: hsa_packet_processor.hh:199
gem5::HSAPacketProcessor::finishPkt
void finishPkt(void *pkt)
Definition: hsa_packet_processor.hh:339
gem5::HSAQueueDescriptor::dmaInProgress
bool dmaInProgress
Definition: hsa_packet_processor.hh:86
gem5::QCntxt::QCntxt
QCntxt(HSAQueueDescriptor *q_desc, AQLRingBuffer *aql_buf)
Definition: hsa_packet_processor.hh:218
gem5::GPUCommandProcessor
Definition: gpu_command_processor.hh:71
gem5::HSAPacketProcessor::finishPkt
void finishPkt(void *pkt, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:630
gem5::HSAPacketProcessor
Definition: hsa_packet_processor.hh:224
gem5::HSAPacketProcessor::handleReadDMA
void handleReadDMA()
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::HSAPacketProcessor::dma_series_ctx
Calls getCurrentEntry once the queueEntry has been dmaRead.
Definition: hsa_packet_processor.hh:350
gem5::HSAQueueDescriptor::isFull
bool isFull()
Definition: hsa_packet_processor.hh:100
gem5::HSAPacketProcessor::getRegdListEntry
class RQLEntry * getRegdListEntry(uint32_t queId)
Definition: hsa_packet_processor.hh:303
gem5::AQLRingBuffer::incWrIdx
void incWrIdx(uint64_t value)
Definition: hsa_packet_processor.hh:207
gem5::AQLRingBuffer::rdIdx
uint64_t rdIdx() const
Definition: hsa_packet_processor.hh:204
gem5::AQLRingBuffer::_aqlBuf
std::vector< hsa_kernel_dispatch_packet_t > _aqlBuf
Definition: hsa_packet_processor.hh:132
gem5::BLOCKED_BBIT
@ BLOCKED_BBIT
Definition: hsa_packet_processor.hh:64
gem5::HSAQueueDescriptor::spaceRemaining
uint64_t spaceRemaining()
Definition: hsa_packet_processor.hh:96
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::QCntxt
Definition: hsa_packet_processor.hh:212
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::DmaDevice
Definition: dma_device.hh:203
gem5::HSAPacketProcessor::hwSchdlr
HWScheduler * hwSchdlr
Definition: hsa_packet_processor.hh:230
gem5::AQLRingBuffer::dispPending
bool dispPending() const
Definition: hsa_packet_processor.hh:171
gem5::HSAPacketProcessor::translateOrDie
void translateOrDie(Addr vaddr, Addr &paddr) override
Function used to translate from virtual to physical addresses.
Definition: hsa_packet_processor.cc:163
gem5::HSAPacketProcessor::RQLEntry::depSignalRdState
SignalState depSignalRdState
Definition: hsa_packet_processor.hh:281
gem5::HSAPacketProcessor::HSAPacketProcessor
HSAPacketProcessor(const Params &p)
Definition: hsa_packet_processor.cc:74
gem5::HSAQueueDescriptor::stalledOnDmaBufAvailability
bool stalledOnDmaBufAvailability
Definition: hsa_packet_processor.hh:85
gem5::HSAPacketProcessor::dma_series_ctx::dma_series_ctx
dma_series_ctx(uint32_t _pkts_ttl, uint32_t _pkts_2_go, uint32_t _start_ix, uint32_t _rl_idx)
Definition: hsa_packet_processor.hh:358
HSA_PACKET_HEADER_TYPE
@ HSA_PACKET_HEADER_TYPE
Packet type.
Definition: hsa.h:2816
gem5::HSAQueueDescriptor
Definition: hsa_packet_processor.hh:76
gem5::AQLRingBuffer::_name
std::string _name
Definition: hsa_packet_processor.hh:133
gem5::AQLRingBuffer::_dispIdx
uint64_t _dispIdx
Definition: hsa_packet_processor.hh:138
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::BLOCKED_BPKT
@ BLOCKED_BPKT
Definition: hsa_packet_processor.hh:67
gem5::HSAPacketProcessor::sendCompletionSignal
void sendCompletionSignal(hsa_signal_value_t signal)
Definition: hsa_packet_processor.cc:702
gem5::HSAPacketProcessor::numHWQueues
int numHWQueues
Definition: hsa_packet_processor.hh:315
gem5::HSAPacketProcessor::RQLEntry::dispPending
bool dispPending()
Definition: hsa_packet_processor.hh:279
gem5::HSAPacketProcessor::RQLEntry::RQLEntry
RQLEntry(HSAPacketProcessor *hsaPP, uint32_t rqIdx)
Definition: hsa_packet_processor.hh:276
gem5::HSAPacketProcessor::displayQueueDescriptor
void displayQueueDescriptor(int pid, uint32_t rl_idx)
Definition: hsa_packet_processor.cc:560
gem5::HSAQueueDescriptor::doorbellPointer
uint64_t doorbellPointer
Definition: hsa_packet_processor.hh:80
gem5::HSAPacketProcessor::updateReadIndex
void updateReadIndex(int, uint32_t)
Definition: hsa_packet_processor.cc:186
gem5::HSAPacketProcessor::RQLEntry::getBarrierBit
bool getBarrierBit() const
Definition: hsa_packet_processor.hh:284
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::AQLRingBuffer::_rdIdx
uint64_t _rdIdx
Definition: hsa_packet_processor.hh:137
gem5::HWScheduler
Definition: hw_scheduler.hh:51
gem5::AQLRingBuffer::incDispIdx
void incDispIdx(uint64_t value)
Definition: hsa_packet_processor.hh:208
HSA_PACKET_TYPE_INVALID
@ HSA_PACKET_TYPE_INVALID
The packet has been processed in the past, but has not been reassigned to the packet processor.
Definition: hsa.h:2756
gem5::HSAPacketProcessor::SignalState::handleReadDMA
void handleReadDMA()
Definition: hsa_packet_processor.cc:465
gem5::HSAPacketProcessor::SignalState
Definition: hsa_packet_processor.hh:235
gem5::AQLRingBuffer::isLastOutstandingPkt
bool isLastOutstandingPkt() const
Packets aren't guaranteed to be completed in-order, and we need to know when the last packet is finis...
Definition: hsa_packet_processor.hh:188
gem5::HSAPacketProcessor::sendAgentDispatchCompletionSignal
void sendAgentDispatchCompletionSignal(void *pkt, hsa_signal_value_t signal)
Definition: hsa_packet_processor.cc:672
gem5::QCntxt::aqlBuf
AQLRingBuffer * aqlBuf
Definition: hsa_packet_processor.hh:215
gem5::QCntxt::QCntxt
QCntxt()
Definition: hsa_packet_processor.hh:221
gem5::AQLRingBuffer::wrIdx
uint64_t wrIdx() const
Definition: hsa_packet_processor.hh:203
gem5::AQLRingBuffer::_hostDispAddresses
std::vector< Addr > _hostDispAddresses
Definition: hsa_packet_processor.hh:134
gem5::HSAPacketProcessor::regdQList
std::vector< class RQLEntry * > regdQList
Definition: hsa_packet_processor.hh:291
gem5::HSAPacketProcessor::pktProcessDelay
const Tick pktProcessDelay
Definition: hsa_packet_processor.hh:319
gem5::HSAPacketProcessor::setDevice
void setDevice(GPUCommandProcessor *dev)
Definition: hsa_packet_processor.cc:605
gem5::AQLRingBuffer::incRdIdx
void incRdIdx(uint64_t value)
Definition: hsa_packet_processor.hh:206
gem5::HSAPacketProcessor::dma_series_ctx::pkts_ttl
uint32_t pkts_ttl
Definition: hsa_packet_processor.hh:353
types.hh
gem5::HSAPacketProcessor::QueueProcessEvent::QueueProcessEvent
QueueProcessEvent(HSAPacketProcessor *_hsaPP, uint32_t _rqIdx)
Definition: hsa_packet_processor.hh:264
gem5::HSAQueueDescriptor::numElts
uint32_t numElts
Definition: hsa_packet_processor.hh:83
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Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer.
Definition: hsa_packet_processor.hh:129
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HSAQueueDescriptor * qDesc
Definition: hsa_packet_processor.hh:214
gem5::HSAPacketProcessor::SignalState::allRead
bool allRead
Definition: hsa_packet_processor.hh:245
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uint64_t * rdIdxPtr()
Definition: hsa_packet_processor.hh:205
gem5::HSAPacketProcessor::QueueProcessEvent::description
virtual const char * description() const
Return a C string describing the event.
gem5::HSAPacketProcessor::Params
HSAPacketProcessorParams Params
Definition: hsa_packet_processor.hh:321
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uint32_t objSize()
Definition: hsa_packet_processor.hh:98
gem5::HSAPacketProcessor::getAddrRanges
virtual AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: hsa_packet_processor.cc:113
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gem5::HSAPacketProcessor::~HSAPacketProcessor
~HSAPacketProcessor()
Definition: hsa_packet_processor.cc:86
gem5::HSAPacketProcessor::SignalState::values
std::vector< hsa_signal_value_t > values
Definition: hsa_packet_processor.hh:250
gem5::HSAPacketProcessor::RQLEntry
Definition: hsa_packet_processor.hh:273
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uint32_t nFree() const
Definition: hsa_packet_processor.hh:198
gem5::AQLRingBuffer::_aqlComplete
std::vector< bool > _aqlComplete
Definition: hsa_packet_processor.hh:135
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Definition: dma_virt_device.hh:42
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vaddr
Definition: pra_constants.hh:278
std::list< AddrRange >
gem5::HSAPacketProcessor::updateReadDispIdDma
void updateReadDispIdDma()
this event is used to update the read_disp_id field (the read pointer) of the MQD,...
Definition: hsa_packet_processor.cc:180
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static const Priority Default_Pri
Default is zero for historical reasons.
Definition: eventq.hh:179
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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uint32_t objSize() const
Definition: hsa_packet_processor.hh:201
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Definition: hsa_packet_processor.cc:413
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virtual Tick write(Packet *) override
Definition: hsa_packet_processor.cc:125
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@ UNBLOCKED
Definition: hsa_packet_processor.hh:63
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void(DmaDevice::* DmaFnPtr)(Addr, int, Event *, uint8_t *, Tick)
Definition: hsa_packet_processor.hh:228
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uint32_t rl_idx
Definition: hsa_packet_processor.hh:356
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uint64_t writeIndex
Definition: hsa_packet_processor.hh:81
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uint64_t dispIdx() const
Definition: hsa_packet_processor.hh:202
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Definition: hsa_packet_processor.hh:282
eventq.hh

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