iob.cc File Reference

This device implemetns the niagara I/O bridge chip. More...

#include "dev/sparc/iob.hh"
#include <cstring>
#include "arch/sparc/faults.hh"
#include "arch/sparc/interrupts.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Iob.hh"
#include "dev/platform.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/faults.hh"
#include "sim/system.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

Detailed Description

This device implemetns the niagara I/O bridge chip.

It manages incomming interrupts and posts them to the CPU when needed. It holds mask registers and various status registers for CPUs to check what interrupts are pending as well as facilities to send IPIs to other cpus.

Definition in file iob.cc.