gem5  v21.2.1.1
faults.hh
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28 
29 #ifndef __SPARC_FAULTS_HH__
30 #define __SPARC_FAULTS_HH__
31 
32 #include "cpu/null_static_inst.hh"
33 #include "cpu/static_inst.hh"
34 #include "sim/faults.hh"
35 
36 // The design of the "name" and "vect" functions is in sim/faults.hh
37 
38 namespace gem5
39 {
40 
41 namespace SparcISA
42 {
43 
44 typedef uint32_t TrapType;
45 typedef uint32_t FaultPriority;
46 
47 class ITB;
48 
49 class SparcFaultBase : public FaultBase
50 {
51  public:
53  {
54  U, User = U,
58  SH = -1,
60  };
61  using PrivilegeLevelSpec = std::array<PrivilegeLevel, NumLevels>;
62  struct FaultVals
63  {
64  const FaultName name;
68  FaultVals(const FaultName& name_, const TrapType& trapType_,
69  const FaultPriority& priority_, const PrivilegeLevelSpec& il)
70  : name(name_), trapType(trapType_), priority(priority_),
72  {}
73  };
74  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
76  virtual TrapType trapType() = 0;
77  virtual FaultPriority priority() = 0;
78  virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
79 };
80 
81 template<typename T>
82 class SparcFault : public SparcFaultBase
83 {
84  protected:
85  static FaultVals vals;
86  public:
87  FaultName name() const { return vals.name; }
90 
93  {
94  return vals.nextPrivilegeLevel[current];
95  }
96 };
97 
98 class PowerOnReset : public SparcFault<PowerOnReset>
99 {
100  public:
101  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
103 };
104 
105 class WatchDogReset : public SparcFault<WatchDogReset> {};
106 
107 class ExternallyInitiatedReset : public SparcFault<ExternallyInitiatedReset> {};
108 
109 class SoftwareInitiatedReset : public SparcFault<SoftwareInitiatedReset> {};
110 
111 class REDStateException : public SparcFault<REDStateException> {};
112 
113 class StoreError : public SparcFault<StoreError> {};
114 
115 class InstructionAccessException : public SparcFault<InstructionAccessException> {};
116 
117 // class InstructionAccessMMUMiss : public SparcFault<InstructionAccessMMUMiss> {};
118 
119 class InstructionAccessError : public SparcFault<InstructionAccessError> {};
120 
121 class IllegalInstruction : public SparcFault<IllegalInstruction> {};
122 
123 class PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {};
124 
125 // class UnimplementedLDD : public SparcFault<UnimplementedLDD> {};
126 
127 // class UnimplementedSTD : public SparcFault<UnimplementedSTD> {};
128 
129 class FpDisabled : public SparcFault<FpDisabled> {};
130 class VecDisabled : public SparcFault<VecDisabled> {};
131 
132 class FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {};
133 
134 class FpExceptionOther : public SparcFault<FpExceptionOther> {};
135 
136 class TagOverflow : public SparcFault<TagOverflow> {};
137 
138 class CleanWindow : public SparcFault<CleanWindow> {};
139 
140 class DivisionByZero : public SparcFault<DivisionByZero> {};
141 
143  public SparcFault<InternalProcessorError> {};
144 
146  public SparcFault<InstructionInvalidTSBEntry> {};
147 
148 class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {};
149 
150 class DataAccessException : public SparcFault<DataAccessException> {};
151 
152 // class DataAccessMMUMiss : public SparcFault<DataAccessMMUMiss> {};
153 
154 class DataAccessError : public SparcFault<DataAccessError> {};
155 
156 class DataAccessProtection : public SparcFault<DataAccessProtection> {};
157 
159  public SparcFault<MemAddressNotAligned> {};
160 
161 class LDDFMemAddressNotAligned : public SparcFault<LDDFMemAddressNotAligned> {};
162 
163 class STDFMemAddressNotAligned : public SparcFault<STDFMemAddressNotAligned> {};
164 
165 class PrivilegedAction : public SparcFault<PrivilegedAction> {};
166 
167 class LDQFMemAddressNotAligned : public SparcFault<LDQFMemAddressNotAligned> {};
168 
169 class STQFMemAddressNotAligned : public SparcFault<STQFMemAddressNotAligned> {};
170 
172  public SparcFault<InstructionRealTranslationMiss> {};
173 
174 class DataRealTranslationMiss : public SparcFault<DataRealTranslationMiss> {};
175 
176 // class AsyncDataError : public SparcFault<AsyncDataError> {};
177 
178 template <class T>
179 class EnumeratedFault : public SparcFault<T>
180 {
181  protected:
182  uint32_t _n;
183  public:
184  EnumeratedFault(uint32_t n) : SparcFault<T>(), _n(n) {}
186 };
187 
188 class InterruptLevelN : public EnumeratedFault<InterruptLevelN>
189 {
190  public:
192  FaultPriority priority() { return 3200 - _n*100; }
193 };
194 
195 class HstickMatch : public SparcFault<HstickMatch> {};
196 
197 class TrapLevelZero : public SparcFault<TrapLevelZero> {};
198 
199 class InterruptVector : public SparcFault<InterruptVector> {};
200 
201 class PAWatchpoint : public SparcFault<PAWatchpoint> {};
202 
203 class VAWatchpoint : public SparcFault<VAWatchpoint> {};
204 
206  public SparcFault<FastInstructionAccessMMUMiss>
207 {
208  protected:
210  public:
212  {}
214  {}
215  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
217 };
218 
219 class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
220 {
221  protected:
223  public:
225  {}
227  {}
228  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
230 };
231 
232 class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
233 
234 class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {};
235 
236 class CpuMondo : public SparcFault<CpuMondo> {};
237 
238 class DevMondo : public SparcFault<DevMondo> {};
239 
240 class ResumableError : public SparcFault<ResumableError> {};
241 
242 class SpillNNormal : public EnumeratedFault<SpillNNormal>
243 {
244  public:
246  // These need to be handled specially to enable spill traps in SE
247  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
249 };
250 
251 class SpillNOther : public EnumeratedFault<SpillNOther>
252 {
253  public:
255  {}
256 };
257 
258 class FillNNormal : public EnumeratedFault<FillNNormal>
259 {
260  public:
262  {}
263  // These need to be handled specially to enable fill traps in SE
264  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
266 };
267 
268 class FillNOther : public EnumeratedFault<FillNOther>
269 {
270  public:
272  {}
273 };
274 
275 class TrapInstruction : public EnumeratedFault<TrapInstruction>
276 {
277  public:
279  {}
280  // In SE, trap instructions are requesting services from the OS.
281  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
283 };
284 
285 /*
286  * Explicitly declare template static member variables to avoid warnings
287  * in some clang versions
288  */
291 template<> SparcFaultBase::FaultVals
296 template<> SparcFaultBase::FaultVals
309 template<> SparcFaultBase::FaultVals
316 template<> SparcFaultBase::FaultVals
318 template<> SparcFaultBase::FaultVals
321 template<> SparcFaultBase::FaultVals
323 template<> SparcFaultBase::FaultVals
325 template<> SparcFaultBase::FaultVals
334 template<> SparcFaultBase::FaultVals
337 template<>
348 
349 
350 void enterREDState(ThreadContext *tc);
351 
352 void doREDFault(ThreadContext *tc, TrapType tt);
353 
354 void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
355 
356 void getREDVector(RegVal TT, Addr &PC, Addr &NPC);
357 
358 void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT);
359 
360 void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT,
361  RegVal TL);
362 
363 } // namespace SparcISA
364 } // namespace gem5
365 
366 #endif // __SPARC_FAULTS_HH__
gem5::SparcISA::EnumeratedFault::trapType
TrapType trapType()
Definition: faults.hh:185
gem5::SparcISA::FillNOther::FillNOther
FillNOther(uint32_t n)
Definition: faults.hh:271
gem5::SparcISA::LDDFMemAddressNotAligned
Definition: faults.hh:161
gem5::SparcISA::SparcFaultBase::ShouldntHappen
@ ShouldntHappen
Definition: faults.hh:59
gem5::SparcISA::FastDataAccessProtection
Definition: faults.hh:232
gem5::SparcISA::PowerOnReset
Definition: faults.hh:98
gem5::SparcISA::SparcFaultBase::Hyperprivileged
@ Hyperprivileged
Definition: faults.hh:56
gem5::SparcISA::FastDataAccessMMUMiss::FastDataAccessMMUMiss
FastDataAccessMMUMiss(Addr addr)
Definition: faults.hh:224
gem5::SparcISA::SparcFaultBase::trapType
virtual TrapType trapType()=0
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SparcISA::FpExceptionOther
Definition: faults.hh:134
gem5::SparcISA::SparcFaultBase::U
@ U
Definition: faults.hh:54
gem5::SparcISA::SpillNNormal::SpillNNormal
SpillNNormal(uint32_t n)
Definition: faults.hh:245
gem5::SparcISA::FastDataAccessMMUMiss::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:680
gem5::SparcISA::DataAccessProtection
Definition: faults.hh:156
gem5::SparcISA::SparcFaultBase::PrivilegeLevel
PrivilegeLevel
Definition: faults.hh:52
gem5::SparcISA::FastInstructionAccessMMUMiss::FastInstructionAccessMMUMiss
FastInstructionAccessMMUMiss(Addr addr)
Definition: faults.hh:211
gem5::SparcISA::SoftwareInitiatedReset
Definition: faults.hh:109
gem5::SparcISA::TrapInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:806
gem5::SparcISA::SpillNOther::SpillNOther
SpillNOther(uint32_t n)
Definition: faults.hh:254
gem5::SparcISA::FastInstructionAccessMMUMiss::FastInstructionAccessMMUMiss
FastInstructionAccessMMUMiss()
Definition: faults.hh:213
gem5::SparcISA::PowerOnReset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:560
gem5::SparcISA::TagOverflow
Definition: faults.hh:136
gem5::SparcISA::SparcFaultBase::FaultVals::priority
const FaultPriority priority
Definition: faults.hh:66
gem5::SparcISA::SparcFaultBase::getNextLevel
virtual PrivilegeLevel getNextLevel(PrivilegeLevel current)=0
gem5::SparcISA::DevMondo
Definition: faults.hh:238
gem5::SparcISA::n
Bitfield< 7 > n
Definition: misc.hh:140
gem5::SparcISA::FastDataAccessMMUMiss::FastDataAccessMMUMiss
FastDataAccessMMUMiss()
Definition: faults.hh:226
gem5::SparcISA::FillNOther
Definition: faults.hh:268
gem5::SparcISA::SparcFaultBase::FaultVals::FaultVals
FaultVals(const FaultName &name_, const TrapType &trapType_, const FaultPriority &priority_, const PrivilegeLevelSpec &il)
Definition: faults.hh:68
gem5::SparcISA::SparcFault::priority
FaultPriority priority()
Definition: faults.hh:89
gem5::SparcISA::STDFMemAddressNotAligned
Definition: faults.hh:163
gem5::SparcISA::SparcFaultBase::priority
virtual FaultPriority priority()=0
faults.hh
gem5::SparcISA::LDQFMemAddressNotAligned
Definition: faults.hh:167
gem5::SparcISA::InternalProcessorError
Definition: faults.hh:142
gem5::SparcISA::doNormalFault
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
This sets everything up for a normal trap except for actually jumping to the handler.
Definition: faults.cc:382
gem5::SparcISA::FastInstructionAccessMMUMiss::vaddr
Addr vaddr
Definition: faults.hh:209
gem5::SparcISA::SparcFaultBase::Privileged
@ Privileged
Definition: faults.hh:55
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::il
Bitfield< 20 > il
Definition: misc_types.hh:61
gem5::SparcISA::MemAddressNotAligned
Definition: faults.hh:158
gem5::SparcISA::InterruptLevelN::priority
FaultPriority priority()
Definition: faults.hh:192
gem5::SparcISA::EnumeratedFault::EnumeratedFault
EnumeratedFault(uint32_t n)
Definition: faults.hh:184
gem5::SparcISA::ExternallyInitiatedReset
Definition: faults.hh:107
gem5::SparcISA::TrapInstruction
Definition: faults.hh:275
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::SparcISA::getPrivVector
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
Definition: faults.cc:490
gem5::SparcISA::DataAccessException
Definition: faults.hh:150
gem5::SparcISA::SparcFaultBase::P
@ P
Definition: faults.hh:55
gem5::SparcISA::getHyperVector
void getHyperVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
Definition: faults.cc:482
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SparcISA::SparcFaultBase::PrivilegeLevelSpec
std::array< PrivilegeLevel, NumLevels > PrivilegeLevelSpec
Definition: faults.hh:61
gem5::SparcISA::SpillNNormal::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:768
gem5::SparcISA::SparcFault
Definition: faults.hh:82
gem5::SparcISA::EnumeratedFault
Definition: faults.hh:179
gem5::SparcISA::InstructionAccessException
Definition: faults.hh:115
gem5::SparcISA::SparcFault::getNextLevel
PrivilegeLevel getNextLevel(PrivilegeLevel current)
Definition: faults.hh:92
gem5::SparcISA::SparcFaultBase::FaultVals::name
const FaultName name
Definition: faults.hh:64
gem5::SparcISA::getREDVector
void getREDVector(RegVal TT, Addr &PC, Addr &NPC)
Definition: faults.cc:473
gem5::SparcISA::REDStateException
Definition: faults.hh:111
gem5::SparcISA::SpillNOther
Definition: faults.hh:251
gem5::SparcISA::SparcFaultBase::NumLevels
@ NumLevels
Definition: faults.hh:57
gem5::SparcISA::VecDisabled
Definition: faults.hh:130
gem5::SparcISA::SparcFaultBase::FaultVals
Definition: faults.hh:62
gem5::SparcISA::TrapType
uint32_t TrapType
Definition: faults.hh:44
gem5::SparcISA::STQFMemAddressNotAligned
Definition: faults.hh:169
gem5::SparcISA::PrivilegedAction
Definition: faults.hh:165
gem5::SparcISA::FillNNormal
Definition: faults.hh:258
static_inst.hh
gem5::SparcISA::SparcFault::trapType
TrapType trapType()
Definition: faults.hh:88
gem5::SparcISA::InstructionRealTranslationMiss
Definition: faults.hh:171
gem5::SparcISA::FastInstructionAccessMMUMiss::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:623
gem5::SparcISA::StoreError
Definition: faults.hh:113
null_static_inst.hh
gem5::SparcISA::CpuMondo
Definition: faults.hh:236
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::PrivilegedOpcode
Definition: faults.hh:123
gem5::SparcISA::FastDataAccessMMUMiss
Definition: faults.hh:219
gem5::SparcISA::CleanWindow
Definition: faults.hh:138
gem5::SparcISA::doREDFault
void doREDFault(ThreadContext *tc, TrapType tt)
This sets everything up for a RED state trap except for actually jumping to the handler.
Definition: faults.cc:303
gem5::SparcISA::SparcFaultBase::H
@ H
Definition: faults.hh:56
gem5::SparcISA::FillNNormal::FillNNormal
FillNNormal(uint32_t n)
Definition: faults.hh:261
gem5::SparcISA::VAWatchpoint
Definition: faults.hh:203
gem5::SparcISA::TrapInstruction::TrapInstruction
TrapInstruction(uint32_t n)
Definition: faults.hh:278
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::SparcISA::InterruptLevelN::InterruptLevelN
InterruptLevelN(uint32_t n)
Definition: faults.hh:191
gem5::SparcISA::IllegalInstruction
Definition: faults.hh:121
gem5::SparcISA::InterruptVector
Definition: faults.hh:199
gem5::SparcISA::SparcFaultBase::SH
@ SH
Definition: faults.hh:58
gem5::SparcISA::TrapLevelZero
Definition: faults.hh:197
gem5::SparcISA::FillNNormal::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:787
gem5::SparcISA::ResumableError
Definition: faults.hh:240
gem5::SparcISA::FaultPriority
uint32_t FaultPriority
Definition: faults.hh:45
gem5::FaultBase
Definition: translation_gen.test.cc:48
gem5::SparcISA::FastInstructionAccessMMUMiss
Definition: faults.hh:205
gem5::SparcISA::DivisionByZero
Definition: faults.hh:140
gem5::SparcISA::FpDisabled
Definition: faults.hh:129
gem5::SparcISA::SparcFaultBase::User
@ User
Definition: faults.hh:54
gem5::SparcISA::InstructionInvalidTSBEntry
Definition: faults.hh:145
gem5::SparcISA::InterruptLevelN
Definition: faults.hh:188
gem5::SparcISA::FpExceptionIEEE754
Definition: faults.hh:132
gem5::SparcISA::FastDataAccessMMUMiss::vaddr
Addr vaddr
Definition: faults.hh:222
gem5::SparcISA::DataInvalidTSBEntry
Definition: faults.hh:148
gem5::SparcISA::SparcFaultBase::FaultVals::trapType
const TrapType trapType
Definition: faults.hh:65
gem5::SparcISA::SparcFault::vals
static FaultVals vals
Definition: faults.hh:85
gem5::SparcISA::SparcFaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:500
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::SparcISA::InstructionBreakpoint
Definition: faults.hh:234
gem5::SparcISA::SparcFaultBase
Definition: faults.hh:49
gem5::SparcISA::InstructionAccessError
Definition: faults.hh:119
gem5::SparcISA::SparcFaultBase::FaultVals::nextPrivilegeLevel
const PrivilegeLevelSpec nextPrivilegeLevel
Definition: faults.hh:67
gem5::SparcISA::HstickMatch
Definition: faults.hh:195
gem5::SparcISA::enterREDState
void enterREDState(ThreadContext *tc)
This causes the thread context to enter RED state.
Definition: faults.cc:282
gem5::SparcISA::SparcFault::name
FaultName name() const
Definition: faults.hh:87
gem5::SparcISA::DataAccessError
Definition: faults.hh:154
gem5::SparcISA::EnumeratedFault::_n
uint32_t _n
Definition: faults.hh:182
gem5::SparcISA::PAWatchpoint
Definition: faults.hh:201
gem5::SparcISA::SpillNNormal
Definition: faults.hh:242
gem5::SparcISA::WatchDogReset
Definition: faults.hh:105
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::SparcISA::DataRealTranslationMiss
Definition: faults.hh:174

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