gem5  v21.1.0.2
faults.hh
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28 
29 #ifndef __SPARC_FAULTS_HH__
30 #define __SPARC_FAULTS_HH__
31 
32 #include "cpu/null_static_inst.hh"
33 #include "cpu/static_inst.hh"
34 #include "sim/faults.hh"
35 
36 // The design of the "name" and "vect" functions is in sim/faults.hh
37 
38 namespace gem5
39 {
40 
41 namespace SparcISA
42 {
43 
44 typedef uint32_t TrapType;
45 typedef uint32_t FaultPriority;
46 
47 class ITB;
48 
49 class SparcFaultBase : public FaultBase
50 {
51  public:
53  {
54  U, User = U,
58  SH = -1,
60  };
61  using PrivilegeLevelSpec = std::array<PrivilegeLevel, NumLevels>;
62  struct FaultVals
63  {
64  const FaultName name;
69  FaultVals(const FaultName& name_, const TrapType& trapType_,
70  const FaultPriority& priority_, const PrivilegeLevelSpec& il)
71  : name(name_), trapType(trapType_), priority(priority_),
73  {}
74  };
75  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
77  virtual TrapType trapType() = 0;
78  virtual FaultPriority priority() = 0;
79  virtual FaultStat & countStat() = 0;
80  virtual PrivilegeLevel getNextLevel(PrivilegeLevel current) = 0;
81 };
82 
83 template<typename T>
84 class SparcFault : public SparcFaultBase
85 {
86  protected:
87  static FaultVals vals;
88  public:
89  FaultName name() const { return vals.name; }
92  FaultStat & countStat() { return vals.count; }
93 
96  {
97  return vals.nextPrivilegeLevel[current];
98  }
99 };
100 
101 class PowerOnReset : public SparcFault<PowerOnReset>
102 {
103  public:
104  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
106 };
107 
108 class WatchDogReset : public SparcFault<WatchDogReset> {};
109 
110 class ExternallyInitiatedReset : public SparcFault<ExternallyInitiatedReset> {};
111 
112 class SoftwareInitiatedReset : public SparcFault<SoftwareInitiatedReset> {};
113 
114 class REDStateException : public SparcFault<REDStateException> {};
115 
116 class StoreError : public SparcFault<StoreError> {};
117 
118 class InstructionAccessException : public SparcFault<InstructionAccessException> {};
119 
120 // class InstructionAccessMMUMiss : public SparcFault<InstructionAccessMMUMiss> {};
121 
122 class InstructionAccessError : public SparcFault<InstructionAccessError> {};
123 
124 class IllegalInstruction : public SparcFault<IllegalInstruction> {};
125 
126 class PrivilegedOpcode : public SparcFault<PrivilegedOpcode> {};
127 
128 // class UnimplementedLDD : public SparcFault<UnimplementedLDD> {};
129 
130 // class UnimplementedSTD : public SparcFault<UnimplementedSTD> {};
131 
132 class FpDisabled : public SparcFault<FpDisabled> {};
133 class VecDisabled : public SparcFault<VecDisabled> {};
134 
135 class FpExceptionIEEE754 : public SparcFault<FpExceptionIEEE754> {};
136 
137 class FpExceptionOther : public SparcFault<FpExceptionOther> {};
138 
139 class TagOverflow : public SparcFault<TagOverflow> {};
140 
141 class CleanWindow : public SparcFault<CleanWindow> {};
142 
143 class DivisionByZero : public SparcFault<DivisionByZero> {};
144 
146  public SparcFault<InternalProcessorError> {};
147 
149  public SparcFault<InstructionInvalidTSBEntry> {};
150 
151 class DataInvalidTSBEntry : public SparcFault<DataInvalidTSBEntry> {};
152 
153 class DataAccessException : public SparcFault<DataAccessException> {};
154 
155 // class DataAccessMMUMiss : public SparcFault<DataAccessMMUMiss> {};
156 
157 class DataAccessError : public SparcFault<DataAccessError> {};
158 
159 class DataAccessProtection : public SparcFault<DataAccessProtection> {};
160 
162  public SparcFault<MemAddressNotAligned> {};
163 
164 class LDDFMemAddressNotAligned : public SparcFault<LDDFMemAddressNotAligned> {};
165 
166 class STDFMemAddressNotAligned : public SparcFault<STDFMemAddressNotAligned> {};
167 
168 class PrivilegedAction : public SparcFault<PrivilegedAction> {};
169 
170 class LDQFMemAddressNotAligned : public SparcFault<LDQFMemAddressNotAligned> {};
171 
172 class STQFMemAddressNotAligned : public SparcFault<STQFMemAddressNotAligned> {};
173 
175  public SparcFault<InstructionRealTranslationMiss> {};
176 
177 class DataRealTranslationMiss : public SparcFault<DataRealTranslationMiss> {};
178 
179 // class AsyncDataError : public SparcFault<AsyncDataError> {};
180 
181 template <class T>
182 class EnumeratedFault : public SparcFault<T>
183 {
184  protected:
185  uint32_t _n;
186  public:
187  EnumeratedFault(uint32_t n) : SparcFault<T>(), _n(n) {}
189 };
190 
191 class InterruptLevelN : public EnumeratedFault<InterruptLevelN>
192 {
193  public:
195  FaultPriority priority() { return 3200 - _n*100; }
196 };
197 
198 class HstickMatch : public SparcFault<HstickMatch> {};
199 
200 class TrapLevelZero : public SparcFault<TrapLevelZero> {};
201 
202 class InterruptVector : public SparcFault<InterruptVector> {};
203 
204 class PAWatchpoint : public SparcFault<PAWatchpoint> {};
205 
206 class VAWatchpoint : public SparcFault<VAWatchpoint> {};
207 
209  public SparcFault<FastInstructionAccessMMUMiss>
210 {
211  protected:
213  public:
215  {}
217  {}
218  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
220 };
221 
222 class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
223 {
224  protected:
226  public:
228  {}
230  {}
231  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
233 };
234 
235 class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
236 
237 class InstructionBreakpoint : public SparcFault<InstructionBreakpoint> {};
238 
239 class CpuMondo : public SparcFault<CpuMondo> {};
240 
241 class DevMondo : public SparcFault<DevMondo> {};
242 
243 class ResumableError : public SparcFault<ResumableError> {};
244 
245 class SpillNNormal : public EnumeratedFault<SpillNNormal>
246 {
247  public:
249  // These need to be handled specially to enable spill traps in SE
250  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
252 };
253 
254 class SpillNOther : public EnumeratedFault<SpillNOther>
255 {
256  public:
258  {}
259 };
260 
261 class FillNNormal : public EnumeratedFault<FillNNormal>
262 {
263  public:
265  {}
266  // These need to be handled specially to enable fill traps in SE
267  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
269 };
270 
271 class FillNOther : public EnumeratedFault<FillNOther>
272 {
273  public:
275  {}
276 };
277 
278 class TrapInstruction : public EnumeratedFault<TrapInstruction>
279 {
280  public:
282  {}
283  // In SE, trap instructions are requesting services from the OS.
284  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
286 };
287 
288 /*
289  * Explicitly declare template static member variables to avoid warnings
290  * in some clang versions
291  */
294 template<> SparcFaultBase::FaultVals
299 template<> SparcFaultBase::FaultVals
312 template<> SparcFaultBase::FaultVals
319 template<> SparcFaultBase::FaultVals
321 template<> SparcFaultBase::FaultVals
324 template<> SparcFaultBase::FaultVals
326 template<> SparcFaultBase::FaultVals
328 template<> SparcFaultBase::FaultVals
337 template<> SparcFaultBase::FaultVals
340 template<>
351 
352 
353 void enterREDState(ThreadContext *tc);
354 
355 void doREDFault(ThreadContext *tc, TrapType tt);
356 
357 void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
358 
359 void getREDVector(RegVal TT, Addr &PC, Addr &NPC);
360 
361 void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT);
362 
363 void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT,
364  RegVal TL);
365 
366 } // namespace SparcISA
367 } // namespace gem5
368 
369 #endif // __SPARC_FAULTS_HH__
gem5::SparcISA::EnumeratedFault::trapType
TrapType trapType()
Definition: faults.hh:188
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::SparcISA::FillNOther::FillNOther
FillNOther(uint32_t n)
Definition: faults.hh:274
gem5::SparcISA::LDDFMemAddressNotAligned
Definition: faults.hh:164
gem5::SparcISA::SparcFaultBase::ShouldntHappen
@ ShouldntHappen
Definition: faults.hh:59
gem5::SparcISA::FastDataAccessProtection
Definition: faults.hh:235
gem5::SparcISA::PowerOnReset
Definition: faults.hh:101
gem5::SparcISA::SparcFaultBase::Hyperprivileged
@ Hyperprivileged
Definition: faults.hh:56
gem5::SparcISA::FastDataAccessMMUMiss::FastDataAccessMMUMiss
FastDataAccessMMUMiss(Addr addr)
Definition: faults.hh:227
gem5::SparcISA::SparcFaultBase::trapType
virtual TrapType trapType()=0
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::SparcISA::FpExceptionOther
Definition: faults.hh:137
gem5::SparcISA::SparcFaultBase::U
@ U
Definition: faults.hh:54
gem5::SparcISA::SpillNNormal::SpillNNormal
SpillNNormal(uint32_t n)
Definition: faults.hh:248
gem5::SparcISA::FastDataAccessMMUMiss::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:681
gem5::SparcISA::DataAccessProtection
Definition: faults.hh:159
gem5::SparcISA::SparcFaultBase::PrivilegeLevel
PrivilegeLevel
Definition: faults.hh:52
gem5::SparcISA::FastInstructionAccessMMUMiss::FastInstructionAccessMMUMiss
FastInstructionAccessMMUMiss(Addr addr)
Definition: faults.hh:214
gem5::SparcISA::SoftwareInitiatedReset
Definition: faults.hh:112
gem5::SparcISA::TrapInstruction::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:807
gem5::SparcISA::SpillNOther::SpillNOther
SpillNOther(uint32_t n)
Definition: faults.hh:257
gem5::SparcISA::FastInstructionAccessMMUMiss::FastInstructionAccessMMUMiss
FastInstructionAccessMMUMiss()
Definition: faults.hh:216
gem5::SparcISA::PowerOnReset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:561
gem5::SparcISA::TagOverflow
Definition: faults.hh:139
gem5::SparcISA::SparcFaultBase::FaultVals::priority
const FaultPriority priority
Definition: faults.hh:66
gem5::SparcISA::SparcFaultBase::getNextLevel
virtual PrivilegeLevel getNextLevel(PrivilegeLevel current)=0
gem5::SparcISA::DevMondo
Definition: faults.hh:241
gem5::SparcISA::n
Bitfield< 7 > n
Definition: misc.hh:140
gem5::SparcISA::SparcFaultBase::FaultVals::count
FaultStat count
Definition: faults.hh:68
gem5::SparcISA::FastDataAccessMMUMiss::FastDataAccessMMUMiss
FastDataAccessMMUMiss()
Definition: faults.hh:229
gem5::SparcISA::FillNOther
Definition: faults.hh:271
gem5::SparcISA::SparcFaultBase::FaultVals::FaultVals
FaultVals(const FaultName &name_, const TrapType &trapType_, const FaultPriority &priority_, const PrivilegeLevelSpec &il)
Definition: faults.hh:69
gem5::SparcISA::SparcFault::priority
FaultPriority priority()
Definition: faults.hh:91
gem5::SparcISA::STDFMemAddressNotAligned
Definition: faults.hh:166
gem5::SparcISA::SparcFaultBase::priority
virtual FaultPriority priority()=0
faults.hh
gem5::SparcISA::LDQFMemAddressNotAligned
Definition: faults.hh:170
gem5::SparcISA::InternalProcessorError
Definition: faults.hh:145
gem5::SparcISA::doNormalFault
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
This sets everything up for a normal trap except for actually jumping to the handler.
Definition: faults.cc:382
gem5::SparcISA::FastInstructionAccessMMUMiss::vaddr
Addr vaddr
Definition: faults.hh:212
gem5::SparcISA::SparcFaultBase::Privileged
@ Privileged
Definition: faults.hh:55
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::il
Bitfield< 20 > il
Definition: misc_types.hh:60
gem5::SparcISA::MemAddressNotAligned
Definition: faults.hh:161
gem5::SparcISA::InterruptLevelN::priority
FaultPriority priority()
Definition: faults.hh:195
gem5::SparcISA::EnumeratedFault::EnumeratedFault
EnumeratedFault(uint32_t n)
Definition: faults.hh:187
gem5::SparcISA::ExternallyInitiatedReset
Definition: faults.hh:110
gem5::SparcISA::TrapInstruction
Definition: faults.hh:278
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::SparcISA::getPrivVector
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
Definition: faults.cc:490
gem5::SparcISA::DataAccessException
Definition: faults.hh:153
gem5::SparcISA::SparcFaultBase::P
@ P
Definition: faults.hh:55
gem5::SparcISA::getHyperVector
void getHyperVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
Definition: faults.cc:482
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::SparcISA::SparcFaultBase::PrivilegeLevelSpec
std::array< PrivilegeLevel, NumLevels > PrivilegeLevelSpec
Definition: faults.hh:61
gem5::SparcISA::SpillNNormal::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:769
gem5::SparcISA::SparcFault
Definition: faults.hh:84
gem5::SparcISA::EnumeratedFault
Definition: faults.hh:182
gem5::SparcISA::InstructionAccessException
Definition: faults.hh:118
gem5::SparcISA::SparcFault::getNextLevel
PrivilegeLevel getNextLevel(PrivilegeLevel current)
Definition: faults.hh:95
gem5::SparcISA::SparcFaultBase::FaultVals::name
const FaultName name
Definition: faults.hh:64
gem5::SparcISA::getREDVector
void getREDVector(RegVal TT, Addr &PC, Addr &NPC)
Definition: faults.cc:473
gem5::SparcISA::REDStateException
Definition: faults.hh:114
gem5::SparcISA::SpillNOther
Definition: faults.hh:254
gem5::SparcISA::SparcFaultBase::NumLevels
@ NumLevels
Definition: faults.hh:57
gem5::SparcISA::VecDisabled
Definition: faults.hh:133
gem5::SparcISA::SparcFaultBase::FaultVals
Definition: faults.hh:62
gem5::SparcISA::TrapType
uint32_t TrapType
Definition: faults.hh:44
gem5::SparcISA::STQFMemAddressNotAligned
Definition: faults.hh:172
gem5::SparcISA::PrivilegedAction
Definition: faults.hh:168
gem5::SparcISA::FillNNormal
Definition: faults.hh:261
static_inst.hh
gem5::SparcISA::SparcFault::trapType
TrapType trapType()
Definition: faults.hh:90
gem5::SparcISA::InstructionRealTranslationMiss
Definition: faults.hh:174
gem5::SparcISA::FastInstructionAccessMMUMiss::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:624
gem5::SparcISA::StoreError
Definition: faults.hh:116
null_static_inst.hh
gem5::SparcISA::CpuMondo
Definition: faults.hh:239
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::PrivilegedOpcode
Definition: faults.hh:126
gem5::SparcISA::FastDataAccessMMUMiss
Definition: faults.hh:222
gem5::SparcISA::CleanWindow
Definition: faults.hh:141
gem5::SparcISA::doREDFault
void doREDFault(ThreadContext *tc, TrapType tt)
This sets everything up for a RED state trap except for actually jumping to the handler.
Definition: faults.cc:303
gem5::SparcISA::SparcFaultBase::H
@ H
Definition: faults.hh:56
gem5::SparcISA::FillNNormal::FillNNormal
FillNNormal(uint32_t n)
Definition: faults.hh:264
gem5::SparcISA::VAWatchpoint
Definition: faults.hh:206
gem5::SparcISA::TrapInstruction::TrapInstruction
TrapInstruction(uint32_t n)
Definition: faults.hh:281
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::SparcISA::InterruptLevelN::InterruptLevelN
InterruptLevelN(uint32_t n)
Definition: faults.hh:194
gem5::SparcISA::IllegalInstruction
Definition: faults.hh:124
gem5::SparcISA::InterruptVector
Definition: faults.hh:202
gem5::SparcISA::SparcFaultBase::SH
@ SH
Definition: faults.hh:58
gem5::SparcISA::TrapLevelZero
Definition: faults.hh:200
gem5::SparcISA::FillNNormal::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:788
gem5::SparcISA::ResumableError
Definition: faults.hh:243
gem5::SparcISA::FaultPriority
uint32_t FaultPriority
Definition: faults.hh:45
gem5::FaultBase
Definition: faults.hh:58
gem5::SparcISA::FastInstructionAccessMMUMiss
Definition: faults.hh:208
gem5::SparcISA::DivisionByZero
Definition: faults.hh:143
gem5::SparcISA::FpDisabled
Definition: faults.hh:132
gem5::SparcISA::SparcFaultBase::countStat
virtual FaultStat & countStat()=0
gem5::SparcISA::SparcFaultBase::User
@ User
Definition: faults.hh:54
gem5::SparcISA::InstructionInvalidTSBEntry
Definition: faults.hh:148
gem5::SparcISA::InterruptLevelN
Definition: faults.hh:191
gem5::SparcISA::FpExceptionIEEE754
Definition: faults.hh:135
gem5::SparcISA::FastDataAccessMMUMiss::vaddr
Addr vaddr
Definition: faults.hh:225
gem5::SparcISA::DataInvalidTSBEntry
Definition: faults.hh:151
gem5::SparcISA::SparcFaultBase::FaultVals::trapType
const TrapType trapType
Definition: faults.hh:65
gem5::SparcISA::SparcFault::vals
static FaultVals vals
Definition: faults.hh:87
gem5::SparcISA::SparcFaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:500
gem5::SparcISA::SparcFault::countStat
FaultStat & countStat()
Definition: faults.hh:92
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::InstructionBreakpoint
Definition: faults.hh:237
gem5::SparcISA::SparcFaultBase
Definition: faults.hh:49
gem5::SparcISA::InstructionAccessError
Definition: faults.hh:122
gem5::SparcISA::SparcFaultBase::FaultVals::nextPrivilegeLevel
const PrivilegeLevelSpec nextPrivilegeLevel
Definition: faults.hh:67
gem5::SparcISA::HstickMatch
Definition: faults.hh:198
gem5::SparcISA::enterREDState
void enterREDState(ThreadContext *tc)
This causes the thread context to enter RED state.
Definition: faults.cc:282
gem5::SparcISA::SparcFault::name
FaultName name() const
Definition: faults.hh:89
gem5::SparcISA::DataAccessError
Definition: faults.hh:157
gem5::SparcISA::EnumeratedFault::_n
uint32_t _n
Definition: faults.hh:185
gem5::SparcISA::PAWatchpoint
Definition: faults.hh:204
gem5::SparcISA::SpillNNormal
Definition: faults.hh:245
gem5::SparcISA::WatchDogReset
Definition: faults.hh:108
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::SparcISA::DataRealTranslationMiss
Definition: faults.hh:177

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