gem5  v21.1.0.2
iob.cc
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28 
36 #include "dev/sparc/iob.hh"
37 
38 #include <cstring>
39 
40 #include "arch/sparc/faults.hh"
41 #include "arch/sparc/interrupts.hh"
42 #include "base/bitfield.hh"
43 #include "base/trace.hh"
44 #include "cpu/base.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/Iob.hh"
47 #include "dev/platform.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/port.hh"
50 #include "sim/faults.hh"
51 #include "sim/system.hh"
52 
53 namespace gem5
54 {
55 
57 {
58  iobManAddr = 0x9800000000ULL;
59  iobManSize = 0x0100000000ULL;
60  iobJBusAddr = 0x9F00000000ULL;
61  iobJBusSize = 0x0100000000ULL;
62  assert(params().system->threads.size() <= MaxNiagaraProcs);
63 
64  pioDelay = p.pio_latency;
65 
66  for (int x = 0; x < NumDeviceIds; ++x) {
67  intMan[x].cpu = 0;
68  intMan[x].vector = 0;
69  intCtl[x].mask = true;
70  intCtl[x].pend = false;
71  }
72 
73 }
74 
75 Tick
77 {
78 
79  if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
80  readIob(pkt);
81  else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
82  readJBus(pkt);
83  else
84  panic("Invalid address reached Iob\n");
85 
86  pkt->makeAtomicResponse();
87  return pioDelay;
88 }
89 
90 void
92 {
93  Addr accessAddr = pkt->getAddr() - iobManAddr;
94 
95  assert(IntManAddr == 0);
96  if (accessAddr < IntManAddr + IntManSize) {
97  int index = (accessAddr - IntManAddr) >> 3;
98  uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
99  pkt->setBE(data);
100  return;
101  }
102 
103  if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
104  int index = (accessAddr - IntCtlAddr) >> 3;
105  uint64_t data = (intCtl[index].mask ? (1 << 2) : 0) |
106  (intCtl[index].pend ? (1 << 0) : 0);
107  pkt->setBE(data);
108  return;
109  }
110 
111  if (accessAddr == JIntVecAddr) {
112  pkt->setBE(jIntVec);
113  return;
114  }
115 
116  panic("Read to unknown IOB offset 0x%x\n", accessAddr);
117 }
118 
119 void
121 {
122  Addr accessAddr = pkt->getAddr() - iobJBusAddr;
123  ContextID cpuid = pkt->req->contextId();
124  int index;
125  uint64_t data;
126 
127 
128 
129 
130  if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
131  index = (accessAddr - JIntData0Addr) >> 3;
132  pkt->setBE(jBusData0[index]);
133  return;
134  }
135 
136  if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
137  index = (accessAddr - JIntData1Addr) >> 3;
138  pkt->setBE(jBusData1[index]);
139  return;
140  }
141 
142  if (accessAddr == JIntDataA0Addr) {
143  pkt->setBE(jBusData0[cpuid]);
144  return;
145  }
146 
147  if (accessAddr == JIntDataA1Addr) {
148  pkt->setBE(jBusData1[cpuid]);
149  return;
150  }
151 
152  if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
153  index = (accessAddr - JIntBusyAddr) >> 3;
154  data = jIntBusy[index].busy ? 1 << 5 : 0 |
156  pkt->setBE(data);
157  return;
158  }
159  if (accessAddr == JIntABusyAddr) {
160  data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
162  pkt->setBE(data);
163  return;
164  };
165 
166  panic("Read to unknown JBus offset 0x%x\n", accessAddr);
167 }
168 
169 Tick
171 {
172  if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
173  writeIob(pkt);
174  else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
175  writeJBus(pkt);
176  else
177  panic("Invalid address reached Iob\n");
178 
179 
180  pkt->makeAtomicResponse();
181  return pioDelay;
182 }
183 
184 void
186 {
187  Addr accessAddr = pkt->getAddr() - iobManAddr;
188  int index;
189  uint64_t data;
190 
191  assert(IntManAddr == 0);
192  if (accessAddr < IntManAddr + IntManSize) {
193  index = (accessAddr - IntManAddr) >> 3;
194  data = pkt->getBE<uint64_t>();
195  intMan[index].cpu = bits(data,12,8);
196  intMan[index].vector = bits(data,5,0);
197  DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
198  intMan[index].cpu, intMan[index].vector);
199  return;
200  }
201 
202  if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
203  index = (accessAddr - IntCtlAddr) >> 3;
204  data = pkt->getBE<uint64_t>();
205  intCtl[index].mask = bits(data,2,2);
206  if (bits(data,1,1))
207  intCtl[index].pend = false;
208  DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
209  intCtl[index].pend, bits(data,2,2));
210  return;
211  }
212 
213  if (accessAddr == JIntVecAddr) {
214  jIntVec = bits(pkt->getBE<uint64_t>(), 5,0);
215  DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
216  return;
217  }
218 
219  if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
220  Type type;
221  int cpu_id;
222  int vector;
223  index = (accessAddr - IntManAddr) >> 3;
224  data = pkt->getBE<uint64_t>();
225  type = (Type)bits(data,17,16);
226  cpu_id = bits(data, 12,8);
227  vector = bits(data,5,0);
228  generateIpi(type,cpu_id, vector);
229  return;
230  }
231 
232  panic("Write to unknown IOB offset 0x%x\n", accessAddr);
233 }
234 
235 void
237 {
238  Addr accessAddr = pkt->getAddr() - iobJBusAddr;
239  ContextID cpuid = pkt->req->contextId();
240  int index;
241  uint64_t data;
242 
243  if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
244  index = (accessAddr - JIntBusyAddr) >> 3;
245  data = pkt->getBE<uint64_t>();
246  jIntBusy[index].busy = bits(data,5,5);
247  DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
248  jIntBusy[index].busy);
249  return;
250  }
251  if (accessAddr == JIntABusyAddr) {
252  data = pkt->getBE<uint64_t>();
253  jIntBusy[cpuid].busy = bits(data,5,5);
254  DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
255  jIntBusy[cpuid].busy);
256  return;
257  };
258 
259  panic("Write to unknown JBus offset 0x%x\n", accessAddr);
260 }
261 
262 void
264 {
265  assert(devid < NumDeviceIds);
266  if (intCtl[devid].mask)
267  return;
268  intCtl[devid].mask = true;
269  intCtl[devid].pend = true;
270  DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
271  devid, intMan[devid].cpu, intMan[devid].vector);
272  auto tc = sys->threads[intMan[devid].cpu];
273  tc->getCpuPtr()->postInterrupt(tc->threadId(), SparcISA::IT_INT_VEC,
274  intMan[devid].vector);
275 }
276 
277 
278 void
279 Iob::generateIpi(Type type, int cpu_id, int vector)
280 {
283  if (cpu_id >= sys->threads.size())
284  return;
285 
286  auto tc = sys->threads[cpu_id];
287  switch (type) {
288  case 0: // interrupt
289  DPRINTF(Iob,
290  "Generating interrupt because of I/O write to cpu: "
291  "%d vec %d\n",
292  cpu_id, vector);
293  tc->getCpuPtr()->postInterrupt(
294  tc->threadId(), SparcISA::IT_INT_VEC, vector);
295  break;
296  case 1: // reset
297  warn("Sending reset to CPU: %d\n", cpu_id);
298  if (vector != por->trapType())
299  panic("Don't know how to set non-POR reset to cpu\n");
300  por->invoke(tc);
301  tc->activate();
302  break;
303  case 2: // idle -- this means stop executing and don't wake on interrupts
304  DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
305  tc->halt();
306  break;
307  case 3: // resume
308  DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
309  tc->activate();
310  break;
311  default:
312  panic("Invalid type to generate ipi\n");
313  }
314 }
315 
316 bool
317 Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
318 {
319  // If we are already dealing with an interrupt for that cpu we can't deal
320  // with another one right now... come back later
321  if (jIntBusy[cpu_id].busy)
322  return false;
323 
324  DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n",
325  source, cpu_id, jIntVec);
326 
327  jIntBusy[cpu_id].busy = true;
328  jIntBusy[cpu_id].source = source;
329  jBusData0[cpu_id] = d0;
330  jBusData1[cpu_id] = d1;
331 
332  auto tc = sys->threads[cpu_id];
333  tc->getCpuPtr()->postInterrupt(
334  tc->threadId(), SparcISA::IT_INT_VEC, jIntVec);
335  return true;
336 }
337 
340 {
341  AddrRangeList ranges;
342  ranges.push_back(RangeSize(iobManAddr, iobManSize));
343  ranges.push_back(RangeSize(iobJBusAddr, iobJBusSize));
344  return ranges;
345 }
346 
347 
348 void
350 {
351 
355  for (int x = 0; x < NumDeviceIds; x++) {
356  ScopedCheckpointSection sec(cp, csprintf("Int%d", x));
357  paramOut(cp, "cpu", intMan[x].cpu);
358  paramOut(cp, "vector", intMan[x].vector);
359  paramOut(cp, "mask", intCtl[x].mask);
360  paramOut(cp, "pend", intCtl[x].pend);
361  };
362  for (int x = 0; x < MaxNiagaraProcs; x++) {
363  ScopedCheckpointSection sec(cp, csprintf("jIntBusy%d", x));
364  paramOut(cp, "busy", jIntBusy[x].busy);
365  paramOut(cp, "source", jIntBusy[x].source);
366  };
367 }
368 
369 void
371 {
375  for (int x = 0; x < NumDeviceIds; x++) {
376  ScopedCheckpointSection sec(cp, csprintf("Int%d", x));
377  paramIn(cp, "cpu", intMan[x].cpu);
378  paramIn(cp, "vector", intMan[x].vector);
379  paramIn(cp, "mask", intCtl[x].mask);
380  paramIn(cp, "pend", intCtl[x].pend);
381  };
382  for (int x = 0; x < MaxNiagaraProcs; x++) {
383  ScopedCheckpointSection sec(cp, csprintf("jIntBusy%d", x));
384  paramIn(cp, "busy", jIntBusy[x].busy);
385  paramIn(cp, "source", jIntBusy[x].source);
386  };
387 }
388 
389 } // namespace gem5
gem5::IntCtlAddr
const Addr IntCtlAddr
Definition: iob.hh:47
gem5::SparcISA::PowerOnReset
Definition: faults.hh:101
gem5::JIntData1Addr
const Addr JIntData1Addr
Definition: iob.hh:56
gem5::Iob::intMan
IntMan intMan[NumDeviceIds]
Definition: iob.hh:116
gem5::Iob::IntMan::vector
int vector
Definition: iob.hh:93
warn
#define warn(...)
Definition: logging.hh:245
gem5::System::Threads::size
int size() const
Definition: system.hh:216
gem5::IntVecDisAddr
const Addr IntVecDisAddr
Definition: iob.hh:50
system.hh
data
const char data[]
Definition: circlebuf.test.cc:48
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Bitfield< 28, 21 > cpuid
Definition: dt_constants.hh:95
gem5::JIntDataA0Addr
const Addr JIntDataA0Addr
Definition: iob.hh:57
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::IntCtlSize
const Addr IntCtlSize
Definition: iob.hh:48
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Definition: intmessage.hh:48
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Definition: pra_constants.hh:47
gem5::RangeSize
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Definition: addr_range.hh:661
gem5::Iob::IntBusy::source
int source
Definition: iob.hh:105
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A pointer to the original request.
Definition: packet.hh:366
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Definition: serialize.hh:68
gem5::Iob::pioDelay
Tick pioDelay
Definition: iob.hh:79
gem5::Iob::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: iob.cc:339
gem5::IntManSize
const Addr IntManSize
Definition: iob.hh:46
gem5::Iob::jIntBusy
IntBusy jIntBusy[MaxNiagaraProcs]
Definition: iob.hh:121
gem5::Iob::iobManSize
Addr iobManSize
Definition: iob.hh:76
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::Iob::writeJBus
void writeJBus(PacketPtr pkt)
Definition: iob.cc:236
gem5::Iob::jBusData0
uint64_t jBusData0[MaxNiagaraProcs]
Definition: iob.hh:119
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Definition: cprintf.hh:161
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Definition: packet.hh:1043
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Definition: iob.cc:317
faults.hh
gem5::Iob
Definition: iob.hh:72
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Iob::IntCtl::pend
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Definition: iob.hh:99
iob.hh
gem5::Iob::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: iob.cc:170
gem5::Iob::DeviceId
DeviceId
Definition: iob.hh:81
gem5::Iob::readJBus
void readJBus(PacketPtr pkt)
Definition: iob.cc:120
gem5::Iob::jBusData1
uint64_t jBusData1[MaxNiagaraProcs]
Definition: iob.hh:120
gem5::Iob::iobJBusAddr
Addr iobJBusAddr
Definition: iob.hh:77
gem5::Iob::intCtl
IntCtl intCtl[NumDeviceIds]
Definition: iob.hh:117
gem5::Iob::writeIob
void writeIob(PacketPtr pkt)
Definition: iob.cc:185
bitfield.hh
faults.hh
gem5::Iob::iobManAddr
Addr iobManAddr
Definition: iob.hh:75
gem5::MaxNiagaraProcs
const int MaxNiagaraProcs
Definition: iob.hh:43
gem5::SparcISA::SparcFault
Definition: faults.hh:84
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::Packet::getBE
T getBE() const
Get the data in the packet byte swapped from big endian to host endian.
Definition: packet_access.hh:71
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Iob::Iob
Iob(const Params &p)
Definition: iob.cc:56
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Definition: pra_constants.hh:326
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uint64_t Tick
Tick count type.
Definition: types.hh:58
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Definition: io_device.hh:105
gem5::X86ISA::type
type
Definition: misc.hh:733
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Bitfield< 20, 16 > d1
Definition: types.hh:66
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void receiveDeviceInterrupt(DeviceId devid)
Definition: iob.cc:263
gem5::Iob::IntCtl::mask
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Definition: iob.hh:98
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void setBE(T v)
Set the value in the data pointer to v as big endian.
Definition: packet_access.hh:101
port.hh
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Iob::NumDeviceIds
@ NumDeviceIds
Definition: iob.hh:87
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
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Definition: faults.hh:90
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int cpu
Definition: iob.hh:92
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const Addr JIntBusySize
Definition: iob.hh:60
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Iob::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: iob.cc:76
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
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Definition: iob.hh:104
gem5::Iob::Type
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Definition: iob.hh:108
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void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: iob.cc:349
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const Addr JIntVecAddr
Definition: iob.hh:49
gem5::Iob::jIntVec
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Definition: iob.hh:118
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Definition: pagetable.hh:73
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const Addr JIntData0Addr
Definition: iob.hh:55
gem5::JIntBusyAddr
const Addr JIntBusyAddr
Definition: iob.hh:59
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void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
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Threads threads
Definition: system.hh:316
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void generateIpi(Type type, int cpu_id, int vector)
Definition: iob.cc:279
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Definition: types.cc:72
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Definition: iob.hh:78
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int ContextID
Globally unique thread context ID.
Definition: types.hh:246
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const Addr IntManAddr
Definition: iob.hh:45
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void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: iob.cc:370
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Definition: serialize.hh:66
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Definition: types.hh:65
std::list< AddrRange >
gem5::Packet::getAddr
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Definition: packet.hh:781
gem5::IntVecDisSize
const Addr IntVecDisSize
Definition: iob.hh:51
gem5::SparcISA::SparcFaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:500
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::JIntABusyAddr
const Addr JIntABusyAddr
Definition: iob.hh:61
gem5::Serializable::ScopedCheckpointSection
Definition: serialize.hh:172
thread_context.hh
gem5::JIntDataA1Addr
const Addr JIntDataA1Addr
Definition: iob.hh:58
gem5::SparcISA::IT_INT_VEC
@ IT_INT_VEC
Definition: interrupts.hh:50
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Iob::readIob
void readIob(PacketPtr pkt)
Definition: iob.cc:91

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