gem5  v22.0.0.1
iob.hh
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28 
34 #ifndef __DEV_SPARC_IOB_HH__
35 #define __DEV_SPARC_IOB_HH__
36 
37 #include "dev/io_device.hh"
38 #include "params/Iob.hh"
39 
40 namespace gem5
41 {
42 
43 const int MaxNiagaraProcs = 32;
44 // IOB Managment Addresses
45 const Addr IntManAddr = 0x0000;
46 const Addr IntManSize = 0x0020;
47 const Addr IntCtlAddr = 0x0400;
48 const Addr IntCtlSize = 0x0020;
49 const Addr JIntVecAddr = 0x0A00;
50 const Addr IntVecDisAddr = 0x0800;
51 const Addr IntVecDisSize = 0x0100;
52 
53 
54 // IOB Control Addresses
55 const Addr JIntData0Addr = 0x0400;
56 const Addr JIntData1Addr = 0x0500;
57 const Addr JIntDataA0Addr = 0x0600;
58 const Addr JIntDataA1Addr = 0x0700;
59 const Addr JIntBusyAddr = 0x0900;
60 const Addr JIntBusySize = 0x0100;
61 const Addr JIntABusyAddr = 0x0B00;
62 
63 
64 // IOB Masks
65 const uint64_t IntManMask = 0x01F3F;
66 const uint64_t IntCtlMask = 0x00006;
67 const uint64_t JIntVecMask = 0x0003F;
68 const uint64_t IntVecDis = 0x31F3F;
69 const uint64_t JIntBusyMask = 0x0003F;
70 
71 
72 class Iob : public PioDevice
73 {
74  private:
80 
81  enum DeviceId
82  {
83  Interal = 0,
84  Error = 1,
85  SSI = 2,
86  Reserved = 3,
88  };
89 
90  struct IntMan
91  {
92  int cpu;
93  int vector;
94  };
95 
96  struct IntCtl
97  {
98  bool mask;
99  bool pend;
100  };
101 
102  struct IntBusy
103  {
104  bool busy;
105  int source;
106  };
107 
108  enum Type
109  {
114  };
115 
118  uint64_t jIntVec;
122 
123  void writeIob(PacketPtr pkt);
124  void writeJBus(PacketPtr pkt);
125  void readIob(PacketPtr pkt);
126  void readJBus(PacketPtr pkt);
127 
128  public:
129  PARAMS(Iob);
130  Iob(const Params &p);
131 
132  Tick read(PacketPtr pkt) override;
133  Tick write(PacketPtr pkt) override;
134  void generateIpi(Type type, int cpu_id, int vector);
135  void receiveDeviceInterrupt(DeviceId devid);
136  bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
137  uint64_t d1);
138 
139  AddrRangeList getAddrRanges() const override;
140 
141  void serialize(CheckpointOut &cp) const override;
142  void unserialize(CheckpointIn &cp) override;
143 };
144 
145 } // namespace gem5
146 
147 #endif //__DEV_SPARC_IOB_HH__
gem5::IntCtlAddr
const Addr IntCtlAddr
Definition: iob.hh:47
gem5::Iob::IntCtl
Definition: iob.hh:96
gem5::Iob::intMan
IntMan intMan[NumDeviceIds]
Definition: iob.hh:116
gem5::JIntData1Addr
const Addr JIntData1Addr
Definition: iob.hh:56
io_device.hh
gem5::Iob::IntMan::vector
int vector
Definition: iob.hh:93
gem5::IntCtlMask
const uint64_t IntCtlMask
Definition: iob.hh:66
gem5::IntVecDisAddr
const Addr IntVecDisAddr
Definition: iob.hh:50
gem5::JIntDataA0Addr
const Addr JIntDataA0Addr
Definition: iob.hh:57
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
gem5::IntCtlSize
const Addr IntCtlSize
Definition: iob.hh:48
gem5::X86ISA::vector
Bitfield< 15, 8 > vector
Definition: intmessage.hh:48
gem5::Iob::IntBusy::source
int source
Definition: iob.hh:105
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Iob::pioDelay
Tick pioDelay
Definition: iob.hh:79
gem5::Iob::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: iob.cc:339
gem5::IntManSize
const Addr IntManSize
Definition: iob.hh:46
gem5::Iob::jIntBusy
IntBusy jIntBusy[MaxNiagaraProcs]
Definition: iob.hh:121
gem5::Iob::iobManSize
Addr iobManSize
Definition: iob.hh:76
gem5::JIntBusyMask
const uint64_t JIntBusyMask
Definition: iob.hh:69
gem5::Iob::writeJBus
void writeJBus(PacketPtr pkt)
Definition: iob.cc:236
gem5::Iob::jBusData0
uint64_t jBusData0[MaxNiagaraProcs]
Definition: iob.hh:119
gem5::Iob::SSI
@ SSI
Definition: iob.hh:85
gem5::Iob::receiveJBusInterrupt
bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
Definition: iob.cc:317
gem5::Iob::Interrupt
@ Interrupt
Definition: iob.hh:110
gem5::Iob
Definition: iob.hh:72
gem5::Iob::IntMan
Definition: iob.hh:90
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Iob::IntBusy
Definition: iob.hh:102
gem5::Iob::IntCtl::pend
bool pend
Definition: iob.hh:99
gem5::Iob::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: iob.cc:170
gem5::Iob::DeviceId
DeviceId
Definition: iob.hh:81
gem5::Iob::readJBus
void readJBus(PacketPtr pkt)
Definition: iob.cc:120
gem5::Iob::jBusData1
uint64_t jBusData1[MaxNiagaraProcs]
Definition: iob.hh:120
gem5::Iob::iobJBusAddr
Addr iobJBusAddr
Definition: iob.hh:77
gem5::Iob::intCtl
IntCtl intCtl[NumDeviceIds]
Definition: iob.hh:117
gem5::Iob::writeIob
void writeIob(PacketPtr pkt)
Definition: iob.cc:185
gem5::Iob::iobManAddr
Addr iobManAddr
Definition: iob.hh:75
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::MaxNiagaraProcs
const int MaxNiagaraProcs
Definition: iob.hh:43
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Iob::Iob
Iob(const Params &p)
Definition: iob.cc:56
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::PowerISA::d1
Bitfield< 20, 16 > d1
Definition: types.hh:66
gem5::Iob::receiveDeviceInterrupt
void receiveDeviceInterrupt(DeviceId devid)
Definition: iob.cc:263
gem5::Iob::IntCtl::mask
bool mask
Definition: iob.hh:98
gem5::Iob::PARAMS
PARAMS(Iob)
gem5::Iob::NumDeviceIds
@ NumDeviceIds
Definition: iob.hh:87
gem5::Iob::Idle
@ Idle
Definition: iob.hh:112
gem5::Iob::IntMan::cpu
int cpu
Definition: iob.hh:92
gem5::Iob::Interal
@ Interal
Definition: iob.hh:83
gem5::JIntBusySize
const Addr JIntBusySize
Definition: iob.hh:60
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Iob::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: iob.cc:76
gem5::Iob::IntBusy::busy
bool busy
Definition: iob.hh:104
gem5::Iob::Type
Type
Definition: iob.hh:108
gem5::Iob::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: iob.cc:349
gem5::JIntVecAddr
const Addr JIntVecAddr
Definition: iob.hh:49
gem5::Iob::jIntVec
uint64_t jIntVec
Definition: iob.hh:118
gem5::JIntData0Addr
const Addr JIntData0Addr
Definition: iob.hh:55
gem5::JIntBusyAddr
const Addr JIntBusyAddr
Definition: iob.hh:59
gem5::Iob::Resume
@ Resume
Definition: iob.hh:113
gem5::Iob::generateIpi
void generateIpi(Type type, int cpu_id, int vector)
Definition: iob.cc:279
gem5::Iob::iobJBusSize
Addr iobJBusSize
Definition: iob.hh:78
gem5::Iob::Reset
@ Reset
Definition: iob.hh:111
gem5::IntManAddr
const Addr IntManAddr
Definition: iob.hh:45
gem5::Iob::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: iob.cc:370
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::PowerISA::d0
Bitfield< 15, 6 > d0
Definition: types.hh:65
std::list< AddrRange >
gem5::IntVecDisSize
const Addr IntVecDisSize
Definition: iob.hh:51
gem5::JIntVecMask
const uint64_t JIntVecMask
Definition: iob.hh:67
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::IntVecDis
const uint64_t IntVecDis
Definition: iob.hh:68
gem5::JIntABusyAddr
const Addr JIntABusyAddr
Definition: iob.hh:61
gem5::Iob::Reserved
@ Reserved
Definition: iob.hh:86
gem5::IntManMask
const uint64_t IntManMask
Definition: iob.hh:65
gem5::JIntDataA1Addr
const Addr JIntDataA1Addr
Definition: iob.hh:58
gem5::Iob::Error
@ Error
Definition: iob.hh:84
gem5::Iob::readIob
void readIob(PacketPtr pkt)
Definition: iob.cc:91

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