gem5  v21.1.0.2
interrupts.hh
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28 
29 #ifndef __ARCH_SPARC_INTERRUPT_HH__
30 #define __ARCH_SPARC_INTERRUPT_HH__
31 
33 #include "arch/sparc/faults.hh"
34 #include "arch/sparc/regs/misc.hh"
35 #include "cpu/thread_context.hh"
36 #include "debug/Interrupt.hh"
37 #include "params/SparcInterrupts.hh"
38 #include "sim/sim_object.hh"
39 
40 namespace gem5
41 {
42 
43 namespace SparcISA
44 {
45 
47 {
56 };
57 
58 class Interrupts : public BaseInterrupts
59 {
60  private:
62  uint64_t intStatus;
63 
64  public:
65 
66  using Params = SparcInterruptsParams;
67 
69  {
70  clearAll();
71  }
72 
73  int
74  InterruptLevel(uint64_t softint)
75  {
76  if (softint & 0x10000 || softint & 0x1)
77  return 14;
78 
79  int level = 15;
80  while (level > 0 && !(1 << level & softint))
81  level--;
82  if (1 << level & softint)
83  return level;
84  return 0;
85  }
86 
87  void
88  post(int int_num, int index) override
89  {
90  DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
91  assert(int_num >= 0 && int_num < NumInterruptTypes);
92  assert(index >= 0 && index < 64);
93 
94  interrupts[int_num] |= 1ULL << index;
95  intStatus |= 1ULL << int_num;
96  }
97 
98  void
99  clear(int int_num, int index) override
100  {
101  DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
102  assert(int_num >= 0 && int_num < NumInterruptTypes);
103  assert(index >= 0 && index < 64);
104 
105  interrupts[int_num] &= ~(1ULL << index);
106  if (!interrupts[int_num])
107  intStatus &= ~(1ULL << int_num);
108  }
109 
110  void
111  clearAll() override
112  {
113  for (int i = 0; i < NumInterruptTypes; ++i) {
114  interrupts[i] = 0;
115  }
116  intStatus = 0;
117  }
118 
119  bool
120  checkInterrupts() const override
121  {
122  if (!intStatus)
123  return false;
124 
125  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
126  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
127 
128  // THESE ARE IN ORDER OF PRIORITY
129  // since there are early returns, and the highest
130  // priority interrupts should get serviced,
131  // it is v. important that new interrupts are inserted
132  // in the right order of processing
133  if (hpstate.hpriv) {
134  if (pstate.ie) {
135  if (interrupts[IT_HINTP]) {
136  // This will be cleaned by a HINTP write
137  return true;
138  }
139  if (interrupts[IT_INT_VEC]) {
140  // this will be cleared by an ASI read (or write)
141  return true;
142  }
143  }
144  } else {
146  // this is cleared by deasserting HPSTATE::tlz
147  return true;
148  }
149  // HStick matches always happen in priv mode (ie doesn't matter)
150  if (interrupts[IT_HINTP]) {
151  return true;
152  }
153  if (interrupts[IT_INT_VEC]) {
154  // this will be cleared by an ASI read (or write)
155  return true;
156  }
157  if (pstate.ie) {
158  if (interrupts[IT_CPU_MONDO]) {
159  return true;
160  }
161  if (interrupts[IT_DEV_MONDO]) {
162  return true;
163  }
164  if (interrupts[IT_SOFT_INT]) {
165  return true;
166  }
167 
168  if (interrupts[IT_RES_ERROR]) {
169  return true;
170  }
171  } // !hpriv && pstate.ie
172  } // !hpriv
173 
174  return false;
175  }
176 
177  Fault
178  getInterrupt() override
179  {
180  assert(checkInterrupts());
181 
182  HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
183  PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
184 
185  // THESE ARE IN ORDER OF PRIORITY
186  // since there are early returns, and the highest
187  // priority interrupts should get serviced,
188  // it is v. important that new interrupts are inserted
189  // in the right order of processing
190  if (hpstate.hpriv) {
191  if (pstate.ie) {
192  if (interrupts[IT_HINTP]) {
193  // This will be cleaned by a HINTP write
194  return std::make_shared<HstickMatch>();
195  }
196  if (interrupts[IT_INT_VEC]) {
197  // this will be cleared by an ASI read (or write)
198  return std::make_shared<InterruptVector>();
199  }
200  }
201  } else {
203  // this is cleared by deasserting HPSTATE::tlz
204  return std::make_shared<TrapLevelZero>();
205  }
206  // HStick matches always happen in priv mode (ie doesn't matter)
207  if (interrupts[IT_HINTP]) {
208  return std::make_shared<HstickMatch>();
209  }
210  if (interrupts[IT_INT_VEC]) {
211  // this will be cleared by an ASI read (or write)
212  return std::make_shared<InterruptVector>();
213  }
214  if (pstate.ie) {
215  if (interrupts[IT_CPU_MONDO]) {
216  return std::make_shared<CpuMondo>();
217  }
218  if (interrupts[IT_DEV_MONDO]) {
219  return std::make_shared<DevMondo>();
220  }
221  if (interrupts[IT_SOFT_INT]) {
223  return std::make_shared<InterruptLevelN>(level);
224  }
225 
226  if (interrupts[IT_RES_ERROR]) {
227  return std::make_shared<ResumableError>();
228  }
229  } // !hpriv && pstate.ie
230  } // !hpriv
231  return NoFault;
232  }
233 
234  void updateIntrInfo() override {}
235 
236  uint64_t
237  get_vec(int int_num)
238  {
239  assert(int_num >= 0 && int_num < NumInterruptTypes);
240  return interrupts[int_num];
241  }
242 
243  void
244  serialize(CheckpointOut &cp) const override
245  {
248  }
249 
250  void
251  unserialize(CheckpointIn &cp) override
252  {
255  }
256 };
257 
258 } // namespace SparcISA
259 } // namespace gem5
260 
261 #endif // __ARCH_SPARC_INTERRUPT_HH__
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
misc.hh
gem5::SparcISA::Interrupts::post
void post(int int_num, int index) override
Definition: interrupts.hh:88
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::SparcISA::Interrupts::clearAll
void clearAll() override
Definition: interrupts.hh:111
gem5::SparcISA::IT_TRAP_LEVEL_ZERO
@ IT_TRAP_LEVEL_ZERO
Definition: interrupts.hh:48
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::SparcISA::IT_CPU_MONDO
@ IT_CPU_MONDO
Definition: interrupts.hh:51
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:44
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SparcISA::Interrupts::updateIntrInfo
void updateIntrInfo() override
Definition: interrupts.hh:234
gem5::SparcISA::IT_SOFT_INT
@ IT_SOFT_INT
Definition: interrupts.hh:54
gem5::SparcISA::NumInterruptTypes
@ NumInterruptTypes
Definition: interrupts.hh:55
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::SparcISA::IT_RES_ERROR
@ IT_RES_ERROR
Definition: interrupts.hh:53
gem5::SparcISA::Interrupts::checkInterrupts
bool checkInterrupts() const override
Definition: interrupts.hh:120
gem5::SparcISA::Interrupts::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: interrupts.hh:251
faults.hh
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
sim_object.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::SparcISA::Interrupts::getInterrupt
Fault getInterrupt() override
Definition: interrupts.hh:178
gem5::SparcISA::IT_DEV_MONDO
@ IT_DEV_MONDO
Definition: interrupts.hh:52
gem5::SparcISA::Interrupts::intStatus
uint64_t intStatus
Definition: interrupts.hh:62
gem5::SparcISA::Interrupts::InterruptLevel
int InterruptLevel(uint64_t softint)
Definition: interrupts.hh:74
gem5::SparcISA::Interrupts::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: interrupts.hh:244
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::SparcISA::Interrupts::get_vec
uint64_t get_vec(int int_num)
Definition: interrupts.hh:237
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::SparcISA::Interrupts
Definition: interrupts.hh:58
gem5::SparcISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:46
gem5::SparcISA::Interrupts::Interrupts
Interrupts(const Params &p)
Definition: interrupts.hh:68
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
interrupts.hh
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::Interrupts::interrupts
uint64_t interrupts[NumInterruptTypes]
Definition: interrupts.hh:61
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::Interrupts::clear
void clear(int int_num, int index) override
Definition: interrupts.hh:99
gem5::BaseInterrupts::Params
BaseInterruptsParams Params
Definition: interrupts.hh:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::IT_HINTP
@ IT_HINTP
Definition: interrupts.hh:49
gem5::ArmISA::Interrupt
Definition: faults.hh:557
thread_context.hh
gem5::SparcISA::IT_INT_VEC
@ IT_INT_VEC
Definition: interrupts.hh:50

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