gem5  v21.1.0.2
base.hh
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41 
42 #ifndef __CPU_BASE_HH__
43 #define __CPU_BASE_HH__
44 
45 #include <vector>
46 
47 // Before we do anything else, check if this build is the NULL ISA,
48 // and if so stop here
49 #include "config/the_isa.hh"
50 #if THE_ISA == NULL_ISA
51 #error Including BaseCPU in a system without CPU support
52 #else
54 #include "base/statistics.hh"
55 #include "mem/port_proxy.hh"
56 #include "sim/clocked_object.hh"
57 #include "sim/eventq.hh"
58 #include "sim/full_system.hh"
59 #include "sim/insttracer.hh"
60 #include "sim/probe/pmu.hh"
61 #include "sim/probe/probe.hh"
62 #include "sim/system.hh"
63 #include "debug/Mwait.hh"
64 
65 namespace gem5
66 {
67 
68 class BaseCPU;
69 struct BaseCPUParams;
70 class CheckerCPU;
71 class ThreadContext;
72 
74 {
76  bool doMonitor(PacketPtr pkt);
77 
78  bool armed;
81  uint64_t val;
82  bool waiting; // 0=normal, 1=mwaiting
83  bool gotWakeup;
84 };
85 
86 class CPUProgressEvent : public Event
87 {
88  protected:
93 
94  public:
95  CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
96 
97  void process();
98 
99  void interval(Tick ival) { _interval = ival; }
100  Tick interval() { return _interval; }
101 
102  void repeatEvent(bool repeat) { _repeatEvent = repeat; }
103 
104  virtual const char *description() const;
105 };
106 
107 class BaseCPU : public ClockedObject
108 {
109  protected:
110 
114 
115  // every cpu has an id, put it in the base cpu
116  // Set at initialization, only time a cpuId might change is during a
117  // takeover (which should be done from within the BaseCPU anyway,
118  // therefore no setCpuId() method is provided
119  int _cpuId;
120 
126  const uint32_t _socketId;
127 
130 
133 
139  uint32_t _taskId;
140 
143  uint32_t _pid;
144 
147 
149  const unsigned int _cacheLineSize;
150 
153  {
155 
158 
161  };
162 
167  static std::unique_ptr<GlobalStats> globalStats;
168 
169  public:
170 
177  virtual Port &getDataPort() = 0;
178 
185  virtual Port &getInstPort() = 0;
186 
188  int cpuId() const { return _cpuId; }
189 
191  uint32_t socketId() const { return _socketId; }
192 
197 
208  Port &getPort(const std::string &if_name,
209  PortID idx=InvalidPortID) override;
210 
212  uint32_t taskId() const { return _taskId; }
214  void taskId(uint32_t id) { _taskId = id; }
215 
216  uint32_t getPid() const { return _pid; }
217  void setPid(uint32_t pid) { _pid = pid; }
218 
221  // @todo remove me after debugging with legion done
222  Tick instCount() { return instCnt; }
223 
224  protected:
226 
227  public:
230  {
231  if (interrupts.empty())
232  return NULL;
233 
234  assert(interrupts.size() > tid);
235  return interrupts[tid];
236  }
237 
238  virtual void wakeup(ThreadID tid) = 0;
239 
240  void
241  postInterrupt(ThreadID tid, int int_num, int index);
242 
243  void
244  clearInterrupt(ThreadID tid, int int_num, int index)
245  {
246  interrupts[tid]->clear(int_num, index);
247  }
248 
249  void
251  {
252  interrupts[tid]->clearAll();
253  }
254 
255  bool
257  {
258  return FullSystem && interrupts[tid]->checkInterrupts();
259  }
260 
261  protected:
263 
265 
266  public:
267 
268 
271  static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
272 
275 
277  virtual void activateContext(ThreadID thread_num);
278 
281  virtual void suspendContext(ThreadID thread_num);
282 
284  virtual void haltContext(ThreadID thread_num);
285 
287  int findContext(ThreadContext *tc);
288 
290  virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
291 
293  unsigned numContexts() {
294  return static_cast<unsigned>(threadContexts.size());
295  }
296 
299  { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
300 
301  public:
302  PARAMS(BaseCPU);
303  BaseCPU(const Params &params, bool is_checker = false);
304  virtual ~BaseCPU();
305 
306  void init() override;
307  void startup() override;
308  void regStats() override;
309 
310  void regProbePoints() override;
311 
312  void registerThreadContexts();
313 
314  // Functions to deschedule and reschedule the events to enter the
315  // power gating sleep before and after checkpoiting respectively.
318 
326  virtual void switchOut();
327 
339  virtual void takeOverFrom(BaseCPU *cpu);
340 
350  void flushTLBs();
351 
357  bool switchedOut() const { return _switchedOut; }
358 
368  virtual void verifyMemoryMode() const { };
369 
375 
377 
381  inline unsigned int cacheLineSize() const { return _cacheLineSize; }
382 
393  void serialize(CheckpointOut &cp) const override;
394 
405  void unserialize(CheckpointIn &cp) override;
406 
413  virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
414 
421  virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
422 
423  virtual Counter totalInsts() const = 0;
424 
425  virtual Counter totalOps() const = 0;
426 
440  void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
441 
449  uint64_t getCurrentInstCount(ThreadID tid);
450 
451  public:
464  virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
465 
466  protected:
474  probing::PMUUPtr pmuProbePoint(const char *name);
475 
486 
491 
494 
497 
500 
512  enum CPUState
513  {
517  };
518 
521 
523  inline void updateCycleCounters(CPUState state)
524  {
525  uint32_t delta = curCycle() - previousCycle;
526 
527  if (previousState == CPU_STATE_ON) {
528  ppActiveCycles->notify(delta);
529  }
530 
531  switch (state)
532  {
533  case CPU_STATE_WAKEUP:
534  ppSleeping->notify(false);
535  break;
536  case CPU_STATE_SLEEP:
537  ppSleeping->notify(true);
538  break;
539  default:
540  break;
541  }
542 
543  ppAllCycles->notify(delta);
544 
546  previousState = state;
547  }
548 
549  // Function tracing
550  private:
552  std::ostream *functionTraceStream;
556  void enableFunctionTrace();
558 
559  private:
561 
562  public:
564  {
567  }
568 
569  static int numSimulatedCPUs() { return cpuList.size(); }
571  {
572  Counter total = 0;
573 
574  int size = cpuList.size();
575  for (int i = 0; i < size; ++i)
576  total += cpuList[i]->totalInsts();
577 
578  return total;
579  }
580 
582  {
583  Counter total = 0;
584 
585  int size = cpuList.size();
586  for (int i = 0; i < size; ++i)
587  total += cpuList[i]->totalOps();
588 
589  return total;
590  }
591 
592  public:
594  {
596  // Number of CPU cycles simulated
600  } baseStats;
601 
602  private:
604 
605  public:
606  void armMonitor(ThreadID tid, Addr address);
607  bool mwait(ThreadID tid, PacketPtr pkt);
608  void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
610  {
611  assert(tid < numThreads);
612  return &addressMonitor[tid];
613  }
614 
616 
617  // Enables CPU to enter power gating on a configurable cycle count
618  protected:
619  void enterPwrGating();
620 
622  const bool powerGatingOnIdle;
624 };
625 
626 } // namespace gem5
627 
628 #endif // THE_ISA == NULL_ISA
629 
630 #endif // __CPU_BASE_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::CPUProgressEvent::CPUProgressEvent
CPUProgressEvent(BaseCPU *_cpu, Tick ival=0)
Definition: base.cc:86
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::CPUProgressEvent::lastNumInst
Counter lastNumInst
Definition: base.hh:90
gem5::BaseCPU::currentFunctionStart
Addr currentFunctionStart
Definition: base.hh:553
gem5::BaseCPU::armMonitor
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
gem5::BaseCPU::functionTraceStream
std::ostream * functionTraceStream
Definition: base.hh:552
gem5::ProbePointArg::notify
void notify(const Arg &arg)
called at the ProbePoint call site, passes arg to each listener.
Definition: probe.hh:313
gem5::BaseCPU::switchedOut
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:357
gem5::BaseCPU::tracer
Trace::InstTracer * tracer
Definition: base.hh:264
gem5::BaseCPU::interrupts
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:225
gem5::BaseCPU::BaseCPUStats::numWorkItemsCompleted
statistics::Scalar numWorkItemsCompleted
Definition: base.hh:599
gem5::BaseCPU::getInstPort
virtual Port & getInstPort()=0
Purely virtual method that returns a reference to the instruction port.
gem5::BaseCPU::mwaitAtomic
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
system.hh
gem5::BaseCPU::ppSleeping
ProbePointArg< bool > * ppSleeping
ProbePoint that signals transitions of threadContexts sets.
Definition: base.hh:509
gem5::Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:195
gem5::BaseCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:315
gem5::BaseCPU::BaseCPUStats::BaseCPUStats
BaseCPUStats(statistics::Group *parent)
Definition: base.cc:374
gem5::BaseCPU::enableFunctionTrace
void enableFunctionTrace()
Definition: base.cc:184
gem5::BaseCPU::unserializeThread
virtual void unserializeThread(CheckpointIn &cp, ThreadID tid)
Unserialize one thread.
Definition: base.hh:421
gem5::CPUProgressEvent::process
void process()
Definition: base.cc:95
gem5::BaseCPU::getInterruptController
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:229
gem5::BaseCPU::numContexts
unsigned numContexts()
Get the number of thread contexts available.
Definition: base.hh:293
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::BaseCPU::GlobalStats::hostOpRate
statistics::Formula hostOpRate
Definition: base.hh:160
insttracer.hh
gem5::BaseCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: base.cc:651
gem5::BaseCPU::ppRetiredInsts
probing::PMUUPtr ppRetiredInsts
Instruction commit probe point.
Definition: base.hh:484
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::BaseCPU::pmuProbePoint
probing::PMUUPtr pmuProbePoint(const char *name)
Helper method to instantiate probe points belonging to this object.
Definition: base.cc:331
gem5::BaseCPU::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:381
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::AddressMonitor::AddressMonitor
AddressMonitor()
Definition: base.cc:682
gem5::AddressMonitor::doMonitor
bool doMonitor(PacketPtr pkt)
Definition: base.cc:688
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:523
gem5::BaseCPU::GlobalStats
Global CPU statistics that are merged into the Root object.
Definition: base.hh:152
gem5::BaseCPU::BaseCPU
BaseCPU(const Params &params, bool is_checker=false)
Definition: base.cc:127
gem5::CPUProgressEvent::interval
Tick interval()
Definition: base.hh:100
gem5::BaseCPU::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:272
gem5::BaseCPU::invldPid
static const uint32_t invldPid
Invalid or unknown Pid.
Definition: base.hh:271
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::BaseCPU::enterPwrGating
void enterPwrGating()
Definition: base.cc:534
gem5::AddressMonitor::vAddr
Addr vAddr
Definition: base.hh:79
gem5::BaseCPU::cpuList
static std::vector< BaseCPU * > cpuList
Static global cpu list.
Definition: base.hh:560
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::BaseCPU::numSimulatedOps
static Counter numSimulatedOps()
Definition: base.hh:581
std::vector
STL vector class.
Definition: stl.hh:37
gem5::BaseCPU::previousCycle
Cycles previousCycle
Definition: base.hh:519
gem5::BaseCPU::getPid
uint32_t getPid() const
Definition: base.hh:216
gem5::BaseCPU::instCount
Tick instCount()
Definition: base.hh:222
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::BaseCPU::socketId
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:191
gem5::BaseCPU::schedulePowerGatingEvent
void schedulePowerGatingEvent()
Definition: base.cc:460
gem5::BaseCPU::setPid
void setPid(uint32_t pid)
Definition: base.hh:217
gem5::BaseCPU::_taskId
uint32_t _taskId
An intrenal representation of a task identifier within gem5.
Definition: base.hh:139
gem5::BaseCPU::totalInsts
virtual Counter totalInsts() const =0
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:50
gem5::BaseCPU::ppAllCycles
probing::PMUUPtr ppAllCycles
CPU cycle counter even if any thread Context is suspended.
Definition: base.hh:496
gem5::AddressMonitor
Definition: base.hh:73
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
pmu.hh
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::BaseCPU::serializeThread
virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const
Serialize a single thread.
Definition: base.hh:413
gem5::BaseCPU::_cpuId
int _cpuId
Definition: base.hh:119
gem5::BaseCPU::regStats
void regStats() override
Callback to set stat parameters.
Definition: base.cc:386
gem5::BaseCPU::ppRetiredInstsPC
probing::PMUUPtr ppRetiredInstsPC
Definition: base.hh:485
gem5::BaseCPU::wakeup
virtual void wakeup(ThreadID tid)=0
gem5::BaseCPU::getDataPort
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
gem5::BaseCPU::deschedulePowerGatingEvent
void deschedulePowerGatingEvent()
Definition: base.cc:452
gem5::CPUProgressEvent::description
virtual const char * description() const
Return a C string describing the event.
Definition: base.cc:122
gem5::BaseCPU::suspendContext
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:502
gem5::BaseCPU::baseStats
gem5::BaseCPU::BaseCPUStats baseStats
gem5::BaseCPU::taskId
void taskId(uint32_t id)
Set cpu task id.
Definition: base.hh:214
gem5::BaseCPU::registerThreadContexts
void registerThreadContexts()
Definition: base.cc:424
gem5::BaseCPU::PARAMS
PARAMS(BaseCPU)
gem5::System
Definition: system.hh:77
gem5::BaseCPU::taskId
uint32_t taskId() const
Get cpu task id.
Definition: base.hh:212
gem5::BaseCPU::GlobalStats::simInsts
statistics::Value simInsts
Definition: base.hh:156
gem5::BaseCPU::ppRetiredStores
probing::PMUUPtr ppRetiredStores
Retired store instructions.
Definition: base.hh:490
gem5::BaseCPU::_dataRequestorId
RequestorID _dataRequestorId
data side request id that must be placed in all requests
Definition: base.hh:132
gem5::BaseCPU::scheduleInstStop
void scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
Schedule an event that exits the simulation loops after a predefined number of instructions.
Definition: base.cc:668
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::BaseCPU::flushTLBs
void flushTLBs()
Flush all TLBs in the CPU.
Definition: base.cc:616
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::probing::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
gem5::BaseCPU::pwrGatingLatency
const Cycles pwrGatingLatency
Definition: base.hh:621
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseCPU::CPUState
CPUState
Definition: base.hh:512
gem5::BaseCPU::BaseCPUStats::numCycles
statistics::Scalar numCycles
Definition: base.hh:597
gem5::BaseCPU::CPU_STATE_WAKEUP
@ CPU_STATE_WAKEUP
Definition: base.hh:516
statistics.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::BaseCPU::haltContext
virtual void haltContext(ThreadID thread_num)
Notify the CPU that the indicated context is now halted.
Definition: base.cc:528
gem5::BaseCPU::GlobalStats::hostInstRate
statistics::Formula hostInstRate
Definition: base.hh:159
gem5::BaseCPU::functionEntryTick
Tick functionEntryTick
Definition: base.hh:555
gem5::BaseCPU::instRequestorId
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
Definition: base.hh:196
gem5::BaseCPU::clearInterrupt
void clearInterrupt(ThreadID tid, int int_num, int index)
Definition: base.hh:244
port_proxy.hh
gem5::BaseCPU::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: base.cc:340
gem5::Trace::InstTracer
Definition: insttracer.hh:259
gem5::BaseCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:630
gem5::BaseCPU::CPU_STATE_ON
@ CPU_STATE_ON
Definition: base.hh:514
gem5::BaseCPU::previousState
CPUState previousState
Definition: base.hh:520
gem5::BaseCPU::_instRequestorId
RequestorID _instRequestorId
instruction side request id that must be placed in all requests
Definition: base.hh:129
gem5::BaseCPU
Definition: base.hh:107
gem5::BaseCPU::totalOps
virtual Counter totalOps() const =0
gem5::BaseCPU::findContext
int findContext(ThreadContext *tc)
Given a Thread Context pointer return the thread num.
Definition: base.cc:477
gem5::AddressMonitor::val
uint64_t val
Definition: base.hh:81
gem5::BaseCPU::numSimulatedInsts
static Counter numSimulatedInsts()
Definition: base.hh:570
gem5::BaseCPU::contextToThread
ThreadID contextToThread(ContextID cid)
Convert ContextID to threadID.
Definition: base.hh:298
gem5::BaseCPU::functionTracingEnabled
bool functionTracingEnabled
Definition: base.hh:551
gem5::BaseCPU::_socketId
const uint32_t _socketId
Each cpu will have a socket ID that corresponds to its physical location in the system.
Definition: base.hh:126
gem5::BaseCPU::~BaseCPU
virtual ~BaseCPU()
Definition: base.cc:189
gem5::BaseCPU::BaseCPUStats
Definition: base.hh:593
gem5::BaseCPU::getContext
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:290
gem5::BaseCPU::postInterrupt
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:194
gem5::BaseCPU::getCpuAddrMonitor
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:609
gem5::BaseCPU::enterPwrGatingEvent
EventFunctionWrapper enterPwrGatingEvent
Definition: base.hh:623
gem5::BaseCPU::probeInstCommit
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
Definition: base.cc:356
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::AddressMonitor::gotWakeup
bool gotWakeup
Definition: base.hh:83
gem5::BaseCPU::instCnt
Tick instCnt
Instruction count used for SPARC misc register.
Definition: base.hh:113
gem5::BaseCPU::GlobalStats::GlobalStats
GlobalStats(statistics::Group *parent)
Definition: base.cc:732
gem5::CPUProgressEvent::_repeatEvent
bool _repeatEvent
Definition: base.hh:92
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::BaseCPU::_switchedOut
bool _switchedOut
Is the CPU switched out or active?
Definition: base.hh:146
full_system.hh
gem5::BaseCPU::getTracer
Trace::InstTracer * getTracer()
Provide access to the tracer pointer.
Definition: base.hh:274
gem5::CPUProgressEvent::repeatEvent
void repeatEvent(bool repeat)
Definition: base.hh:102
gem5::BaseCPU::CPU_STATE_SLEEP
@ CPU_STATE_SLEEP
Definition: base.hh:515
gem5::ProbePointArg< bool >
gem5::BaseCPU::currentFunctionEnd
Addr currentFunctionEnd
Definition: base.hh:554
gem5::BaseCPU::workItemEnd
void workItemEnd()
Definition: base.hh:220
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::CPUProgressEvent::interval
void interval(Tick ival)
Definition: base.hh:99
gem5::BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:262
gem5::BaseCPU::takeOverFrom
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:554
gem5::BaseCPU::BaseCPUStats::numWorkItemsStarted
statistics::Scalar numWorkItemsStarted
Definition: base.hh:598
gem5::BaseCPU::activateContext
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:488
gem5::BaseCPU::traceFunctions
void traceFunctions(Addr pc)
Definition: base.hh:563
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::BaseCPU::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Definition: base.cc:410
gem5::BaseCPU::cpuId
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:188
gem5::BaseCPU::workItemBegin
void workItemBegin()
Definition: base.hh:219
clocked_object.hh
gem5::statistics::Value
Definition: statistics.hh:1979
interrupts.hh
gem5::BaseCPU::verifyMemoryMode
virtual void verifyMemoryMode() const
Verify that the system is in a memory mode supported by the CPU.
Definition: base.hh:368
gem5::BaseCPU::checkInterrupts
bool checkInterrupts(ThreadID tid) const
Definition: base.hh:256
gem5::BaseCPU::ppRetiredLoads
probing::PMUUPtr ppRetiredLoads
Retired load instructions.
Definition: base.hh:488
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseCPU::traceFunctionsInternal
void traceFunctionsInternal(Addr pc)
Definition: base.cc:703
gem5::BaseCPU::switchOut
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:540
gem5::BaseCPU::syscallRetryLatency
Cycles syscallRetryLatency
Definition: base.hh:615
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::BaseCPU::GlobalStats::simOps
statistics::Value simOps
Definition: base.hh:157
gem5::BaseCPU::getCurrentInstCount
uint64_t getCurrentInstCount(ThreadID tid)
Get the number of instructions executed by the specified thread on this CPU.
Definition: base.cc:677
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::AddressMonitor::pAddr
Addr pAddr
Definition: base.hh:80
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::BaseCPU::dataRequestorId
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
Definition: base.hh:194
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::AddressMonitor::waiting
bool waiting
Definition: base.hh:82
gem5::BaseCPU::mwait
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
gem5::BaseCPU::_cacheLineSize
const unsigned int _cacheLineSize
Cache the cache line size that we get from the system.
Definition: base.hh:149
gem5::BaseCPU::ppActiveCycles
probing::PMUUPtr ppActiveCycles
CPU cycle counter, only counts if any thread contexts is active.
Definition: base.hh:499
gem5::CPUProgressEvent::cpu
BaseCPU * cpu
Definition: base.hh:91
gem5::BaseCPU::numSimulatedCPUs
static int numSimulatedCPUs()
Definition: base.hh:569
probe.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::BaseCPU::ppRetiredBranches
probing::PMUUPtr ppRetiredBranches
Retired branches (any type)
Definition: base.hh:493
gem5::CPUProgressEvent
Definition: base.hh:86
gem5::BaseCPU::clearInterrupts
void clearInterrupts(ThreadID tid)
Definition: base.hh:250
gem5::BaseCPU::_pid
uint32_t _pid
The current OS process ID that is executing on this processor.
Definition: base.hh:143
gem5::AddressMonitor::armed
bool armed
Definition: base.hh:78
gem5::BaseCPU::powerGatingOnIdle
const bool powerGatingOnIdle
Definition: base.hh:622
gem5::BaseCPU::globalStats
static std::unique_ptr< GlobalStats > globalStats
Pointer to the global stat structure.
Definition: base.hh:167
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::BaseCPU::addressMonitor
std::vector< AddressMonitor > addressMonitor
Definition: base.hh:603
gem5::CPUProgressEvent::_interval
Tick _interval
Definition: base.hh:89
eventq.hh

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