42 #ifndef __CPU_BASE_HH__
43 #define __CPU_BASE_HH__
49 #include "debug/Mwait.hh"
265 static const uint32_t
invldPid = std::numeric_limits<uint32_t>::max();
305 void init()
override;
597 for (
int i = 0;
i < size; ++
i)
609 for (
int i = 0;
i < size; ++
i)
653 panic(
"htmSendAbortSignal not implemented");
void regStats() override
Callback to set stat parameters.
int findContext(ThreadContext *tc)
Given a Thread Context pointer return the thread num.
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
probing::PMUUPtr ppRetiredInsts
Instruction commit probe point.
const Cycles pwrGatingLatency
virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const
Serialize a single thread.
virtual Counter totalOps() const =0
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
Cycles syscallRetryLatency
uint32_t socketId() const
Reads this CPU's Socket ID.
void traceFunctionsInternal(Addr pc)
trace::InstTracer * tracer
const bool powerGatingOnIdle
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
void registerThreadContexts()
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
virtual void haltContext(ThreadID thread_num)
Notify the CPU that the indicated context is now halted.
probing::PMUUPtr ppRetiredLoads
Retired load instructions.
void clearInterrupts(ThreadID tid)
Tick instCnt
Instruction count used for SPARC misc register.
probing::PMUUPtr ppAllCycles
CPU cycle counter even if any thread Context is suspended.
probing::PMUUPtr ppRetiredInstsPC
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
void taskId(uint32_t id)
Set cpu task id.
probing::PMUUPtr pmuProbePoint(const char *name)
Helper method to instantiate probe points belonging to this object.
static const uint32_t invldPid
Invalid or unknown Pid.
void postInterrupt(ThreadID tid, int int_num, int index)
bool mwait(ThreadID tid, PacketPtr pkt)
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
const uint32_t _socketId
Each cpu will have a socket ID that corresponds to its physical location in the system.
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
virtual Port & getInstPort()=0
Purely virtual method that returns a reference to the instruction port.
void scheduleInstStopAnyThread(Counter max_insts)
Schedule an exit event when any threads in the core reach the max_insts instructions using the schedu...
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
probing::PMUUPtr ppRetiredStores
Retired store instructions.
bool _switchedOut
Is the CPU switched out or active?
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Addr currentFunctionStart
virtual Counter totalInsts() const =0
void schedulePowerGatingEvent()
static std::unique_ptr< GlobalStats > globalStats
Pointer to the global stat structure.
virtual void verifyMemoryMode() const
Verify that the system is in a memory mode supported by the CPU.
void regProbePoints() override
Register probe points for this object.
void scheduleSimpointsInstStop(std::vector< Counter > inst_starts)
Schedule simpoint events using the scheduleInstStop function.
uint32_t taskId() const
Get cpu task id.
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
static int numSimulatedCPUs()
void enableFunctionTrace()
unsigned numContexts()
Get the number of thread contexts available.
gem5::BaseCPU::BaseCPUStats baseStats
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
probing::PMUUPtr ppRetiredBranches
Retired branches (any type)
void deschedulePowerGatingEvent()
bool checkInterrupts(ThreadID tid) const
virtual void wakeup(ThreadID tid)=0
probing::PMUUPtr ppActiveCycles
CPU cycle counter, only counts if any thread contexts is active.
bool functionTracingEnabled
int cpuId() const
Reads this CPU's ID.
uint32_t _taskId
An intrenal representation of a task identifier within gem5.
void setPid(uint32_t pid)
std::vector< BaseInterrupts * > interrupts
void startup() override
startup() is the final initialization call before simulation.
virtual void unserializeThread(CheckpointIn &cp, ThreadID tid)
Unserialize one thread.
void traceFunctions(Addr pc)
virtual void switchOut()
Prepare for another CPU to take over execution.
void clearInterrupt(ThreadID tid, int int_num, int index)
void flushTLBs()
Flush all TLBs in the CPU.
ThreadID contextToThread(ContextID cid)
Convert ContextID to threadID.
void armMonitor(ThreadID tid, Addr address)
unsigned int cacheLineSize() const
Get the cache line size of the system.
ProbePointArg< bool > * ppSleeping
ProbePoint that signals transitions of threadContexts sets.
static Counter numSimulatedOps()
BaseInterrupts * getInterruptController(ThreadID tid)
std::ostream * functionTraceStream
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
std::vector< AddressMonitor > addressMonitor
std::vector< ThreadContext * > threadContexts
static std::vector< BaseCPU * > cpuList
Static global cpu list.
RequestorID _instRequestorId
instruction side request id that must be placed in all requests
EventFunctionWrapper enterPwrGatingEvent
void scheduleInstStop(ThreadID tid, Counter insts, std::string cause)
Schedule an event that exits the simulation loops after a predefined number of instructions.
bool switchedOut() const
Determine if the CPU is switched out.
BaseCPU(const Params ¶ms, bool is_checker=false)
uint32_t _pid
The current OS process ID that is executing on this processor.
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
uint64_t getCurrentInstCount(ThreadID tid)
Get the number of instructions executed by the specified thread on this CPU.
RequestorID _dataRequestorId
data side request id that must be placed in all requests
static Counter numSimulatedInsts()
const unsigned int _cacheLineSize
Cache the cache line size that we get from the system.
trace::InstTracer * getTracer()
Provide access to the tracer pointer.
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
virtual void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
CPUProgressEvent(BaseCPU *_cpu, Tick ival=0)
void repeatEvent(bool repeat)
virtual const char * description() const
Return a C string describing the event.
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ClockedObjectParams Params
Parameters of ClockedObject.
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Cycles is a wrapper class for representing cycle counts, i.e.
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Ports are used to interface objects to each other.
void notify(const Arg &arg)
called at the ProbePoint call site, passes arg to each listener.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
This is a simple scalar statistic, like a counter.
ClockedObject declaration and implementation.
#define panic(...)
This implements a cprintf based panic() function.
const Params & params() const
std::unique_ptr< PMU > PMUUPtr
const FlagsType total
Print the total.
double Counter
All counters are of 64-bit values.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
const PortID InvalidPortID
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
uint64_t Tick
Tick count type.
int ContextID
Globally unique thread context ID.
PortProxy Object Declaration.
Declaration of Statistics objects.
bool doMonitor(PacketPtr pkt)
statistics::Scalar numWorkItemsStarted
BaseCPUStats(statistics::Group *parent)
statistics::Scalar numCycles
statistics::Scalar numWorkItemsCompleted
Global CPU statistics that are merged into the Root object.
statistics::Formula hostInstRate
statistics::Value simInsts
GlobalStats(statistics::Group *parent)
statistics::Formula hostOpRate