gem5  v22.0.0.2
base.hh
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41 
42 #ifndef __CPU_BASE_HH__
43 #define __CPU_BASE_HH__
44 
45 #include <vector>
46 
47 // Before we do anything else, check if this build is the NULL ISA,
48 // and if so stop here
49 #include "config/the_isa.hh"
50 
51 #if IS_NULL_ISA
52 #error Including BaseCPU in a system without CPU support
53 #else
55 #include "base/statistics.hh"
56 #include "debug/Mwait.hh"
57 #include "mem/htm.hh"
58 #include "mem/port_proxy.hh"
59 #include "sim/clocked_object.hh"
60 #include "sim/eventq.hh"
61 #include "sim/full_system.hh"
62 #include "sim/insttracer.hh"
63 #include "sim/probe/pmu.hh"
64 #include "sim/probe/probe.hh"
65 #include "sim/system.hh"
66 
67 namespace gem5
68 {
69 
70 class BaseCPU;
71 struct BaseCPUParams;
72 class CheckerCPU;
73 class ThreadContext;
74 
75 struct AddressMonitor
76 {
77  AddressMonitor();
78  bool doMonitor(PacketPtr pkt);
79 
80  bool armed;
81  Addr vAddr;
82  Addr pAddr;
83  uint64_t val;
84  bool waiting; // 0=normal, 1=mwaiting
85  bool gotWakeup;
86 };
87 
88 class CPUProgressEvent : public Event
89 {
90  protected:
91  Tick _interval;
92  Counter lastNumInst;
93  BaseCPU *cpu;
94  bool _repeatEvent;
95 
96  public:
97  CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
98 
99  void process();
100 
101  void interval(Tick ival) { _interval = ival; }
102  Tick interval() { return _interval; }
103 
104  void repeatEvent(bool repeat) { _repeatEvent = repeat; }
105 
106  virtual const char *description() const;
107 };
108 
109 class BaseCPU : public ClockedObject
110 {
111  protected:
112 
115  Tick instCnt;
116 
117  // every cpu has an id, put it in the base cpu
118  // Set at initialization, only time a cpuId might change is during a
119  // takeover (which should be done from within the BaseCPU anyway,
120  // therefore no setCpuId() method is provided
121  int _cpuId;
122 
128  const uint32_t _socketId;
129 
131  RequestorID _instRequestorId;
132 
134  RequestorID _dataRequestorId;
135 
141  uint32_t _taskId;
142 
145  uint32_t _pid;
146 
148  bool _switchedOut;
149 
151  const unsigned int _cacheLineSize;
152 
154  struct GlobalStats : public statistics::Group
155  {
156  GlobalStats(statistics::Group *parent);
157 
158  statistics::Value simInsts;
159  statistics::Value simOps;
160 
161  statistics::Formula hostInstRate;
162  statistics::Formula hostOpRate;
163  };
164 
169  static std::unique_ptr<GlobalStats> globalStats;
170 
171  public:
172 
179  virtual Port &getDataPort() = 0;
180 
187  virtual Port &getInstPort() = 0;
188 
190  int cpuId() const { return _cpuId; }
191 
193  uint32_t socketId() const { return _socketId; }
194 
196  RequestorID dataRequestorId() const { return _dataRequestorId; }
198  RequestorID instRequestorId() const { return _instRequestorId; }
199 
210  Port &getPort(const std::string &if_name,
211  PortID idx=InvalidPortID) override;
212 
214  uint32_t taskId() const { return _taskId; }
216  void taskId(uint32_t id) { _taskId = id; }
217 
218  uint32_t getPid() const { return _pid; }
219  void setPid(uint32_t pid) { _pid = pid; }
220 
221  inline void workItemBegin() { baseStats.numWorkItemsStarted++; }
222  inline void workItemEnd() { baseStats.numWorkItemsCompleted++; }
223  // @todo remove me after debugging with legion done
224  Tick instCount() { return instCnt; }
225 
226  protected:
227  std::vector<BaseInterrupts*> interrupts;
228 
229  public:
230  BaseInterrupts *
231  getInterruptController(ThreadID tid)
232  {
233  if (interrupts.empty())
234  return NULL;
235 
236  assert(interrupts.size() > tid);
237  return interrupts[tid];
238  }
239 
240  virtual void wakeup(ThreadID tid) = 0;
241 
242  void postInterrupt(ThreadID tid, int int_num, int index);
243 
244  void
245  clearInterrupt(ThreadID tid, int int_num, int index)
246  {
247  interrupts[tid]->clear(int_num, index);
248  }
249 
250  void
251  clearInterrupts(ThreadID tid)
252  {
253  interrupts[tid]->clearAll();
254  }
255 
256  bool
257  checkInterrupts(ThreadID tid) const
258  {
259  return FullSystem && interrupts[tid]->checkInterrupts();
260  }
261 
262  protected:
263  std::vector<ThreadContext *> threadContexts;
264 
265  Trace::InstTracer * tracer;
266 
267  public:
268 
269 
272  static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
273 
275  Trace::InstTracer * getTracer() { return tracer; }
276 
278  virtual void activateContext(ThreadID thread_num);
279 
282  virtual void suspendContext(ThreadID thread_num);
283 
285  virtual void haltContext(ThreadID thread_num);
286 
288  int findContext(ThreadContext *tc);
289 
291  virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
292 
294  unsigned
295  numContexts()
296  {
297  return static_cast<unsigned>(threadContexts.size());
298  }
299 
301  ThreadID
302  contextToThread(ContextID cid)
303  {
304  return static_cast<ThreadID>(cid - threadContexts[0]->contextId());
305  }
306 
307  public:
308  PARAMS(BaseCPU);
309  BaseCPU(const Params &params, bool is_checker = false);
310  virtual ~BaseCPU();
311 
312  void init() override;
313  void startup() override;
314  void regStats() override;
315 
316  void regProbePoints() override;
317 
318  void registerThreadContexts();
319 
320  // Functions to deschedule and reschedule the events to enter the
321  // power gating sleep before and after checkpoiting respectively.
322  void deschedulePowerGatingEvent();
323  void schedulePowerGatingEvent();
324 
332  virtual void switchOut();
333 
345  virtual void takeOverFrom(BaseCPU *cpu);
346 
356  void flushTLBs();
357 
363  bool switchedOut() const { return _switchedOut; }
364 
374  virtual void verifyMemoryMode() const { };
375 
380  ThreadID numThreads;
381 
382  System *system;
383 
387  inline unsigned int cacheLineSize() const { return _cacheLineSize; }
388 
399  void serialize(CheckpointOut &cp) const override;
400 
411  void unserialize(CheckpointIn &cp) override;
412 
419  virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
420 
427  virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
428 
429  virtual Counter totalInsts() const = 0;
430 
431  virtual Counter totalOps() const = 0;
432 
446  void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
447 
455  uint64_t getCurrentInstCount(ThreadID tid);
456 
457  public:
470  virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
471 
472  protected:
480  probing::PMUUPtr pmuProbePoint(const char *name);
481 
490  probing::PMUUPtr ppRetiredInsts;
491  probing::PMUUPtr ppRetiredInstsPC;
492 
494  probing::PMUUPtr ppRetiredLoads;
496  probing::PMUUPtr ppRetiredStores;
497 
499  probing::PMUUPtr ppRetiredBranches;
500 
502  probing::PMUUPtr ppAllCycles;
503 
505  probing::PMUUPtr ppActiveCycles;
506 
515  ProbePointArg<bool> *ppSleeping;
518  enum CPUState
519  {
520  CPU_STATE_ON,
521  CPU_STATE_SLEEP,
522  CPU_STATE_WAKEUP
523  };
524 
525  Cycles previousCycle;
526  CPUState previousState;
527 
529  inline void
530  updateCycleCounters(CPUState state)
531  {
532  uint32_t delta = curCycle() - previousCycle;
533 
534  if (previousState == CPU_STATE_ON) {
535  ppActiveCycles->notify(delta);
536  }
537 
538  switch (state) {
539  case CPU_STATE_WAKEUP:
540  ppSleeping->notify(false);
541  break;
542  case CPU_STATE_SLEEP:
543  ppSleeping->notify(true);
544  break;
545  default:
546  break;
547  }
548 
549  ppAllCycles->notify(delta);
550 
551  previousCycle = curCycle();
552  previousState = state;
553  }
554 
555  // Function tracing
556  private:
557  bool functionTracingEnabled;
558  std::ostream *functionTraceStream;
559  Addr currentFunctionStart;
560  Addr currentFunctionEnd;
561  Tick functionEntryTick;
562  void enableFunctionTrace();
563  void traceFunctionsInternal(Addr pc);
564 
565  private:
566  static std::vector<BaseCPU *> cpuList;
567 
568  public:
569  void
570  traceFunctions(Addr pc)
571  {
572  if (functionTracingEnabled)
573  traceFunctionsInternal(pc);
574  }
575 
576  static int numSimulatedCPUs() { return cpuList.size(); }
577  static Counter
578  numSimulatedInsts()
579  {
580  Counter total = 0;
581 
582  int size = cpuList.size();
583  for (int i = 0; i < size; ++i)
584  total += cpuList[i]->totalInsts();
585 
586  return total;
587  }
588 
589  static Counter
590  numSimulatedOps()
591  {
592  Counter total = 0;
593 
594  int size = cpuList.size();
595  for (int i = 0; i < size; ++i)
596  total += cpuList[i]->totalOps();
597 
598  return total;
599  }
600 
601  public:
602  struct BaseCPUStats : public statistics::Group
603  {
604  BaseCPUStats(statistics::Group *parent);
605  // Number of CPU cycles simulated
606  statistics::Scalar numCycles;
607  statistics::Scalar numWorkItemsStarted;
608  statistics::Scalar numWorkItemsCompleted;
609  } baseStats;
610 
611  private:
612  std::vector<AddressMonitor> addressMonitor;
613 
614  public:
615  void armMonitor(ThreadID tid, Addr address);
616  bool mwait(ThreadID tid, PacketPtr pkt);
617  void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
618  AddressMonitor *
619  getCpuAddrMonitor(ThreadID tid)
620  {
621  assert(tid < numThreads);
622  return &addressMonitor[tid];
623  }
624 
625  Cycles syscallRetryLatency;
626 
635  virtual void
636  htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
637  HtmFailureFaultCause cause)
638  {
639  panic("htmSendAbortSignal not implemented");
640  }
641 
642  // Enables CPU to enter power gating on a configurable cycle count
643  protected:
644  void enterPwrGating();
645 
646  const Cycles pwrGatingLatency;
647  const bool powerGatingOnIdle;
648  EventFunctionWrapper enterPwrGatingEvent;
649 };
650 
651 } // namespace gem5
652 
653 #endif // !IS_NULL_ISA
654 
655 #endif // __CPU_BASE_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:264
gem5::Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:53
system.hh
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
insttracer.hh
htm.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
std::vector
STL vector class.
Definition: stl.hh:37
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:312
gem5::PacketPtr
Packet * PacketPtr
Definition: thread_context.hh:76
pmu.hh
gem5::StaticInstPtr
RefCountingPtr< StaticInst > StaticInstPtr
Definition: static_inst_fwd.hh:37
gem5::probing::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
statistics.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
port_proxy.hh
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:215
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
full_system.hh
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
state
atomic_var_t state
Definition: helpers.cc:188
clocked_object.hh
interrupts.hh
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
PARAMS
#define PARAMS(type)
Definition: sim_object.hh:371
probe.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
eventq.hh

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