gem5  v22.1.0.0
base.hh
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41 
42 #ifndef __CPU_BASE_HH__
43 #define __CPU_BASE_HH__
44 
45 #include <vector>
46 
48 #include "base/statistics.hh"
49 #include "debug/Mwait.hh"
50 #include "mem/htm.hh"
51 #include "mem/port_proxy.hh"
52 #include "sim/clocked_object.hh"
53 #include "sim/eventq.hh"
54 #include "sim/full_system.hh"
55 #include "sim/insttracer.hh"
56 #include "sim/probe/pmu.hh"
57 #include "sim/probe/probe.hh"
58 #include "sim/system.hh"
59 
60 namespace gem5
61 {
62 
63 class BaseCPU;
64 struct BaseCPUParams;
65 class CheckerCPU;
66 class ThreadContext;
67 
69 {
71  bool doMonitor(PacketPtr pkt);
72 
73  bool armed;
76  uint64_t val;
77  bool waiting; // 0=normal, 1=mwaiting
78  bool gotWakeup;
79 };
80 
81 class CPUProgressEvent : public Event
82 {
83  protected:
88 
89  public:
90  CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
91 
92  void process();
93 
94  void interval(Tick ival) { _interval = ival; }
95  Tick interval() { return _interval; }
96 
97  void repeatEvent(bool repeat) { _repeatEvent = repeat; }
98 
99  virtual const char *description() const;
100 };
101 
102 class BaseCPU : public ClockedObject
103 {
104  protected:
105 
109 
110  // every cpu has an id, put it in the base cpu
111  // Set at initialization, only time a cpuId might change is during a
112  // takeover (which should be done from within the BaseCPU anyway,
113  // therefore no setCpuId() method is provided
114  int _cpuId;
115 
121  const uint32_t _socketId;
122 
125 
128 
134  uint32_t _taskId;
135 
138  uint32_t _pid;
139 
142 
144  const unsigned int _cacheLineSize;
145 
148  {
150 
153 
156  };
157 
162  static std::unique_ptr<GlobalStats> globalStats;
163 
164  public:
165 
172  virtual Port &getDataPort() = 0;
173 
180  virtual Port &getInstPort() = 0;
181 
183  int cpuId() const { return _cpuId; }
184 
186  uint32_t socketId() const { return _socketId; }
187 
192 
203  Port &getPort(const std::string &if_name,
204  PortID idx=InvalidPortID) override;
205 
207  uint32_t taskId() const { return _taskId; }
209  void taskId(uint32_t id) { _taskId = id; }
210 
211  uint32_t getPid() const { return _pid; }
212  void setPid(uint32_t pid) { _pid = pid; }
213 
216  // @todo remove me after debugging with legion done
217  Tick instCount() { return instCnt; }
218 
219  protected:
221 
222  public:
225  {
226  if (interrupts.empty())
227  return NULL;
228 
229  assert(interrupts.size() > tid);
230  return interrupts[tid];
231  }
232 
233  virtual void wakeup(ThreadID tid) = 0;
234 
235  void postInterrupt(ThreadID tid, int int_num, int index);
236 
237  void
238  clearInterrupt(ThreadID tid, int int_num, int index)
239  {
240  interrupts[tid]->clear(int_num, index);
241  }
242 
243  void
245  {
246  interrupts[tid]->clearAll();
247  }
248 
249  bool
251  {
252  return FullSystem && interrupts[tid]->checkInterrupts();
253  }
254 
255  protected:
257 
259 
260  public:
261 
262 
265  static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
266 
269 
271  virtual void activateContext(ThreadID thread_num);
272 
275  virtual void suspendContext(ThreadID thread_num);
276 
278  virtual void haltContext(ThreadID thread_num);
279 
281  int findContext(ThreadContext *tc);
282 
284  virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
285 
287  unsigned
289  {
290  return static_cast<unsigned>(threadContexts.size());
291  }
292 
294  ThreadID
296  {
297  return static_cast<ThreadID>(cid - threadContexts[0]->contextId());
298  }
299 
300  public:
302  BaseCPU(const Params &params, bool is_checker = false);
303  virtual ~BaseCPU();
304 
305  void init() override;
306  void startup() override;
307  void regStats() override;
308 
309  void regProbePoints() override;
310 
311  void registerThreadContexts();
312 
313  // Functions to deschedule and reschedule the events to enter the
314  // power gating sleep before and after checkpoiting respectively.
317 
325  virtual void switchOut();
326 
338  virtual void takeOverFrom(BaseCPU *cpu);
339 
349  void flushTLBs();
350 
356  bool switchedOut() const { return _switchedOut; }
357 
367  virtual void verifyMemoryMode() const { };
368 
374 
376 
380  inline unsigned int cacheLineSize() const { return _cacheLineSize; }
381 
392  void serialize(CheckpointOut &cp) const override;
393 
404  void unserialize(CheckpointIn &cp) override;
405 
412  virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
413 
420  virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
421 
422  virtual Counter totalInsts() const = 0;
423 
424  virtual Counter totalOps() const = 0;
425 
439  void scheduleInstStop(ThreadID tid, Counter insts, std::string cause);
440 
451 
460  void scheduleInstStopAnyThread(Counter max_insts);
461 
469  uint64_t getCurrentInstCount(ThreadID tid);
470 
471  public:
484  virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
485 
486  protected:
494  probing::PMUUPtr pmuProbePoint(const char *name);
495 
506 
511 
514 
517 
520 
532  enum CPUState
533  {
537  };
538 
541 
543  inline void
545  {
546  uint32_t delta = curCycle() - previousCycle;
547 
548  if (previousState == CPU_STATE_ON) {
549  ppActiveCycles->notify(delta);
550  }
551 
552  switch (state) {
553  case CPU_STATE_WAKEUP:
554  ppSleeping->notify(false);
555  break;
556  case CPU_STATE_SLEEP:
557  ppSleeping->notify(true);
558  break;
559  default:
560  break;
561  }
562 
563  ppAllCycles->notify(delta);
564 
567  }
568 
569  // Function tracing
570  private:
572  std::ostream *functionTraceStream;
576  void enableFunctionTrace();
578 
579  private:
581 
582  public:
583  void
585  {
588  }
589 
590  static int numSimulatedCPUs() { return cpuList.size(); }
591  static Counter
593  {
594  Counter total = 0;
595 
596  int size = cpuList.size();
597  for (int i = 0; i < size; ++i)
598  total += cpuList[i]->totalInsts();
599 
600  return total;
601  }
602 
603  static Counter
605  {
606  Counter total = 0;
607 
608  int size = cpuList.size();
609  for (int i = 0; i < size; ++i)
610  total += cpuList[i]->totalOps();
611 
612  return total;
613  }
614 
615  public:
617  {
619  // Number of CPU cycles simulated
624 
625  private:
627 
628  public:
629  void armMonitor(ThreadID tid, Addr address);
630  bool mwait(ThreadID tid, PacketPtr pkt);
631  void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
634  {
635  assert(tid < numThreads);
636  return &addressMonitor[tid];
637  }
638 
640 
649  virtual void
650  htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
651  HtmFailureFaultCause cause)
652  {
653  panic("htmSendAbortSignal not implemented");
654  }
655 
656  // Enables CPU to enter power gating on a configurable cycle count
657  protected:
658  void enterPwrGating();
659 
661  const bool powerGatingOnIdle;
663 };
664 
665 } // namespace gem5
666 
667 #endif // __CPU_BASE_HH__
void regStats() override
Callback to set stat parameters.
Definition: base.cc:383
int findContext(ThreadContext *tc)
Given a Thread Context pointer return the thread num.
Definition: base.cc:469
RequestorID dataRequestorId() const
Reads this CPU's unique data requestor ID.
Definition: base.hh:189
probing::PMUUPtr ppRetiredInsts
Instruction commit probe point.
Definition: base.hh:504
const Cycles pwrGatingLatency
Definition: base.hh:660
virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const
Serialize a single thread.
Definition: base.hh:412
virtual Counter totalOps() const =0
RequestorID instRequestorId() const
Reads this CPU's unique instruction requestor ID.
Definition: base.hh:191
Cycles syscallRetryLatency
Definition: base.hh:639
Tick functionEntryTick
Definition: base.hh:575
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:186
void traceFunctionsInternal(Addr pc)
Definition: base.cc:698
trace::InstTracer * tracer
Definition: base.hh:258
const bool powerGatingOnIdle
Definition: base.hh:661
AddressMonitor * getCpuAddrMonitor(ThreadID tid)
Definition: base.hh:633
void registerThreadContexts()
Definition: base.cc:421
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
virtual void haltContext(ThreadID thread_num)
Notify the CPU that the indicated context is now halted.
Definition: base.cc:520
probing::PMUUPtr ppRetiredLoads
Retired load instructions.
Definition: base.hh:508
void clearInterrupts(ThreadID tid)
Definition: base.hh:244
Tick instCnt
Instruction count used for SPARC misc register.
Definition: base.hh:108
Addr currentFunctionEnd
Definition: base.hh:574
int _cpuId
Definition: base.hh:114
probing::PMUUPtr ppAllCycles
CPU cycle counter even if any thread Context is suspended.
Definition: base.hh:516
probing::PMUUPtr ppRetiredInstsPC
Definition: base.hh:505
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:273
uint32_t getPid() const
Definition: base.hh:211
System * system
Definition: base.hh:375
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
Definition: base.cc:240
Cycles previousCycle
Definition: base.hh:539
void enterPwrGating()
Definition: base.cc:526
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:544
void taskId(uint32_t id)
Set cpu task id.
Definition: base.hh:209
probing::PMUUPtr pmuProbePoint(const char *name)
Helper method to instantiate probe points belonging to this object.
Definition: base.cc:328
static const uint32_t invldPid
Invalid or unknown Pid.
Definition: base.hh:265
void postInterrupt(ThreadID tid, int int_num, int index)
Definition: base.cc:194
bool mwait(ThreadID tid, PacketPtr pkt)
Definition: base.cc:217
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
Definition: base.hh:284
const uint32_t _socketId
Each cpu will have a socket ID that corresponds to its physical location in the system.
Definition: base.hh:121
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: base.cc:643
void workItemBegin()
Definition: base.hh:214
virtual Port & getInstPort()=0
Purely virtual method that returns a reference to the instruction port.
void scheduleInstStopAnyThread(Counter max_insts)
Schedule an exit event when any threads in the core reach the max_insts instructions using the schedu...
Definition: base.cc:736
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: base.cc:622
probing::PMUUPtr ppRetiredStores
Retired store instructions.
Definition: base.hh:510
bool _switchedOut
Is the CPU switched out or active?
Definition: base.hh:141
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Definition: base.cc:407
Addr currentFunctionStart
Definition: base.hh:573
virtual Counter totalInsts() const =0
void schedulePowerGatingEvent()
Definition: base.cc:452
@ CPU_STATE_ON
Definition: base.hh:534
@ CPU_STATE_SLEEP
Definition: base.hh:535
@ CPU_STATE_WAKEUP
Definition: base.hh:536
static std::unique_ptr< GlobalStats > globalStats
Pointer to the global stat structure.
Definition: base.hh:162
virtual void verifyMemoryMode() const
Verify that the system is in a memory mode supported by the CPU.
Definition: base.hh:367
void regProbePoints() override
Register probe points for this object.
Definition: base.cc:337
void scheduleSimpointsInstStop(std::vector< Counter > inst_starts)
Schedule simpoint events using the scheduleInstStop function.
Definition: base.cc:727
uint32_t taskId() const
Get cpu task id.
Definition: base.hh:207
virtual void suspendContext(ThreadID thread_num)
Notify the CPU that the indicated context is now suspended.
Definition: base.cc:494
static int numSimulatedCPUs()
Definition: base.hh:590
void enableFunctionTrace()
Definition: base.cc:184
unsigned numContexts()
Get the number of thread contexts available.
Definition: base.hh:288
gem5::BaseCPU::BaseCPUStats baseStats
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:367
probing::PMUUPtr ppRetiredBranches
Retired branches (any type)
Definition: base.hh:513
void deschedulePowerGatingEvent()
Definition: base.cc:444
Tick instCount()
Definition: base.hh:217
bool checkInterrupts(ThreadID tid) const
Definition: base.hh:250
CPUState previousState
Definition: base.hh:540
virtual void wakeup(ThreadID tid)=0
probing::PMUUPtr ppActiveCycles
CPU cycle counter, only counts if any thread contexts is active.
Definition: base.hh:519
bool functionTracingEnabled
Definition: base.hh:571
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:183
uint32_t _taskId
An intrenal representation of a task identifier within gem5.
Definition: base.hh:134
void setPid(uint32_t pid)
Definition: base.hh:212
std::vector< BaseInterrupts * > interrupts
Definition: base.hh:220
void startup() override
startup() is the final initialization call before simulation.
Definition: base.cc:312
virtual void unserializeThread(CheckpointIn &cp, ThreadID tid)
Unserialize one thread.
Definition: base.hh:420
void traceFunctions(Addr pc)
Definition: base.hh:584
virtual ~BaseCPU()
Definition: base.cc:189
virtual void switchOut()
Prepare for another CPU to take over execution.
Definition: base.cc:532
void clearInterrupt(ThreadID tid, int int_num, int index)
Definition: base.hh:238
void flushTLBs()
Flush all TLBs in the CPU.
Definition: base.cc:608
ThreadID contextToThread(ContextID cid)
Convert ContextID to threadID.
Definition: base.hh:295
void armMonitor(ThreadID tid, Addr address)
Definition: base.cc:205
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: base.hh:380
ProbePointArg< bool > * ppSleeping
ProbePoint that signals transitions of threadContexts sets.
Definition: base.hh:529
static Counter numSimulatedOps()
Definition: base.hh:604
BaseInterrupts * getInterruptController(ThreadID tid)
Definition: base.hh:224
PARAMS(BaseCPU)
std::ostream * functionTraceStream
Definition: base.hh:572
virtual void takeOverFrom(BaseCPU *cpu)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: base.cc:546
std::vector< AddressMonitor > addressMonitor
Definition: base.hh:626
std::vector< ThreadContext * > threadContexts
Definition: base.hh:256
static std::vector< BaseCPU * > cpuList
Static global cpu list.
Definition: base.hh:580
RequestorID _instRequestorId
instruction side request id that must be placed in all requests
Definition: base.hh:124
EventFunctionWrapper enterPwrGatingEvent
Definition: base.hh:662
void scheduleInstStop(ThreadID tid, Counter insts, std::string cause)
Schedule an event that exits the simulation loops after a predefined number of instructions.
Definition: base.cc:660
bool switchedOut() const
Determine if the CPU is switched out.
Definition: base.hh:356
BaseCPU(const Params &params, bool is_checker=false)
Definition: base.cc:127
void workItemEnd()
Definition: base.hh:215
uint32_t _pid
The current OS process ID that is executing on this processor.
Definition: base.hh:138
virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc)
Helper method to trigger PMU probes for a committed instruction.
Definition: base.cc:353
uint64_t getCurrentInstCount(ThreadID tid)
Get the number of instructions executed by the specified thread on this CPU.
Definition: base.cc:669
RequestorID _dataRequestorId
data side request id that must be placed in all requests
Definition: base.hh:127
static Counter numSimulatedInsts()
Definition: base.hh:592
const unsigned int _cacheLineSize
Cache the cache line size that we get from the system.
Definition: base.hh:144
trace::InstTracer * getTracer()
Provide access to the tracer pointer.
Definition: base.hh:268
virtual void activateContext(ThreadID thread_num)
Notify the CPU that the indicated context is now active.
Definition: base.cc:480
virtual void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
Definition: base.hh:650
CPUProgressEvent(BaseCPU *_cpu, Tick ival=0)
Definition: base.cc:86
Counter lastNumInst
Definition: base.hh:85
BaseCPU * cpu
Definition: base.hh:86
void repeatEvent(bool repeat)
Definition: base.hh:97
virtual const char * description() const
Return a C string describing the event.
Definition: base.cc:122
void interval(Tick ival)
Definition: base.hh:94
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
ClockedObjectParams Params
Parameters of ClockedObject.
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:79
virtual std::string name() const
Definition: named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
Ports are used to interface objects to each other.
Definition: port.hh:62
void notify(const Arg &arg)
called at the ProbePoint call site, passes arg to each listener.
Definition: probe.hh:313
ThreadContext is the external interface to all thread state for anything outside of the CPU.
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2540
Statistics container.
Definition: group.hh:94
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1931
STL vector class.
Definition: stl.hh:37
ClockedObject declaration and implementation.
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
const Params & params() const
Definition: sim_object.hh:176
atomic_var_t state
Definition: helpers.cc:188
Bitfield< 7 > i
Definition: misc_types.hh:67
Bitfield< 33 > id
Definition: misc_types.hh:257
Bitfield< 4 > pc
Bitfield< 30, 0 > index
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:61
const FlagsType total
Print the total.
Definition: info.hh:60
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
const PortID InvalidPortID
Definition: types.hh:246
std::ostream CheckpointOut
Definition: serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
uint64_t Tick
Tick count type.
Definition: types.hh:58
uint16_t RequestorID
Definition: request.hh:95
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
HtmFailureFaultCause
Definition: htm.hh:48
PortProxy Object Declaration.
Declaration of Statistics objects.
bool doMonitor(PacketPtr pkt)
Definition: base.cc:682
uint64_t val
Definition: base.hh:76
statistics::Scalar numWorkItemsStarted
Definition: base.hh:621
BaseCPUStats(statistics::Group *parent)
Definition: base.cc:371
statistics::Scalar numCycles
Definition: base.hh:620
statistics::Scalar numWorkItemsCompleted
Definition: base.hh:622
Global CPU statistics that are merged into the Root object.
Definition: base.hh:148
statistics::Value simOps
Definition: base.hh:152
statistics::Formula hostInstRate
Definition: base.hh:154
statistics::Value simInsts
Definition: base.hh:151
GlobalStats(statistics::Group *parent)
Definition: base.cc:744
statistics::Formula hostOpRate
Definition: base.hh:155

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