gem5 v24.0.0.0
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This device implements the niagara I/O Bridge chip. More...
Go to the source code of this file.
Classes | |
class | gem5::Iob |
struct | gem5::Iob::IntMan |
struct | gem5::Iob::IntCtl |
struct | gem5::Iob::IntBusy |
Namespaces | |
namespace | gem5 |
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved. | |
Variables | |
const int | gem5::MaxNiagaraProcs = 32 |
const Addr | gem5::IntManAddr = 0x0000 |
const Addr | gem5::IntManSize = 0x0020 |
const Addr | gem5::IntCtlAddr = 0x0400 |
const Addr | gem5::IntCtlSize = 0x0020 |
const Addr | gem5::JIntVecAddr = 0x0A00 |
const Addr | gem5::IntVecDisAddr = 0x0800 |
const Addr | gem5::IntVecDisSize = 0x0100 |
const Addr | gem5::JIntData0Addr = 0x0400 |
const Addr | gem5::JIntData1Addr = 0x0500 |
const Addr | gem5::JIntDataA0Addr = 0x0600 |
const Addr | gem5::JIntDataA1Addr = 0x0700 |
const Addr | gem5::JIntBusyAddr = 0x0900 |
const Addr | gem5::JIntBusySize = 0x0100 |
const Addr | gem5::JIntABusyAddr = 0x0B00 |
const uint64_t | gem5::IntManMask = 0x01F3F |
const uint64_t | gem5::IntCtlMask = 0x00006 |
const uint64_t | gem5::JIntVecMask = 0x0003F |
const uint64_t | gem5::IntVecDis = 0x31F3F |
const uint64_t | gem5::JIntBusyMask = 0x0003F |
This device implements the niagara I/O Bridge chip.
The device manages internal (ipi) and external (serial, pci via jbus).
Definition in file iob.hh.