gem5  v21.1.0.2
kfd_ioctl.h
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1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #ifndef KFD_IOCTL_H_INCLUDED
24 #define KFD_IOCTL_H_INCLUDED
25 
26 #include <cstdint>
27 #include <drm/drm.h>
28 #include <linux/ioctl.h>
29 #include <linux/types.h>
30 
31 namespace gem5
32 {
33 
34 /*
35  * - 1.1 - initial version
36  * - 1.3 - Add SMI events support
37  */
38 #define KFD_IOCTL_MAJOR_VERSION 1
39 #define KFD_IOCTL_MINOR_VERSION 3
40 
42 {
43  uint32_t major_version; /* from KFD */
44  uint32_t minor_version; /* from KFD */
45 };
46 
47 /* For kfd_ioctl_create_queue_args.queue_type. */
48 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0
49 #define KFD_IOC_QUEUE_TYPE_SDMA 1
50 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
51 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 3
52 
53 #define KFD_MAX_QUEUE_PERCENTAGE 100
54 #define KFD_MAX_QUEUE_PRIORITY 15
55 
57 {
58  uint64_t ring_base_address; /* to KFD */
59  uint64_t write_pointer_address; /* from KFD */
60  uint64_t read_pointer_address; /* from KFD */
61  uint64_t doorbell_offset; /* from KFD */
62 
63  uint32_t ring_size; /* to KFD */
64  uint32_t gpu_id; /* to KFD */
65  uint32_t queue_type; /* to KFD */
66  uint32_t queue_percentage; /* to KFD */
67  uint32_t queue_priority; /* to KFD */
68  uint32_t queue_id; /* from KFD */
69 
70  uint64_t eop_buffer_address; /* to KFD */
71  uint64_t eop_buffer_size; /* to KFD */
72  uint64_t ctx_save_restore_address; /* to KFD */
73  uint32_t ctx_save_restore_size; /* to KFD */
74  uint32_t ctl_stack_size; /* to KFD */
75 };
76 
78 {
79  uint32_t queue_id; /* to KFD */
80  uint32_t pad;
81 };
82 
84 {
85  uint64_t ring_base_address; /* to KFD */
86 
87  uint32_t queue_id; /* to KFD */
88  uint32_t ring_size; /* to KFD */
89  uint32_t queue_percentage; /* to KFD */
90  uint32_t queue_priority; /* to KFD */
91 };
92 
94 {
95  uint32_t queue_id; /* to KFD */
96  uint32_t num_cu_mask; /* to KFD */
97  uint64_t cu_mask_ptr; /* to KFD */
98 };
99 
101 {
102  uint64_t ctl_stack_address; /* to KFD */
103  uint32_t ctl_stack_used_size; /* from KFD */
104  uint32_t save_area_used_size; /* from KFD */
105  uint32_t queue_id; /* to KFD */
106  uint32_t pad;
107 };
108 
109 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
110 #define KFD_IOC_CACHE_POLICY_COHERENT 0
111 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
112 
114 {
115  uint64_t alternate_aperture_base; /* to KFD */
116  uint64_t alternate_aperture_size; /* to KFD */
117 
118  uint32_t gpu_id; /* to KFD */
119  uint32_t default_policy; /* to KFD */
120  uint32_t alternate_policy; /* to KFD */
121  uint32_t pad;
122 };
123 
124 /*
125  * All counters are monotonic. They are used for profiling of compute jobs.
126  * The profiling is done by userspace.
127  *
128  * In case of GPU reset, the counter should not be affected.
129  */
130 
132 {
133  uint64_t gpu_clock_counter; /* from KFD */
134  uint64_t cpu_clock_counter; /* from KFD */
135  uint64_t system_clock_counter; /* from KFD */
136  uint64_t system_clock_freq; /* from KFD */
137 
138  uint32_t gpu_id; /* to KFD */
139  uint32_t pad;
140 };
141 
143 {
144  uint64_t lds_base; /* from KFD */
145  uint64_t lds_limit; /* from KFD */
146  uint64_t scratch_base; /* from KFD */
147  uint64_t scratch_limit; /* from KFD */
148  uint64_t gpuvm_base; /* from KFD */
149  uint64_t gpuvm_limit; /* from KFD */
150  uint32_t gpu_id; /* from KFD */
151  uint32_t pad;
152 };
153 
154 /*
155  * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
156  * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
157  * unlimited number of GPUs.
158  */
159 #define NUM_OF_SUPPORTED_GPUS 7
161 {
164 
165  /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
166  uint32_t num_of_nodes;
167  uint32_t pad;
168 };
169 
171 {
172  /* User allocated. Pointer to struct kfd_process_device_apertures
173  * filled in by Kernel
174  */
176  /* to KFD - indicates amount of memory present in
177  * kfd_process_device_apertures_ptr
178  * from KFD - Number of entries filled by KFD.
179  */
180  uint32_t num_of_nodes;
181  uint32_t pad;
182 };
183 
184 #define MAX_ALLOWED_NUM_POINTS 100
185 #define MAX_ALLOWED_AW_BUFF_SIZE 4096
186 #define MAX_ALLOWED_WAC_BUFF_SIZE 128
187 
189 {
190  uint32_t gpu_id; /* to KFD */
191  uint32_t pad;
192 };
193 
195 {
196  uint32_t gpu_id; /* to KFD */
197  uint32_t pad;
198 };
199 
201 {
202  uint64_t content_ptr; /* a pointer to the actual content */
203  uint32_t gpu_id; /* to KFD */
204  uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
205 };
206 
208 {
209  uint64_t content_ptr; /* a pointer to the actual content */
210  uint32_t gpu_id; /* to KFD */
211  uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
212 };
213 
214 /* Matching HSA_EVENTTYPE */
215 #define KFD_IOC_EVENT_SIGNAL 0
216 #define KFD_IOC_EVENT_NODECHANGE 1
217 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2
218 #define KFD_IOC_EVENT_HW_EXCEPTION 3
219 #define KFD_IOC_EVENT_SYSTEM_EVENT 4
220 #define KFD_IOC_EVENT_DEBUG_EVENT 5
221 #define KFD_IOC_EVENT_PROFILE_EVENT 6
222 #define KFD_IOC_EVENT_QUEUE_EVENT 7
223 #define KFD_IOC_EVENT_MEMORY 8
224 
225 #define KFD_IOC_WAIT_RESULT_COMPLETE 0
226 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1
227 #define KFD_IOC_WAIT_RESULT_FAIL 2
228 
229 #define KFD_SIGNAL_EVENT_LIMIT 4096
230 
231 /* For kfd_event_data.hw_exception_data.reset_type. */
232 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
233 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
234 
235 /* For kfd_event_data.hw_exception_data.reset_cause. */
236 #define KFD_HW_EXCEPTION_GPU_HANG 0
237 #define KFD_HW_EXCEPTION_ECC 1
238 
239 /* For kfd_hsa_memory_exception_data.ErrorType */
240 #define KFD_MEM_ERR_NO_RAS 0
241 #define KFD_MEM_ERR_SRAM_ECC 1
242 #define KFD_MEM_ERR_POISON_CONSUMED 2
243 #define KFD_MEM_ERR_GPU_HANG 3
244 
246 {
247  uint64_t event_page_offset; /* from KFD */
248  uint32_t event_trigger_data; /* from KFD - signal events only */
249  uint32_t event_type; /* to KFD */
250  uint32_t auto_reset; /* to KFD */
251  uint32_t node_id; /* to KFD - only valid for certain
252  event types */
253  uint32_t event_id; /* from KFD */
254  uint32_t event_slot_index; /* from KFD */
255 };
256 
258 {
259  uint32_t event_id; /* to KFD */
260  uint32_t pad;
261 };
262 
264 {
265  uint32_t event_id; /* to KFD */
266  uint32_t pad;
267 };
268 
270 {
271  uint32_t event_id; /* to KFD */
272  uint32_t pad;
273 };
274 
276 {
277  uint32_t NotPresent; /* Page not present or supervisor privilege */
278  uint32_t ReadOnly; /* Write access to a read-only page */
279  uint32_t NoExecute; /* Execute access to a page marked NX */
280  uint32_t imprecise; /* Can't determine the exact fault address */
281 };
282 
283 /* memory exception data */
285 {
287  uint64_t va;
288  uint32_t gpu_id;
289  uint32_t ErrorType; /* 0 = no RAS error,
290  * 1 = ECC_SRAM,
291  * 2 = Link_SYNFLOOD (poison),
292  * 3 = GPU hang(not attributable to a specific cause),
293  * other values reserved
294  */
295 };
296 
297 /* hw exception data */
299 {
300  uint32_t reset_type;
301  uint32_t reset_cause;
302  uint32_t memory_lost;
303  uint32_t gpu_id;
304 };
305 
306 /* Event data */
308 {
309  union
310  {
313  }; /* From KFD */
314  uint64_t kfd_event_data_ext; /* pointer to an extension structure
315  for future exception types */
316  uint32_t event_id; /* to KFD */
317  uint32_t pad;
318 };
319 
321 {
322  uint64_t events_ptr; /* pointed to struct
323  kfd_event_data array, to KFD */
324  uint32_t num_events; /* to KFD */
325  uint32_t wait_for_all; /* to KFD */
326  uint32_t timeout; /* to KFD */
327  uint32_t wait_result; /* from KFD */
328 };
329 
331 {
332  uint64_t va_addr; /* to KFD */
333  uint32_t gpu_id; /* to KFD */
334  uint32_t pad;
335 };
336 
338 {
339  /* to KFD: pointer to tile array */
340  uint64_t tile_config_ptr;
341  /* to KFD: pointer to macro tile array */
343  /* to KFD: array size allocated by user mode
344  * from KFD: array size filled by kernel
345  */
347  /* to KFD: array size allocated by user mode
348  * from KFD: array size filled by kernel
349  */
351 
352  uint32_t gpu_id; /* to KFD */
353  uint32_t gb_addr_config; /* from KFD */
354  uint32_t num_banks; /* from KFD */
355  uint32_t num_ranks; /* from KFD */
356  /* struct size can be extended later if needed
357  * without breaking ABI compatibility
358  */
359 };
360 
362 {
363  uint64_t tba_addr; /* to KFD */
364  uint64_t tma_addr; /* to KFD */
365  uint32_t gpu_id; /* to KFD */
366  uint32_t pad;
367 };
368 
370 {
371  uint32_t drm_fd; /* to KFD */
372  uint32_t gpu_id; /* to KFD */
373 };
374 
375 /* Allocation flags: memory types */
376 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
377 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
378 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
379 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
380 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
381 /* Allocation flags: attributes/access options */
382 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
383 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
384 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
385 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
386 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
387 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
388 
389 /* Allocate memory for later SVM (shared virtual memory) mapping.
390  *
391  * @va_addr: virtual address of the memory to be allocated
392  * all later mappings on all GPUs will use this address
393  * @size: size in bytes
394  * @handle: buffer handle returned to user mode, used to refer to
395  * this allocation for mapping, unmapping and freeing
396  * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
397  * for userptrs this is overloaded to specify the CPU address
398  * @gpu_id: device identifier
399  * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
400  */
402 {
403  uint64_t va_addr; /* to KFD */
404  uint64_t size; /* to KFD */
405  uint64_t handle; /* from KFD */
406  uint64_t mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */
407  uint32_t gpu_id; /* to KFD */
408  uint32_t flags;
409 };
410 
411 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
412  *
413  * @handle: memory handle returned by alloc
414  */
416 {
417  uint64_t handle; /* to KFD */
418 };
419 
420 /* Map memory to one or more GPUs
421  *
422  * @handle: memory handle returned by alloc
423  * @device_ids_array_ptr: array of gpu_ids (uint32_t per device)
424  * @n_devices: number of devices in the array
425  * @n_success: number of devices mapped successfully
426  *
427  * @n_success returns information to the caller how many devices from
428  * the start of the array have mapped the buffer successfully. It can
429  * be passed into a subsequent retry call to skip those devices. For
430  * the first call the caller should initialize it to 0.
431  *
432  * If the ioctl completes with return code 0 (success), n_success ==
433  * n_devices.
434  */
436 {
437  uint64_t handle; /* to KFD */
438  uint64_t device_ids_array_ptr; /* to KFD */
439  uint32_t n_devices; /* to KFD */
440  uint32_t n_success; /* to/from KFD */
441 };
442 
443 /* Unmap memory from one or more GPUs
444  *
445  * same arguments as for mapping
446  */
448 {
449  uint64_t handle; /* to KFD */
450  uint64_t device_ids_array_ptr; /* to KFD */
451  uint32_t n_devices; /* to KFD */
452  uint32_t n_success; /* to/from KFD */
453 };
454 
455 /* Allocate GWS for specific queue
456  *
457  * @queue_id: queue's id that GWS is allocated for
458  * @num_gws: how many GWS to allocate
459  * @first_gws: index of the first GWS allocated.
460  * only support contiguous GWS allocation
461  */
463 {
464  uint32_t queue_id; /* to KFD */
465  uint32_t num_gws; /* to KFD */
466  uint32_t first_gws; /* from KFD */
467  uint32_t pad;
468 };
469 
471 {
472  uint64_t size; /* from KFD */
473  uint64_t metadata_ptr; /* to KFD */
474  uint32_t metadata_size; /* to KFD (space allocated by user)
475  * from KFD (actual metadata size) */
476  uint32_t gpu_id; /* from KFD */
477  uint32_t flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
478  uint32_t dmabuf_fd; /* to KFD */
479 };
480 
482 {
483  uint64_t va_addr; /* to KFD */
484  uint64_t handle; /* from KFD */
485  uint32_t gpu_id; /* to KFD */
486  uint32_t dmabuf_fd; /* to KFD */
487 };
488 
489 /*
490  * KFD SMI(System Management Interface) events
491  */
493 {
494  KFD_SMI_EVENT_NONE = 0, /* not used */
495  KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */
499 };
500 
501 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
502 
504 {
505  uint32_t gpuid; /* to KFD */
506  uint32_t anon_fd; /* from KFD */
507 };
508 
509 /* Register offset inside the remapped mmio page
510  */
512 {
515 };
516 
517 #define AMDKFD_IOCTL_BASE 'K'
518 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
519 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
520 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
521 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
522 
523 #define AMDKFD_IOC_GET_VERSION \
524  AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
525 
526 #define AMDKFD_IOC_CREATE_QUEUE \
527  AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
528 
529 #define AMDKFD_IOC_DESTROY_QUEUE \
530  AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
531 
532 #define AMDKFD_IOC_SET_MEMORY_POLICY \
533  AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
534 
535 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \
536  AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
537 
538 #define AMDKFD_IOC_GET_PROCESS_APERTURES \
539  AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
540 
541 #define AMDKFD_IOC_UPDATE_QUEUE \
542  AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
543 
544 #define AMDKFD_IOC_CREATE_EVENT \
545  AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
546 
547 #define AMDKFD_IOC_DESTROY_EVENT \
548  AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
549 
550 #define AMDKFD_IOC_SET_EVENT \
551  AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
552 
553 #define AMDKFD_IOC_RESET_EVENT \
554  AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
555 
556 #define AMDKFD_IOC_WAIT_EVENTS \
557  AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
558 
559 #define AMDKFD_IOC_DBG_REGISTER \
560  AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
561 
562 #define AMDKFD_IOC_DBG_UNREGISTER \
563  AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
564 
565 #define AMDKFD_IOC_DBG_ADDRESS_WATCH \
566  AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
567 
568 #define AMDKFD_IOC_DBG_WAVE_CONTROL \
569  AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
570 
571 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
572  AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
573 
574 #define AMDKFD_IOC_GET_TILE_CONFIG \
575  AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
576 
577 #define AMDKFD_IOC_SET_TRAP_HANDLER \
578  AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
579 
580 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
581  AMDKFD_IOWR(0x14, \
582  struct kfd_ioctl_get_process_apertures_new_args)
583 
584 #define AMDKFD_IOC_ACQUIRE_VM \
585  AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
586 
587 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
588  AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
589 
590 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
591  AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
592 
593 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
594  AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
595 
596 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
597  AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
598 
599 #define AMDKFD_IOC_SET_CU_MASK \
600  AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
601 
602 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
603  AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
604 
605 #define AMDKFD_IOC_GET_DMABUF_INFO \
606  AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
607 
608 #define AMDKFD_IOC_IMPORT_DMABUF \
609  AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
610 
611 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \
612  AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
613 
614 #define AMDKFD_IOC_SMI_EVENTS \
615  AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args)
616 
617 #define AMDKFD_COMMAND_START 0x01
618 #define AMDKFD_COMMAND_END 0x20
619 
620 } // namespace gem5
621 
622 #endif
gem5::kfd_ioctl_create_queue_args::queue_priority
uint32_t queue_priority
Definition: kfd_ioctl.h:67
gem5::kfd_ioctl_import_dmabuf_args::handle
uint64_t handle
Definition: kfd_ioctl.h:484
gem5::kfd_event_data
Definition: kfd_ioctl.h:307
gem5::kfd_ioctl_get_tile_config_args::num_macro_tile_configs
uint32_t num_macro_tile_configs
Definition: kfd_ioctl.h:350
gem5::kfd_process_device_apertures::pad
uint32_t pad
Definition: kfd_ioctl.h:151
gem5::kfd_hsa_hw_exception_data::gpu_id
uint32_t gpu_id
Definition: kfd_ioctl.h:303
gem5::kfd_memory_exception_failure
Definition: kfd_ioctl.h:275
gem5::kfd_ioctl_dbg_address_watch_args::content_ptr
uint64_t content_ptr
Definition: kfd_ioctl.h:202
gem5::kfd_ioctl_get_process_apertures_new_args::pad
uint32_t pad
Definition: kfd_ioctl.h:181
gem5::kfd_ioctl_wait_events_args::events_ptr
uint64_t events_ptr
Definition: kfd_ioctl.h:322
gem5::kfd_ioctl_alloc_queue_gws_args
Definition: kfd_ioctl.h:462
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uint32_t event_slot_index
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gem5::kfd_ioctl_set_scratch_backing_va_args
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gem5::KFD_SMI_EVENT_GPU_PRE_RESET
@ KFD_SMI_EVENT_GPU_PRE_RESET
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@ KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL
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uint32_t num_gws
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@ KFD_SMI_EVENT_VMFAULT
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uint32_t imprecise
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uint32_t num_ranks
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uint32_t flags
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gem5::kfd_ioctl_smi_events_args
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gem5::KFD_SMI_EVENT_THERMAL_THROTTLE
@ KFD_SMI_EVENT_THERMAL_THROTTLE
Definition: kfd_ioctl.h:496
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Definition: kfd_ioctl.h:372
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struct kfd_hsa_hw_exception_data hw_exception_data
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struct kfd_memory_exception_failure failure
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uint32_t num_of_nodes
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uint32_t ctl_stack_size
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Definition: kfd_ioctl.h:451
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uint64_t handle
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struct kfd_hsa_memory_exception_data memory_exception_data
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uint32_t node_id
Definition: kfd_ioctl.h:251
gem5::KFD_SMI_EVENT_GPU_POST_RESET
@ KFD_SMI_EVENT_GPU_POST_RESET
Definition: kfd_ioctl.h:498
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kfd_smi_event
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uint32_t gpu_id
Definition: kfd_ioctl.h:365
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uint64_t device_ids_array_ptr
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NUM_OF_SUPPORTED_GPUS
#define NUM_OF_SUPPORTED_GPUS
Definition: kfd_ioctl.h:159
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uint32_t pad
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uint32_t pad
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gem5::kfd_ioctl_create_queue_args::write_pointer_address
uint64_t write_pointer_address
Definition: kfd_ioctl.h:59
gem5::kfd_ioctl_destroy_event_args
Definition: kfd_ioctl.h:257
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uint32_t queue_id
Definition: kfd_ioctl.h:87
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struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS]
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uint64_t scratch_limit
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gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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uint64_t alternate_aperture_base
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uint32_t gpu_id
Definition: kfd_ioctl.h:476
gem5::KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
@ KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
Definition: kfd_ioctl.h:513
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uint64_t size
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gem5::kfd_mmio_remap
kfd_mmio_remap
Definition: kfd_ioctl.h:511
gem5::kfd_ioctl_reset_event_args
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uint64_t read_pointer_address
Definition: kfd_ioctl.h:60
gem5::kfd_ioctl_wait_events_args
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gem5::kfd_ioctl_wait_events_args::wait_for_all
uint32_t wait_for_all
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gem5::kfd_ioctl_import_dmabuf_args::va_addr
uint64_t va_addr
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gem5::kfd_ioctl_alloc_memory_of_gpu_args::mmap_offset
uint64_t mmap_offset
Definition: kfd_ioctl.h:406
gem5::KFD_SMI_EVENT_NONE
@ KFD_SMI_EVENT_NONE
Definition: kfd_ioctl.h:494
gem5::kfd_ioctl_create_queue_args::queue_percentage
uint32_t queue_percentage
Definition: kfd_ioctl.h:66
gem5::kfd_ioctl_set_trap_handler_args::pad
uint32_t pad
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gem5::kfd_ioctl_get_process_apertures_args
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