gem5  v22.0.0.2
kfd_ioctl.h
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1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #ifndef KFD_IOCTL_H_INCLUDED
24 #define KFD_IOCTL_H_INCLUDED
25 
26 #include <cstdint>
27 #include <linux/ioctl.h>
28 #include <linux/types.h>
29 
30 namespace gem5
31 {
32 
33 /*
34  * - 1.1 - initial version
35  * - 1.3 - Add SMI events support
36  */
37 #define KFD_IOCTL_MAJOR_VERSION 1
38 #define KFD_IOCTL_MINOR_VERSION 3
39 
41 {
42  uint32_t major_version; /* from KFD */
43  uint32_t minor_version; /* from KFD */
44 };
45 
46 /* For kfd_ioctl_create_queue_args.queue_type. */
47 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0
48 #define KFD_IOC_QUEUE_TYPE_SDMA 1
49 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
50 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 3
51 
52 #define KFD_MAX_QUEUE_PERCENTAGE 100
53 #define KFD_MAX_QUEUE_PRIORITY 15
54 
56 {
57  uint64_t ring_base_address; /* to KFD */
58  uint64_t write_pointer_address; /* from KFD */
59  uint64_t read_pointer_address; /* from KFD */
60  uint64_t doorbell_offset; /* from KFD */
61 
62  uint32_t ring_size; /* to KFD */
63  uint32_t gpu_id; /* to KFD */
64  uint32_t queue_type; /* to KFD */
65  uint32_t queue_percentage; /* to KFD */
66  uint32_t queue_priority; /* to KFD */
67  uint32_t queue_id; /* from KFD */
68 
69  uint64_t eop_buffer_address; /* to KFD */
70  uint64_t eop_buffer_size; /* to KFD */
71  uint64_t ctx_save_restore_address; /* to KFD */
72  uint32_t ctx_save_restore_size; /* to KFD */
73  uint32_t ctl_stack_size; /* to KFD */
74 };
75 
77 {
78  uint32_t queue_id; /* to KFD */
79  uint32_t pad;
80 };
81 
83 {
84  uint64_t ring_base_address; /* to KFD */
85 
86  uint32_t queue_id; /* to KFD */
87  uint32_t ring_size; /* to KFD */
88  uint32_t queue_percentage; /* to KFD */
89  uint32_t queue_priority; /* to KFD */
90 };
91 
93 {
94  uint32_t queue_id; /* to KFD */
95  uint32_t num_cu_mask; /* to KFD */
96  uint64_t cu_mask_ptr; /* to KFD */
97 };
98 
100 {
101  uint64_t ctl_stack_address; /* to KFD */
102  uint32_t ctl_stack_used_size; /* from KFD */
103  uint32_t save_area_used_size; /* from KFD */
104  uint32_t queue_id; /* to KFD */
105  uint32_t pad;
106 };
107 
108 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
109 #define KFD_IOC_CACHE_POLICY_COHERENT 0
110 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
111 
113 {
114  uint64_t alternate_aperture_base; /* to KFD */
115  uint64_t alternate_aperture_size; /* to KFD */
116 
117  uint32_t gpu_id; /* to KFD */
118  uint32_t default_policy; /* to KFD */
119  uint32_t alternate_policy; /* to KFD */
120  uint32_t pad;
121 };
122 
123 /*
124  * All counters are monotonic. They are used for profiling of compute jobs.
125  * The profiling is done by userspace.
126  *
127  * In case of GPU reset, the counter should not be affected.
128  */
129 
131 {
132  uint64_t gpu_clock_counter; /* from KFD */
133  uint64_t cpu_clock_counter; /* from KFD */
134  uint64_t system_clock_counter; /* from KFD */
135  uint64_t system_clock_freq; /* from KFD */
136 
137  uint32_t gpu_id; /* to KFD */
138  uint32_t pad;
139 };
140 
142 {
143  uint64_t lds_base; /* from KFD */
144  uint64_t lds_limit; /* from KFD */
145  uint64_t scratch_base; /* from KFD */
146  uint64_t scratch_limit; /* from KFD */
147  uint64_t gpuvm_base; /* from KFD */
148  uint64_t gpuvm_limit; /* from KFD */
149  uint32_t gpu_id; /* from KFD */
150  uint32_t pad;
151 };
152 
153 /*
154  * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
155  * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
156  * unlimited number of GPUs.
157  */
158 #define NUM_OF_SUPPORTED_GPUS 7
160 {
163 
164  /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
165  uint32_t num_of_nodes;
166  uint32_t pad;
167 };
168 
170 {
171  /* User allocated. Pointer to struct kfd_process_device_apertures
172  * filled in by Kernel
173  */
175  /* to KFD - indicates amount of memory present in
176  * kfd_process_device_apertures_ptr
177  * from KFD - Number of entries filled by KFD.
178  */
179  uint32_t num_of_nodes;
180  uint32_t pad;
181 };
182 
183 #define MAX_ALLOWED_NUM_POINTS 100
184 #define MAX_ALLOWED_AW_BUFF_SIZE 4096
185 #define MAX_ALLOWED_WAC_BUFF_SIZE 128
186 
188 {
189  uint32_t gpu_id; /* to KFD */
190  uint32_t pad;
191 };
192 
194 {
195  uint32_t gpu_id; /* to KFD */
196  uint32_t pad;
197 };
198 
200 {
201  uint64_t content_ptr; /* a pointer to the actual content */
202  uint32_t gpu_id; /* to KFD */
203  uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
204 };
205 
207 {
208  uint64_t content_ptr; /* a pointer to the actual content */
209  uint32_t gpu_id; /* to KFD */
210  uint32_t buf_size_in_bytes; /*including gpu_id and buf_size */
211 };
212 
213 /* Matching HSA_EVENTTYPE */
214 #define KFD_IOC_EVENT_SIGNAL 0
215 #define KFD_IOC_EVENT_NODECHANGE 1
216 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2
217 #define KFD_IOC_EVENT_HW_EXCEPTION 3
218 #define KFD_IOC_EVENT_SYSTEM_EVENT 4
219 #define KFD_IOC_EVENT_DEBUG_EVENT 5
220 #define KFD_IOC_EVENT_PROFILE_EVENT 6
221 #define KFD_IOC_EVENT_QUEUE_EVENT 7
222 #define KFD_IOC_EVENT_MEMORY 8
223 
224 #define KFD_IOC_WAIT_RESULT_COMPLETE 0
225 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1
226 #define KFD_IOC_WAIT_RESULT_FAIL 2
227 
228 #define KFD_SIGNAL_EVENT_LIMIT 4096
229 
230 /* For kfd_event_data.hw_exception_data.reset_type. */
231 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
232 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
233 
234 /* For kfd_event_data.hw_exception_data.reset_cause. */
235 #define KFD_HW_EXCEPTION_GPU_HANG 0
236 #define KFD_HW_EXCEPTION_ECC 1
237 
238 /* For kfd_hsa_memory_exception_data.ErrorType */
239 #define KFD_MEM_ERR_NO_RAS 0
240 #define KFD_MEM_ERR_SRAM_ECC 1
241 #define KFD_MEM_ERR_POISON_CONSUMED 2
242 #define KFD_MEM_ERR_GPU_HANG 3
243 
245 {
246  uint64_t event_page_offset; /* from KFD */
247  uint32_t event_trigger_data; /* from KFD - signal events only */
248  uint32_t event_type; /* to KFD */
249  uint32_t auto_reset; /* to KFD */
250  uint32_t node_id; /* to KFD - only valid for certain
251  event types */
252  uint32_t event_id; /* from KFD */
253  uint32_t event_slot_index; /* from KFD */
254 };
255 
257 {
258  uint32_t event_id; /* to KFD */
259  uint32_t pad;
260 };
261 
263 {
264  uint32_t event_id; /* to KFD */
265  uint32_t pad;
266 };
267 
269 {
270  uint32_t event_id; /* to KFD */
271  uint32_t pad;
272 };
273 
275 {
276  uint32_t NotPresent; /* Page not present or supervisor privilege */
277  uint32_t ReadOnly; /* Write access to a read-only page */
278  uint32_t NoExecute; /* Execute access to a page marked NX */
279  uint32_t imprecise; /* Can't determine the exact fault address */
280 };
281 
282 /* memory exception data */
284 {
286  uint64_t va;
287  uint32_t gpu_id;
288  uint32_t ErrorType; /* 0 = no RAS error,
289  * 1 = ECC_SRAM,
290  * 2 = Link_SYNFLOOD (poison),
291  * 3 = GPU hang(not attributable to a specific cause),
292  * other values reserved
293  */
294 };
295 
296 /* hw exception data */
298 {
299  uint32_t reset_type;
300  uint32_t reset_cause;
301  uint32_t memory_lost;
302  uint32_t gpu_id;
303 };
304 
305 /* Event data */
307 {
308  union
309  {
312  }; /* From KFD */
313  uint64_t kfd_event_data_ext; /* pointer to an extension structure
314  for future exception types */
315  uint32_t event_id; /* to KFD */
316  uint32_t pad;
317 };
318 
320 {
321  uint64_t events_ptr; /* pointed to struct
322  kfd_event_data array, to KFD */
323  uint32_t num_events; /* to KFD */
324  uint32_t wait_for_all; /* to KFD */
325  uint32_t timeout; /* to KFD */
326  uint32_t wait_result; /* from KFD */
327 };
328 
330 {
331  uint64_t va_addr; /* to KFD */
332  uint32_t gpu_id; /* to KFD */
333  uint32_t pad;
334 };
335 
337 {
338  /* to KFD: pointer to tile array */
339  uint64_t tile_config_ptr;
340  /* to KFD: pointer to macro tile array */
342  /* to KFD: array size allocated by user mode
343  * from KFD: array size filled by kernel
344  */
346  /* to KFD: array size allocated by user mode
347  * from KFD: array size filled by kernel
348  */
350 
351  uint32_t gpu_id; /* to KFD */
352  uint32_t gb_addr_config; /* from KFD */
353  uint32_t num_banks; /* from KFD */
354  uint32_t num_ranks; /* from KFD */
355  /* struct size can be extended later if needed
356  * without breaking ABI compatibility
357  */
358 };
359 
361 {
362  uint64_t tba_addr; /* to KFD */
363  uint64_t tma_addr; /* to KFD */
364  uint32_t gpu_id; /* to KFD */
365  uint32_t pad;
366 };
367 
369 {
370  uint32_t drm_fd; /* to KFD */
371  uint32_t gpu_id; /* to KFD */
372 };
373 
374 /* Allocation flags: memory types */
375 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
376 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
377 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
378 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
379 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
380 /* Allocation flags: attributes/access options */
381 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
382 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
383 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
384 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
385 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
386 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
387 
388 /* Allocate memory for later SVM (shared virtual memory) mapping.
389  *
390  * @va_addr: virtual address of the memory to be allocated
391  * all later mappings on all GPUs will use this address
392  * @size: size in bytes
393  * @handle: buffer handle returned to user mode, used to refer to
394  * this allocation for mapping, unmapping and freeing
395  * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
396  * for userptrs this is overloaded to specify the CPU address
397  * @gpu_id: device identifier
398  * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
399  */
401 {
402  uint64_t va_addr; /* to KFD */
403  uint64_t size; /* to KFD */
404  uint64_t handle; /* from KFD */
405  uint64_t mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */
406  uint32_t gpu_id; /* to KFD */
407  uint32_t flags;
408 };
409 
410 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
411  *
412  * @handle: memory handle returned by alloc
413  */
415 {
416  uint64_t handle; /* to KFD */
417 };
418 
419 /* Map memory to one or more GPUs
420  *
421  * @handle: memory handle returned by alloc
422  * @device_ids_array_ptr: array of gpu_ids (uint32_t per device)
423  * @n_devices: number of devices in the array
424  * @n_success: number of devices mapped successfully
425  *
426  * @n_success returns information to the caller how many devices from
427  * the start of the array have mapped the buffer successfully. It can
428  * be passed into a subsequent retry call to skip those devices. For
429  * the first call the caller should initialize it to 0.
430  *
431  * If the ioctl completes with return code 0 (success), n_success ==
432  * n_devices.
433  */
435 {
436  uint64_t handle; /* to KFD */
437  uint64_t device_ids_array_ptr; /* to KFD */
438  uint32_t n_devices; /* to KFD */
439  uint32_t n_success; /* to/from KFD */
440 };
441 
442 /* Unmap memory from one or more GPUs
443  *
444  * same arguments as for mapping
445  */
447 {
448  uint64_t handle; /* to KFD */
449  uint64_t device_ids_array_ptr; /* to KFD */
450  uint32_t n_devices; /* to KFD */
451  uint32_t n_success; /* to/from KFD */
452 };
453 
454 /* Allocate GWS for specific queue
455  *
456  * @queue_id: queue's id that GWS is allocated for
457  * @num_gws: how many GWS to allocate
458  * @first_gws: index of the first GWS allocated.
459  * only support contiguous GWS allocation
460  */
462 {
463  uint32_t queue_id; /* to KFD */
464  uint32_t num_gws; /* to KFD */
465  uint32_t first_gws; /* from KFD */
466  uint32_t pad;
467 };
468 
470 {
471  uint64_t size; /* from KFD */
472  uint64_t metadata_ptr; /* to KFD */
473  uint32_t metadata_size; /* to KFD (space allocated by user)
474  * from KFD (actual metadata size) */
475  uint32_t gpu_id; /* from KFD */
476  uint32_t flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
477  uint32_t dmabuf_fd; /* to KFD */
478 };
479 
481 {
482  uint64_t va_addr; /* to KFD */
483  uint64_t handle; /* from KFD */
484  uint32_t gpu_id; /* to KFD */
485  uint32_t dmabuf_fd; /* to KFD */
486 };
487 
488 /*
489  * KFD SMI(System Management Interface) events
490  */
492 {
493  KFD_SMI_EVENT_NONE = 0, /* not used */
494  KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */
498 };
499 
500 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
501 
503 {
504  uint32_t gpuid; /* to KFD */
505  uint32_t anon_fd; /* from KFD */
506 };
507 
508 /* Register offset inside the remapped mmio page
509  */
511 {
514 };
515 
516 #define AMDKFD_IOCTL_BASE 'K'
517 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
518 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
519 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
520 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
521 
522 #define AMDKFD_IOC_GET_VERSION \
523  AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
524 
525 #define AMDKFD_IOC_CREATE_QUEUE \
526  AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
527 
528 #define AMDKFD_IOC_DESTROY_QUEUE \
529  AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
530 
531 #define AMDKFD_IOC_SET_MEMORY_POLICY \
532  AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
533 
534 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \
535  AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
536 
537 #define AMDKFD_IOC_GET_PROCESS_APERTURES \
538  AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
539 
540 #define AMDKFD_IOC_UPDATE_QUEUE \
541  AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
542 
543 #define AMDKFD_IOC_CREATE_EVENT \
544  AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
545 
546 #define AMDKFD_IOC_DESTROY_EVENT \
547  AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
548 
549 #define AMDKFD_IOC_SET_EVENT \
550  AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
551 
552 #define AMDKFD_IOC_RESET_EVENT \
553  AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
554 
555 #define AMDKFD_IOC_WAIT_EVENTS \
556  AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
557 
558 #define AMDKFD_IOC_DBG_REGISTER \
559  AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
560 
561 #define AMDKFD_IOC_DBG_UNREGISTER \
562  AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
563 
564 #define AMDKFD_IOC_DBG_ADDRESS_WATCH \
565  AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
566 
567 #define AMDKFD_IOC_DBG_WAVE_CONTROL \
568  AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
569 
570 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
571  AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
572 
573 #define AMDKFD_IOC_GET_TILE_CONFIG \
574  AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
575 
576 #define AMDKFD_IOC_SET_TRAP_HANDLER \
577  AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
578 
579 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
580  AMDKFD_IOWR(0x14, \
581  struct kfd_ioctl_get_process_apertures_new_args)
582 
583 #define AMDKFD_IOC_ACQUIRE_VM \
584  AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
585 
586 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
587  AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
588 
589 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
590  AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
591 
592 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
593  AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
594 
595 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
596  AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
597 
598 #define AMDKFD_IOC_SET_CU_MASK \
599  AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
600 
601 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
602  AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
603 
604 #define AMDKFD_IOC_GET_DMABUF_INFO \
605  AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
606 
607 #define AMDKFD_IOC_IMPORT_DMABUF \
608  AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
609 
610 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \
611  AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
612 
613 #define AMDKFD_IOC_SMI_EVENTS \
614  AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args)
615 
616 #define AMDKFD_COMMAND_START 0x01
617 #define AMDKFD_COMMAND_END 0x20
618 
619 } // namespace gem5
620 
621 #endif
gem5::kfd_ioctl_create_queue_args::queue_priority
uint32_t queue_priority
Definition: kfd_ioctl.h:66
gem5::kfd_ioctl_import_dmabuf_args::handle
uint64_t handle
Definition: kfd_ioctl.h:483
gem5::kfd_event_data
Definition: kfd_ioctl.h:306
gem5::kfd_ioctl_get_tile_config_args::num_macro_tile_configs
uint32_t num_macro_tile_configs
Definition: kfd_ioctl.h:349
gem5::kfd_process_device_apertures::pad
uint32_t pad
Definition: kfd_ioctl.h:150
gem5::kfd_hsa_hw_exception_data::gpu_id
uint32_t gpu_id
Definition: kfd_ioctl.h:302
gem5::kfd_memory_exception_failure
Definition: kfd_ioctl.h:274
gem5::kfd_ioctl_dbg_address_watch_args::content_ptr
uint64_t content_ptr
Definition: kfd_ioctl.h:201
gem5::kfd_ioctl_get_process_apertures_new_args::pad
uint32_t pad
Definition: kfd_ioctl.h:180
gem5::kfd_ioctl_wait_events_args::events_ptr
uint64_t events_ptr
Definition: kfd_ioctl.h:321
gem5::kfd_ioctl_alloc_queue_gws_args
Definition: kfd_ioctl.h:461
gem5::kfd_ioctl_get_process_apertures_new_args::num_of_nodes
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@ KFD_SMI_EVENT_GPU_PRE_RESET
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@ KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL
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@ KFD_SMI_EVENT_VMFAULT
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@ KFD_SMI_EVENT_THERMAL_THROTTLE
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@ KFD_SMI_EVENT_GPU_POST_RESET
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kfd_smi_event
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NUM_OF_SUPPORTED_GPUS
#define NUM_OF_SUPPORTED_GPUS
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struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS]
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gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
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gem5::KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
@ KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
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uint64_t size
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kfd_mmio_remap
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uint32_t wait_for_all
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gem5::kfd_ioctl_alloc_memory_of_gpu_args::mmap_offset
uint64_t mmap_offset
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gem5::KFD_SMI_EVENT_NONE
@ KFD_SMI_EVENT_NONE
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