gem5
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arch
x86
insts
microregop.hh
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_INSTS_MICROREGOP_HH__
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#define __ARCH_X86_INSTS_MICROREGOP_HH__
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#include "
arch/x86/insts/microop.hh
"
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#include "
arch/x86/insts/microop_args.hh
"
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namespace
gem5
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{
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namespace
X86ISA
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{
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class
RegOpBase
:
public
X86MicroopBase
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{
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protected
:
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const
uint16_t
ext
;
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RegOpBase
(
ExtMachInst
mach_inst,
const
char
*mnem,
const
char
*inst_mnem,
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uint64_t set_flags, OpClass op_class, uint8_t data_size,
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uint16_t _ext) :
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X86MicroopBase
(mach_inst, mnem, inst_mnem, set_flags, op_class),
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ext
(_ext),
dataSize
(data_size),
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foldOBit
((data_size == 1 && !mach_inst.rex.
present
) ? 1 << 6 : 0)
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{}
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//Figure out what the condition code flags should be.
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uint64_t
genFlags
(uint64_t old_flags, uint64_t flag_mask,
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uint64_t _dest, uint64_t _src1, uint64_t _src2,
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bool
subtract=
false
)
const
;
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public
:
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const
uint8_t
dataSize
;
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const
RegIndex
foldOBit
;
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};
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template
<
typename
...Operands>
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using
RegOpT
=
InstOperands
<
RegOpBase
, Operands...>;
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}
// namespace X86ISA
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}
// namespace gem5
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#endif
//__ARCH_X86_INSTS_MICROREGOP_HH__
gem5::X86ISA::InstOperands
Definition
microop_args.hh:396
gem5::X86ISA::RegOpBase
Definition
microregop.hh:51
gem5::X86ISA::RegOpBase::dataSize
const uint8_t dataSize
Definition
microregop.hh:69
gem5::X86ISA::RegOpBase::genFlags
uint64_t genFlags(uint64_t old_flags, uint64_t flag_mask, uint64_t _dest, uint64_t _src1, uint64_t _src2, bool subtract=false) const
Definition
microregop.cc:53
gem5::X86ISA::RegOpBase::RegOpBase
RegOpBase(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, uint8_t data_size, uint16_t _ext)
Definition
microregop.hh:55
gem5::X86ISA::RegOpBase::foldOBit
const RegIndex foldOBit
Definition
microregop.hh:70
gem5::X86ISA::RegOpBase::ext
const uint16_t ext
Definition
microregop.hh:53
gem5::X86ISA::X86MicroopBase
Definition
microop.hh:98
microop.hh
microop_args.hh
gem5::X86ISA::present
Bitfield< 7 > present
Definition
misc.hh:1027
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::RegIndex
uint16_t RegIndex
Definition
types.hh:176
gem5::X86ISA::ExtMachInst
Definition
types.hh:213
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