gem5 v24.0.0.0
Loading...
Searching...
No Matches
microop_args.hh
Go to the documentation of this file.
1/*
2 * Copyright 2021 Google Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
29#define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
30
31#include <cstdint>
32#include <sstream>
33#include <string>
34#include <tuple>
35#include <type_traits>
36#include <utility>
37
40#include "arch/x86/regs/int.hh"
41#include "arch/x86/regs/misc.hh"
43#include "arch/x86/types.hh"
44#include "base/compiler.hh"
45#include "base/cprintf.hh"
46#include "cpu/reg_class.hh"
47#include "sim/faults.hh"
48
49namespace gem5
50{
51
52namespace X86ISA
53{
54
55struct DestOp
56{
58 const size_t size;
59 RegIndex opIndex() const { return dest; }
60
61 DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
62 template <class InstType>
63 DestOp(RegIndex _dest, InstType *inst) : dest(_dest),
64 size(inst->getDestSize())
65 {}
66};
67
68struct Src1Op
69{
71 const size_t size;
72 RegIndex opIndex() const { return src1; }
73
74 Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
75 template <class InstType>
76 Src1Op(RegIndex _src1, InstType *inst) : src1(_src1),
77 size(inst->getSrcSize())
78 {}
79};
80
81struct Src2Op
82{
84 const size_t size;
85 RegIndex opIndex() const { return src2; }
86
87 Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
88 template <class InstType>
89 Src2Op(RegIndex _src2, InstType *inst) : src2(_src2),
90 size(inst->getSrcSize())
91 {}
92};
93
94struct Src3Op
95{
97 const size_t size;
98 RegIndex opIndex() const { return src3; }
99
100 Src3Op(RegIndex _src3, size_t _size) : src3(_src3), size(_size) {}
101 template <class InstType>
102 Src3Op(RegIndex _src3, InstType *inst) : src3(_src3),
103 size(inst->getSrcSize())
104 {}
105};
106
107struct DataOp
108{
110 const size_t size;
111 RegIndex opIndex() const { return data; }
112
113 DataOp(RegIndex _data, size_t _size) : data(_data), size(_size) {}
114};
115
117{
119 const size_t size;
120 RegIndex opIndex() const { return dataHi; }
121
122 DataHiOp(RegIndex data_hi, size_t _size) : dataHi(data_hi), size(_size) {}
123};
124
126{
128 const size_t size;
129 RegIndex opIndex() const { return dataLow; }
130
131 DataLowOp(RegIndex data_low, size_t _size) : dataLow(data_low), size(_size)
132 {}
133};
134
135template <class T, class Enabled=void>
136struct HasDataSize : public std::false_type {};
137
138template <class T>
139struct HasDataSize<T, decltype((void)&T::dataSize)> : public std::true_type {};
140
141template <class T>
143
144template <class Base>
145struct IntOp : public Base
146{
148
149 template <class Inst>
150 IntOp(Inst *inst, std::enable_if_t<HasDataSizeV<Inst>, ArgType> idx) :
151 Base(idx.index, inst->dataSize)
152 {}
153
154 template <class Inst>
155 IntOp(Inst *inst, std::enable_if_t<!HasDataSizeV<Inst>, ArgType> idx) :
156 Base(idx.index, inst)
157 {}
158
159 void
160 print(std::ostream &os) const
161 {
162 X86StaticInst::printReg(os, intRegClass[this->opIndex()], this->size);
163 }
164};
165
166template <class Base>
167struct FoldedOp : public Base
168{
170
171 template <class InstType>
172 FoldedOp(InstType *inst, ArgType idx) :
173 Base(intRegFolded(idx.index, inst->foldOBit), inst->dataSize)
174 {}
175
176 void
177 print(std::ostream &os) const
178 {
179 X86StaticInst::printReg(os, intRegClass[this->opIndex()], this->size);
180 }
181};
182
183template <class Base>
184struct CrOp : public Base
185{
187
188 template <class InstType>
189 CrOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
190
191 void
192 print(std::ostream &os) const
193 {
194 ccprintf(os, "cr%d", this->opIndex());
195 }
196};
197
198template <class Base>
199struct DbgOp : public Base
200{
202
203 template <class InstType>
204 DbgOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
205
206 void
207 print(std::ostream &os) const
208 {
209 ccprintf(os, "dr%d", this->opIndex());
210 }
211
212};
213
214template <class Base>
215struct SegOp : public Base
216{
218
219 template <class InstType>
220 SegOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
221
222 void
223 print(std::ostream &os) const
224 {
225 X86StaticInst::printSegment(os, this->opIndex());
226 }
227};
228
229template <class Base>
230struct MiscOp : public Base
231{
233
234 template <class InstType>
235 MiscOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
236
237 void
238 print(std::ostream &os) const
239 {
240 X86StaticInst::printReg(os, miscRegClass[this->opIndex()], this->size);
241 }
242};
243
244template <class Base>
245struct FloatOp : public Base
246{
248
249 template <class Inst>
250 FloatOp(Inst *inst, std::enable_if_t<HasDataSizeV<Inst>, ArgType> idx) :
251 Base(idx.index, inst->dataSize)
252 {}
253
254 template <class Inst>
255 FloatOp(Inst *inst, std::enable_if_t<!HasDataSizeV<Inst>, ArgType> idx) :
256 Base(idx.index, inst)
257 {}
258
259 void
260 print(std::ostream &os) const
261 {
262 X86StaticInst::printReg(os, floatRegClass[this->opIndex()],
263 this->size);
264 }
265};
266
274
282
286
288
293
294struct Imm8Op
295{
296 using ArgType = uint8_t;
297
298 uint8_t imm8;
299
300 template <class InstType>
301 Imm8Op(InstType *inst, ArgType _imm8) : imm8(_imm8) {}
302
303 void
304 print(std::ostream &os) const
305 {
306 ccprintf(os, "%#x", imm8);
307 }
308};
309
311{
312 using ArgType = uint64_t;
313
314 uint64_t imm64;
315
316 template <class InstType>
317 Imm64Op(InstType *inst, ArgType _imm64) : imm64(_imm64) {}
318
319 void
320 print(std::ostream &os) const
321 {
322 ccprintf(os, "%#x", imm64);
323 }
324};
325
326struct UpcOp
327{
329
331
332 template <class InstType>
333 UpcOp(InstType *inst, ArgType _target) : target(_target) {}
334
335 void
336 print(std::ostream &os) const
337 {
338 ccprintf(os, "%#x", target);
339 }
340};
341
343{
344 using ArgType = Fault;
345
347
348 template <class InstType>
349 FaultOp(InstType *inst, ArgType _fault) : fault(_fault) {}
350
351 void
352 print(std::ostream &os) const
353 {
354 ccprintf(os, fault ? fault->name() : "NoFault");
355 }
356};
357
358struct AddrOp
359{
368
369 const uint8_t scale;
372 const uint64_t disp;
373 const uint8_t segment;
374 const size_t size;
375
376 template <class InstType>
377 AddrOp(InstType *inst, const ArgType &args) : scale(args.scale),
378 index(intRegFolded(args.index.index, inst->foldABit)),
379 base(intRegFolded(args.base.index, inst->foldABit)),
380 disp(args.disp), segment(args.segment.index),
381 size(inst->addressSize)
382 {
384 }
385
386 void
387 print(std::ostream &os) const
388 {
390 os, segment, scale, index, base, disp, size, false);
391 }
392};
393
394template <typename Base, typename ...Operands>
395class InstOperands : public Base, public Operands...
396{
397 private:
398 using ArgTuple = std::tuple<typename Operands::ArgType...>;
399
400 template <std::size_t ...I, typename ...CTorArgs>
401 InstOperands(std::index_sequence<I...>, ExtMachInst mach_inst,
402 const char *mnem, const char *inst_mnem, uint64_t set_flags,
403 OpClass op_class, [[maybe_unused]] ArgTuple args,
404 CTorArgs... ctor_args) :
405 Base(mach_inst, mnem, inst_mnem, set_flags, op_class, ctor_args...),
406 Operands(this, std::get<I>(args))...
407 {}
408
409 protected:
410 template <typename ...CTorArgs>
411 InstOperands(ExtMachInst mach_inst, const char *mnem,
412 const char *inst_mnem, uint64_t set_flags, OpClass op_class,
413 ArgTuple args, CTorArgs... ctor_args) :
414 InstOperands(std::make_index_sequence<sizeof...(Operands)>{},
415 mach_inst, mnem, inst_mnem, set_flags, op_class,
416 std::move(args), ctor_args...)
417 {}
418
419 std::string
421 const loader::SymbolTable *symtab) const override
422 {
423 std::stringstream response;
424 Base::printMnemonic(response, this->instMnem, this->mnemonic);
425 int count = 0;
426 GEM5_FOR_EACH_IN_PACK(ccprintf(response, count++ ? ", " : ""),
427 Operands::print(response));
428 return response.str();
429 }
430};
431
432} // namespace X86ISA
433} // namespace gem5
434
435#endif //__ARCH_X86_INSTS_MICROOP_ARGS_HH__
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
InstOperands(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, ArgTuple args, CTorArgs... ctor_args)
std::tuple< typename Operands::ArgType... > ArgTuple
InstOperands(std::index_sequence< I... >, ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, ArgTuple args, CTorArgs... ctor_args)
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
static void printSegment(std::ostream &os, int segment)
static void printReg(std::ostream &os, RegId reg, int size)
constexpr RegClass miscRegClass
Definition misc.hh:2937
Bitfield< 19 > pc
Definition misc.hh:840
Bitfield< 17 > os
Definition misc.hh:838
constexpr RegClass intRegClass
Definition int.hh:123
constexpr bool HasDataSizeV
Bitfield< 5, 3 > index
Definition types.hh:98
static constexpr RegId intRegFolded(RegIndex index, RegIndex foldBit)
Definition int.hh:187
constexpr RegClass floatRegClass
Definition float.hh:143
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint16_t MicroPC
Definition types.hh:149
void ccprintf(cp::Print &print)
Definition cprintf.hh:130
Overload hash function for BasicBlockRange type.
Definition binary32.hh:81
const uint64_t disp
const RegIndex index
void print(std::ostream &os) const
const uint8_t segment
AddrOp(InstType *inst, const ArgType &args)
const RegIndex base
CrOp(InstType *inst, ArgType idx)
void print(std::ostream &os) const
RegIndex opIndex() const
DataHiOp(RegIndex data_hi, size_t _size)
DataLowOp(RegIndex data_low, size_t _size)
RegIndex opIndex() const
const RegIndex data
DataOp(RegIndex _data, size_t _size)
RegIndex opIndex() const
void print(std::ostream &os) const
DbgOp(InstType *inst, ArgType idx)
DestOp(RegIndex _dest, InstType *inst)
const RegIndex dest
DestOp(RegIndex _dest, size_t _size)
RegIndex opIndex() const
void print(std::ostream &os) const
FaultOp(InstType *inst, ArgType _fault)
FloatOp(Inst *inst, std::enable_if_t< HasDataSizeV< Inst >, ArgType > idx)
FloatOp(Inst *inst, std::enable_if_t<!HasDataSizeV< Inst >, ArgType > idx)
void print(std::ostream &os) const
void print(std::ostream &os) const
FoldedOp(InstType *inst, ArgType idx)
Classes for register indices passed to instruction constructors.
void print(std::ostream &os) const
Imm64Op(InstType *inst, ArgType _imm64)
Imm8Op(InstType *inst, ArgType _imm8)
void print(std::ostream &os) const
IntOp(Inst *inst, std::enable_if_t<!HasDataSizeV< Inst >, ArgType > idx)
void print(std::ostream &os) const
IntOp(Inst *inst, std::enable_if_t< HasDataSizeV< Inst >, ArgType > idx)
MiscOp(InstType *inst, ArgType idx)
void print(std::ostream &os) const
SegOp(InstType *inst, ArgType idx)
void print(std::ostream &os) const
const RegIndex src1
Src1Op(RegIndex _src1, size_t _size)
Src1Op(RegIndex _src1, InstType *inst)
RegIndex opIndex() const
const RegIndex src2
Src2Op(RegIndex _src2, InstType *inst)
Src2Op(RegIndex _src2, size_t _size)
RegIndex opIndex() const
RegIndex opIndex() const
Src3Op(RegIndex _src3, InstType *inst)
const RegIndex src3
Src3Op(RegIndex _src3, size_t _size)
UpcOp(InstType *inst, ArgType _target)
void print(std::ostream &os) const

Generated on Tue Jun 18 2024 16:24:00 for gem5 by doxygen 1.11.0