gem5  v21.2.1.1
microop_args.hh
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27 
28 #ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
29 #define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
30 
31 #include <cstdint>
32 #include <sstream>
33 #include <string>
34 #include <tuple>
35 #include <type_traits>
36 #include <utility>
37 
39 #include "arch/x86/regs/int.hh"
40 #include "arch/x86/types.hh"
41 #include "base/compiler.hh"
42 #include "base/cprintf.hh"
43 #include "cpu/reg_class.hh"
44 #include "sim/faults.hh"
45 
46 namespace gem5
47 {
48 
49 namespace X86ISA
50 {
51 
52 struct DestOp
53 {
54  const RegIndex dest;
55  const size_t size;
56  RegIndex opIndex() const { return dest; }
57 
58  DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
59  template <class InstType>
60  DestOp(RegIndex _dest, InstType *inst) : dest(_dest),
61  size(inst->getDestSize())
62  {}
63 };
64 
65 struct Src1Op
66 {
67  const RegIndex src1;
68  const size_t size;
69  RegIndex opIndex() const { return src1; }
70 
71  Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
72  template <class InstType>
73  Src1Op(RegIndex _src1, InstType *inst) : src1(_src1),
74  size(inst->getSrcSize())
75  {}
76 };
77 
78 struct Src2Op
79 {
80  const RegIndex src2;
81  const size_t size;
82  RegIndex opIndex() const { return src2; }
83 
84  Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
85  template <class InstType>
86  Src2Op(RegIndex _src2, InstType *inst) : src2(_src2),
87  size(inst->getSrcSize())
88  {}
89 };
90 
91 struct DataOp
92 {
93  const RegIndex data;
94  const size_t size;
95  RegIndex opIndex() const { return data; }
96 
97  DataOp(RegIndex _data, size_t _size) : data(_data), size(_size) {}
98 };
99 
100 struct DataHiOp
101 {
103  const size_t size;
104  RegIndex opIndex() const { return dataHi; }
105 
106  DataHiOp(RegIndex data_hi, size_t _size) : dataHi(data_hi), size(_size) {}
107 };
108 
109 struct DataLowOp
110 {
112  const size_t size;
113  RegIndex opIndex() const { return dataLow; }
114 
115  DataLowOp(RegIndex data_low, size_t _size) : dataLow(data_low), size(_size)
116  {}
117 };
118 
119 template <class T, class Enabled=void>
120 struct HasDataSize : public std::false_type {};
121 
122 template <class T>
123 struct HasDataSize<T, decltype((void)&T::dataSize)> : public std::true_type {};
124 
125 template <class T>
127 
128 template <class Base>
129 struct IntOp : public Base
130 {
132 
133  template <class Inst>
134  IntOp(Inst *inst, std::enable_if_t<HasDataSizeV<Inst>, ArgType> idx) :
135  Base(idx.index, inst->dataSize)
136  {}
137 
138  template <class Inst>
139  IntOp(Inst *inst, std::enable_if_t<!HasDataSizeV<Inst>, ArgType> idx) :
140  Base(idx.index, inst)
141  {}
142 
143  void
144  print(std::ostream &os) const
145  {
146  X86StaticInst::printReg(os, RegId(IntRegClass, this->opIndex()),
147  this->size);
148  }
149 };
150 
151 template <class Base>
152 struct FoldedOp : public Base
153 {
155 
156  template <class InstType>
157  FoldedOp(InstType *inst, ArgType idx) :
158  Base(INTREG_FOLDED(idx.index, inst->foldOBit), inst->dataSize)
159  {}
160 
161  void
162  print(std::ostream &os) const
163  {
164  X86StaticInst::printReg(os, RegId(IntRegClass, this->opIndex()),
165  this->size);
166  }
167 };
168 
169 template <class Base>
170 struct CrOp : public Base
171 {
173 
174  template <class InstType>
175  CrOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
176 
177  void
178  print(std::ostream &os) const
179  {
180  ccprintf(os, "cr%d", this->opIndex());
181  }
182 };
183 
184 template <class Base>
185 struct DbgOp : public Base
186 {
188 
189  template <class InstType>
190  DbgOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
191 
192  void
193  print(std::ostream &os) const
194  {
195  ccprintf(os, "dr%d", this->opIndex());
196  }
197 
198 };
199 
200 template <class Base>
201 struct SegOp : public Base
202 {
204 
205  template <class InstType>
206  SegOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
207 
208  void
209  print(std::ostream &os) const
210  {
211  X86StaticInst::printSegment(os, this->opIndex());
212  }
213 };
214 
215 template <class Base>
216 struct MiscOp : public Base
217 {
219 
220  template <class InstType>
221  MiscOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
222 
223  void
224  print(std::ostream &os) const
225  {
226  X86StaticInst::printReg(os, RegId(MiscRegClass, this->opIndex()),
227  this->size);
228  }
229 };
230 
231 template <class Base>
232 struct FloatOp : public Base
233 {
235 
236  template <class Inst>
237  FloatOp(Inst *inst, std::enable_if_t<HasDataSizeV<Inst>, ArgType> idx) :
238  Base(idx.index, inst->dataSize)
239  {}
240 
241  template <class Inst>
242  FloatOp(Inst *inst, std::enable_if_t<!HasDataSizeV<Inst>, ArgType> idx) :
243  Base(idx.index, inst)
244  {}
245 
246  void
247  print(std::ostream &os) const
248  {
249  X86StaticInst::printReg(os, RegId(FloatRegClass, this->opIndex()),
250  this->size);
251  }
252 };
253 
261 
269 
273 
278 
279 struct Imm8Op
280 {
281  using ArgType = uint8_t;
282 
283  uint8_t imm8;
284 
285  template <class InstType>
286  Imm8Op(InstType *inst, ArgType _imm8) : imm8(_imm8) {}
287 
288  void
289  print(std::ostream &os) const
290  {
291  ccprintf(os, "%#x", imm8);
292  }
293 };
294 
295 struct Imm64Op
296 {
297  using ArgType = uint64_t;
298 
299  uint64_t imm64;
300 
301  template <class InstType>
302  Imm64Op(InstType *inst, ArgType _imm64) : imm64(_imm64) {}
303 
304  void
305  print(std::ostream &os) const
306  {
307  ccprintf(os, "%#x", imm64);
308  }
309 };
310 
311 struct UpcOp
312 {
313  using ArgType = MicroPC;
314 
316 
317  template <class InstType>
318  UpcOp(InstType *inst, ArgType _target) : target(_target) {}
319 
320  void
321  print(std::ostream &os) const
322  {
323  ccprintf(os, "%#x", target);
324  }
325 };
326 
327 struct FaultOp
328 {
329  using ArgType = Fault;
330 
332 
333  template <class InstType>
334  FaultOp(InstType *inst, ArgType _fault) : fault(_fault) {}
335 
336  void
337  print(std::ostream &os) const
338  {
339  ccprintf(os, fault ? fault->name() : "NoFault");
340  }
341 };
342 
343 struct AddrOp
344 {
345  struct ArgType
346  {
347  uint8_t scale;
350  uint64_t disp;
352  };
353 
354  const uint8_t scale;
356  const RegIndex base;
357  const uint64_t disp;
358  const uint8_t segment;
359  const size_t size;
360 
361  template <class InstType>
362  AddrOp(InstType *inst, const ArgType &args) : scale(args.scale),
363  index(INTREG_FOLDED(args.index.index, inst->foldABit)),
364  base(INTREG_FOLDED(args.base.index, inst->foldABit)),
365  disp(args.disp), segment(args.segment.index),
366  size(inst->addressSize)
367  {
368  assert(segment < NUM_SEGMENTREGS);
369  }
370 
371  void
372  print(std::ostream &os) const
373  {
375  os, segment, scale, index, base, disp, size, false);
376  }
377 };
378 
379 template <typename Base, typename ...Operands>
380 class InstOperands : public Base, public Operands...
381 {
382  private:
383  using ArgTuple = std::tuple<typename Operands::ArgType...>;
384 
385  template <std::size_t ...I, typename ...CTorArgs>
386  InstOperands(std::index_sequence<I...>, ExtMachInst mach_inst,
387  const char *mnem, const char *inst_mnem, uint64_t set_flags,
388  OpClass op_class, [[maybe_unused]] ArgTuple args,
389  CTorArgs... ctor_args) :
390  Base(mach_inst, mnem, inst_mnem, set_flags, op_class, ctor_args...),
391  Operands(this, std::get<I>(args))...
392  {}
393 
394  protected:
395  template <typename ...CTorArgs>
396  InstOperands(ExtMachInst mach_inst, const char *mnem,
397  const char *inst_mnem, uint64_t set_flags, OpClass op_class,
398  ArgTuple args, CTorArgs... ctor_args) :
399  InstOperands(std::make_index_sequence<sizeof...(Operands)>{},
400  mach_inst, mnem, inst_mnem, set_flags, op_class,
401  std::move(args), ctor_args...)
402  {}
403 
404  std::string
406  const loader::SymbolTable *symtab) const override
407  {
408  std::stringstream response;
409  Base::printMnemonic(response, this->instMnem, this->mnemonic);
410  int count = 0;
411  GEM5_FOR_EACH_IN_PACK(ccprintf(response, count++ ? ", " : ""),
412  Operands::print(response));
413  return response.str();
414  }
415 };
416 
417 } // namespace X86ISA
418 } // namespace gem5
419 
420 #endif //__ARCH_X86_INSTS_MICROOP_ARGS_HH__
gem5::X86ISA::UpcOp::UpcOp
UpcOp(InstType *inst, ArgType _target)
Definition: microop_args.hh:318
gem5::X86ISA::FpRegIndex
Definition: static_inst.hh:65
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::UpcOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:321
gem5::X86ISA::MiscOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:224
gem5::X86ISA::FaultOp::FaultOp
FaultOp(InstType *inst, ArgType _fault)
Definition: microop_args.hh:334
gem5::X86ISA::DestOp
Definition: microop_args.hh:52
gem5::X86ISA::Src1Op::Src1Op
Src1Op(RegIndex _src1, size_t _size)
Definition: microop_args.hh:71
gem5::X86ISA::Imm64Op::ArgType
uint64_t ArgType
Definition: microop_args.hh:297
gem5::X86ISA::FoldedOp::FoldedOp
FoldedOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:157
gem5::X86ISA::Imm8Op::Imm8Op
Imm8Op(InstType *inst, ArgType _imm8)
Definition: microop_args.hh:286
gem5::X86ISA::GpRegIndex
Classes for register indices passed to instruction constructors.
Definition: static_inst.hh:59
gem5::X86ISA::Imm8Op::print
void print(std::ostream &os) const
Definition: microop_args.hh:289
gem5::X86ISA::DataHiOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:104
gem5::X86ISA::FaultOp::ArgType
Fault ArgType
Definition: microop_args.hh:329
gem5::X86ISA::DestOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:56
gem5::X86ISA::Imm8Op::ArgType
uint8_t ArgType
Definition: microop_args.hh:281
gem5::X86ISA::Imm64Op::print
void print(std::ostream &os) const
Definition: microop_args.hh:305
gem5::X86ISA::DestOp::DestOp
DestOp(RegIndex _dest, size_t _size)
Definition: microop_args.hh:58
gem5::X86ISA::DataHiOp
Definition: microop_args.hh:100
gem5::X86ISA::DataLowOp::size
const size_t size
Definition: microop_args.hh:112
gem5::X86ISA::Imm8Op
Definition: microop_args.hh:279
static_inst.hh
gem5::X86ISA::DbgOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:193
gem5::X86ISA::DataHiOp::size
const size_t size
Definition: microop_args.hh:103
gem5::X86ISA::CrRegIndex
Definition: static_inst.hh:77
gem5::X86ISA::Src2Op::Src2Op
Src2Op(RegIndex _src2, size_t _size)
Definition: microop_args.hh:84
gem5::X86ISA::Imm64Op::Imm64Op
Imm64Op(InstType *inst, ArgType _imm64)
Definition: microop_args.hh:302
gem5::X86ISA::FaultOp::fault
Fault fault
Definition: microop_args.hh:331
gem5::X86ISA::AddrOp::ArgType
Definition: microop_args.hh:345
gem5::X86ISA::DataLowOp
Definition: microop_args.hh:109
gem5::X86ISA::Imm64Op::imm64
uint64_t imm64
Definition: microop_args.hh:299
gem5::X86ISA::Src1Op::Src1Op
Src1Op(RegIndex _src1, InstType *inst)
Definition: microop_args.hh:73
gem5::X86ISA::DataLowOp::DataLowOp
DataLowOp(RegIndex data_low, size_t _size)
Definition: microop_args.hh:115
gem5::X86ISA::InstOperands::InstOperands
InstOperands(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, ArgTuple args, CTorArgs... ctor_args)
Definition: microop_args.hh:396
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:257
gem5::X86ISA::Src1Op::size
const size_t size
Definition: microop_args.hh:68
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::INTREG_FOLDED
static IntRegIndex INTREG_FOLDED(int index, int foldBit)
Definition: int.hh:181
gem5::X86ISA::FaultOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:337
gem5::X86ISA::CrOp::CrOp
CrOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:175
gem5::X86ISA::IntOp
Definition: microop_args.hh:129
gem5::X86ISA::AddrOp::base
const RegIndex base
Definition: microop_args.hh:356
gem5::X86ISA::Src2Op::Src2Op
Src2Op(RegIndex _src2, InstType *inst)
Definition: microop_args.hh:86
faults.hh
gem5::X86ISA::AddrOp
Definition: microop_args.hh:343
gem5::X86ISA::AddrOp::ArgType::disp
uint64_t disp
Definition: microop_args.hh:350
gem5::X86ISA::FloatOp::FloatOp
FloatOp(Inst *inst, std::enable_if_t<!HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:242
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::X86ISA::FloatOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:247
gem5::X86ISA::AddrOp::ArgType::scale
uint8_t scale
Definition: microop_args.hh:347
gem5::X86ISA::IntOp::IntOp
IntOp(Inst *inst, std::enable_if_t<!HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:139
gem5::X86ISA::DbgOp
Definition: microop_args.hh:185
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::X86ISA::HasDataSize
Definition: microop_args.hh:120
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::X86ISA::DestOp::dest
const RegIndex dest
Definition: microop_args.hh:54
gem5::X86ISA::DestOp::size
const size_t size
Definition: microop_args.hh:55
gem5::X86ISA::Src2Op::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:82
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::X86ISA::DataHiOp::dataHi
const RegIndex dataHi
Definition: microop_args.hh:102
gem5::X86ISA::SegOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:209
gem5::X86ISA::NUM_SEGMENTREGS
@ NUM_SEGMENTREGS
Definition: segment.hh:65
gem5::X86ISA::DataLowOp::dataLow
const RegIndex dataLow
Definition: microop_args.hh:111
gem5::X86ISA::FoldedOp
Definition: microop_args.hh:152
int.hh
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::X86ISA::AddrOp::segment
const uint8_t segment
Definition: microop_args.hh:358
gem5::X86ISA::Imm64Op
Definition: microop_args.hh:295
gem5::X86ISA::HasDataSizeV
constexpr bool HasDataSizeV
Definition: microop_args.hh:126
gem5::X86ISA::DataOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:95
gem5::X86ISA::UpcOp::target
MicroPC target
Definition: microop_args.hh:315
gem5::X86ISA::UpcOp::ArgType
MicroPC ArgType
Definition: microop_args.hh:313
gem5::X86ISA::Src2Op::src2
const RegIndex src2
Definition: microop_args.hh:80
cprintf.hh
compiler.hh
gem5::X86ISA::Src2Op::size
const size_t size
Definition: microop_args.hh:81
gem5::X86ISA::SegOp
Definition: microop_args.hh:201
gem5::X86ISA::AddrOp::ArgType::base
GpRegIndex base
Definition: microop_args.hh:349
gem5::X86ISA::Src2Op
Definition: microop_args.hh:78
gem5::X86ISA::SegOp::SegOp
SegOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:206
gem5::X86ISA::Src1Op
Definition: microop_args.hh:65
gem5::X86ISA::AddrOp::size
const size_t size
Definition: microop_args.hh:359
gem5::X86ISA::UpcOp
Definition: microop_args.hh:311
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::InstOperands::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: microop_args.hh:405
gem5::X86ISA::AddrOp::AddrOp
AddrOp(InstType *inst, const ArgType &args)
Definition: microop_args.hh:362
gem5::X86ISA::DataOp
Definition: microop_args.hh:91
gem5::X86ISA::DataOp::DataOp
DataOp(RegIndex _data, size_t _size)
Definition: microop_args.hh:97
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::AddrOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:372
gem5::X86ISA::DataHiOp::DataHiOp
DataHiOp(RegIndex data_hi, size_t _size)
Definition: microop_args.hh:106
gem5::X86ISA::AddrOp::index
const RegIndex index
Definition: microop_args.hh:355
gem5::X86ISA::IntOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:144
gem5::X86ISA::CrOp
Definition: microop_args.hh:170
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::X86ISA::DbgOp::DbgOp
DbgOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:190
gem5::X86ISA::Src1Op::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:69
gem5::X86ISA::Imm8Op::imm8
uint8_t imm8
Definition: microop_args.hh:283
gem5::X86ISA::DataLowOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:113
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::DataOp::size
const size_t size
Definition: microop_args.hh:94
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::AddrOp::ArgType::segment
SegRegIndex segment
Definition: microop_args.hh:351
gem5::X86ISA::Src1Op::src1
const RegIndex src1
Definition: microop_args.hh:67
gem5::X86ISA::CrOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:178
reg_class.hh
gem5::X86ISA::DataOp::data
const RegIndex data
Definition: microop_args.hh:93
gem5::X86ISA::FloatOp::FloatOp
FloatOp(Inst *inst, std::enable_if_t< HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:237
gem5::X86ISA::FloatOp
Definition: microop_args.hh:232
gem5::X86ISA::AddrOp::scale
const uint8_t scale
Definition: microop_args.hh:354
gem5::X86ISA::AddrOp::ArgType::index
GpRegIndex index
Definition: microop_args.hh:348
gem5::X86ISA::DestOp::DestOp
DestOp(RegIndex _dest, InstType *inst)
Definition: microop_args.hh:60
gem5::X86ISA::InstOperands
Definition: microop_args.hh:380
gem5::X86ISA::MiscOp::MiscOp
MiscOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:221
gem5::X86ISA::FoldedOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:162
gem5::X86ISA::CtrlRegIndex
Definition: static_inst.hh:71
gem5::X86ISA::IntOp::IntOp
IntOp(Inst *inst, std::enable_if_t< HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:134
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::X86ISA::MiscOp
Definition: microop_args.hh:216
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::X86ISA::InstOperands::InstOperands
InstOperands(std::index_sequence< I... >, ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, [[maybe_unused]] ArgTuple args, CTorArgs... ctor_args)
Definition: microop_args.hh:386
gem5::X86ISA::SegRegIndex
Definition: static_inst.hh:89
gem5::X86ISA::AddrOp::disp
const uint64_t disp
Definition: microop_args.hh:357
types.hh
gem5::X86ISA::FaultOp
Definition: microop_args.hh:327
gem5::X86ISA::InstOperands< X86MicroopBase >::ArgTuple
std::tuple< typename Operands::ArgType... > ArgTuple
Definition: microop_args.hh:383
gem5::X86ISA::DbgRegIndex
Definition: static_inst.hh:83
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113

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