gem5  v21.1.0.2
microop_args.hh
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27 
28 #ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
29 #define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
30 
31 #include <cstdint>
32 #include <sstream>
33 #include <string>
34 #include <tuple>
35 #include <utility>
36 
38 #include "arch/x86/regs/int.hh"
39 #include "arch/x86/types.hh"
40 #include "base/compiler.hh"
41 #include "base/cprintf.hh"
42 #include "cpu/reg_class.hh"
43 #include "sim/faults.hh"
44 
45 namespace gem5
46 {
47 
48 namespace X86ISA
49 {
50 
51 struct DestOp
52 {
53  const RegIndex dest;
54  const size_t size;
55  RegIndex opIndex() const { return dest; }
56 
57  DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
58 };
59 
60 struct Src1Op
61 {
62  const RegIndex src1;
63  const size_t size;
64  RegIndex opIndex() const { return src1; }
65 
66  Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
67 };
68 
69 struct Src2Op
70 {
71  const RegIndex src2;
72  const size_t size;
73  RegIndex opIndex() const { return src2; }
74 
75  Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
76 };
77 
78 struct DataOp
79 {
80  const RegIndex data;
81  const size_t size;
82  RegIndex opIndex() const { return data; }
83 
84  DataOp(RegIndex _data, size_t _size) : data(_data), size(_size) {}
85 };
86 
87 struct DataHiOp
88 {
90  const size_t size;
91  RegIndex opIndex() const { return dataHi; }
92 
93  DataHiOp(RegIndex data_hi, size_t _size) : dataHi(data_hi), size(_size) {}
94 };
95 
96 struct DataLowOp
97 {
99  const size_t size;
100  RegIndex opIndex() const { return dataLow; }
101 
102  DataLowOp(RegIndex data_low, size_t _size) : dataLow(data_low), size(_size)
103  {}
104 };
105 
106 template <class Base>
107 struct IntOp : public Base
108 {
110 
111  template <class InstType>
112  IntOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
113 
114  void
115  print(std::ostream &os) const
116  {
117  X86StaticInst::printReg(os, RegId(IntRegClass, this->opIndex()),
118  this->size);
119  }
120 };
121 
122 template <class Base>
123 struct FoldedOp : public Base
124 {
126 
127  template <class InstType>
128  FoldedOp(InstType *inst, ArgType idx) :
129  Base(INTREG_FOLDED(idx.index, inst->foldOBit), inst->dataSize)
130  {}
131 
132  void
133  print(std::ostream &os) const
134  {
135  X86StaticInst::printReg(os, RegId(IntRegClass, this->opIndex()),
136  this->size);
137  }
138 };
139 
140 template <class Base>
141 struct CrOp : public Base
142 {
144 
145  template <class InstType>
146  CrOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
147 
148  void
149  print(std::ostream &os) const
150  {
151  ccprintf(os, "cr%d", this->opIndex());
152  }
153 };
154 
155 template <class Base>
156 struct DbgOp : public Base
157 {
159 
160  template <class InstType>
161  DbgOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
162 
163  void
164  print(std::ostream &os) const
165  {
166  ccprintf(os, "dr%d", this->opIndex());
167  }
168 
169 };
170 
171 template <class Base>
172 struct SegOp : public Base
173 {
175 
176  template <class InstType>
177  SegOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
178 
179  void
180  print(std::ostream &os) const
181  {
182  X86StaticInst::printSegment(os, this->opIndex());
183  }
184 };
185 
186 template <class Base>
187 struct MiscOp : public Base
188 {
190 
191  template <class InstType>
192  MiscOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
193 
194  void
195  print(std::ostream &os) const
196  {
197  X86StaticInst::printReg(os, RegId(MiscRegClass, this->opIndex()),
198  this->size);
199  }
200 };
201 
202 template <class Base>
203 struct FloatOp : public Base
204 {
206 
207  template <class InstType>
208  FloatOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
209 
210  void
211  print(std::ostream &os) const
212  {
213  X86StaticInst::printReg(os, RegId(FloatRegClass, this->opIndex()),
214  this->size);
215  }
216 };
217 
225 
233 
237 
242 
243 struct Imm8Op
244 {
245  using ArgType = uint8_t;
246 
247  uint8_t imm8;
248 
249  template <class InstType>
250  Imm8Op(InstType *inst, ArgType _imm8) : imm8(_imm8) {}
251 
252  void
253  print(std::ostream &os) const
254  {
255  ccprintf(os, "%#x", imm8);
256  }
257 };
258 
259 struct Imm64Op
260 {
261  using ArgType = uint64_t;
262 
263  uint64_t imm64;
264 
265  template <class InstType>
266  Imm64Op(InstType *inst, ArgType _imm64) : imm64(_imm64) {}
267 
268  void
269  print(std::ostream &os) const
270  {
271  ccprintf(os, "%#x", imm64);
272  }
273 };
274 
275 struct UpcOp
276 {
277  using ArgType = MicroPC;
278 
280 
281  template <class InstType>
282  UpcOp(InstType *inst, ArgType _target) : target(_target) {}
283 
284  void
285  print(std::ostream &os) const
286  {
287  ccprintf(os, "%#x", target);
288  }
289 };
290 
291 struct FaultOp
292 {
293  using ArgType = Fault;
294 
296 
297  template <class InstType>
298  FaultOp(InstType *inst, ArgType _fault) : fault(_fault) {}
299 
300  void
301  print(std::ostream &os) const
302  {
303  ccprintf(os, fault ? fault->name() : "NoFault");
304  }
305 };
306 
307 struct AddrOp
308 {
309  struct ArgType
310  {
311  uint8_t scale;
314  uint64_t disp;
316  };
317 
318  const uint8_t scale;
320  const RegIndex base;
321  const uint64_t disp;
322  const uint8_t segment;
323  const size_t size;
324 
325  template <class InstType>
326  AddrOp(InstType *inst, const ArgType &args) : scale(args.scale),
327  index(INTREG_FOLDED(args.index.index, inst->foldABit)),
328  base(INTREG_FOLDED(args.base.index, inst->foldABit)),
329  disp(args.disp), segment(args.segment.index),
330  size(inst->addressSize)
331  {
332  assert(segment < NUM_SEGMENTREGS);
333  }
334 
335  void
336  print(std::ostream &os) const
337  {
339  os, segment, scale, index, base, disp, size, false);
340  }
341 };
342 
343 template <typename Base, typename ...Operands>
344 class InstOperands : public Base, public Operands...
345 {
346  private:
347  using ArgTuple = std::tuple<typename Operands::ArgType...>;
348 
349  template <std::size_t ...I, typename ...CTorArgs>
350  InstOperands(std::index_sequence<I...>, ExtMachInst mach_inst,
351  const char *mnem, const char *inst_mnem, uint64_t set_flags,
352  OpClass op_class, GEM5_VAR_USED ArgTuple args,
353  CTorArgs... ctor_args) :
354  Base(mach_inst, mnem, inst_mnem, set_flags, op_class, ctor_args...),
355  Operands(this, std::get<I>(args))...
356  {}
357 
358  protected:
359  template <typename ...CTorArgs>
360  InstOperands(ExtMachInst mach_inst, const char *mnem,
361  const char *inst_mnem, uint64_t set_flags, OpClass op_class,
362  ArgTuple args, CTorArgs... ctor_args) :
363  InstOperands(std::make_index_sequence<sizeof...(Operands)>{},
364  mach_inst, mnem, inst_mnem, set_flags, op_class,
365  std::move(args), ctor_args...)
366  {}
367 
368  std::string
370  const loader::SymbolTable *symtab) const override
371  {
372  std::stringstream response;
373  Base::printMnemonic(response, this->instMnem, this->mnemonic);
374  int count = 0;
375  GEM5_FOR_EACH_IN_PACK(ccprintf(response, count++ ? ", " : ""),
376  Operands::print(response));
377  return response.str();
378  }
379 };
380 
381 } // namespace X86ISA
382 } // namespace gem5
383 
384 #endif //__ARCH_X86_INSTS_MICROOP_ARGS_HH__
gem5::X86ISA::UpcOp::UpcOp
UpcOp(InstType *inst, ArgType _target)
Definition: microop_args.hh:282
gem5::X86ISA::FpRegIndex
Definition: static_inst.hh:63
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::UpcOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:285
gem5::X86ISA::FloatOp::FloatOp
FloatOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:208
gem5::X86ISA::MiscOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:195
gem5::X86ISA::FaultOp::FaultOp
FaultOp(InstType *inst, ArgType _fault)
Definition: microop_args.hh:298
gem5::X86ISA::DestOp
Definition: microop_args.hh:51
gem5::X86ISA::Src1Op::Src1Op
Src1Op(RegIndex _src1, size_t _size)
Definition: microop_args.hh:66
gem5::X86ISA::Imm64Op::ArgType
uint64_t ArgType
Definition: microop_args.hh:261
gem5::X86ISA::FoldedOp::FoldedOp
FoldedOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:128
gem5::X86ISA::Imm8Op::Imm8Op
Imm8Op(InstType *inst, ArgType _imm8)
Definition: microop_args.hh:250
gem5::X86ISA::GpRegIndex
Classes for register indices passed to instruction constructors.
Definition: static_inst.hh:57
gem5::X86ISA::Imm8Op::print
void print(std::ostream &os) const
Definition: microop_args.hh:253
gem5::X86ISA::DataHiOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:91
gem5::X86ISA::FaultOp::ArgType
Fault ArgType
Definition: microop_args.hh:293
gem5::X86ISA::DestOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:55
gem5::X86ISA::Imm8Op::ArgType
uint8_t ArgType
Definition: microop_args.hh:245
gem5::X86ISA::Imm64Op::print
void print(std::ostream &os) const
Definition: microop_args.hh:269
gem5::X86ISA::DestOp::DestOp
DestOp(RegIndex _dest, size_t _size)
Definition: microop_args.hh:57
gem5::X86ISA::DataHiOp
Definition: microop_args.hh:87
gem5::X86ISA::DataLowOp::size
const size_t size
Definition: microop_args.hh:99
gem5::X86ISA::Imm8Op
Definition: microop_args.hh:243
static_inst.hh
gem5::X86ISA::DbgOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:164
gem5::X86ISA::DataHiOp::size
const size_t size
Definition: microop_args.hh:90
gem5::X86ISA::CrRegIndex
Definition: static_inst.hh:75
gem5::X86ISA::Src2Op::Src2Op
Src2Op(RegIndex _src2, size_t _size)
Definition: microop_args.hh:75
gem5::X86ISA::Imm64Op::Imm64Op
Imm64Op(InstType *inst, ArgType _imm64)
Definition: microop_args.hh:266
gem5::X86ISA::FaultOp::fault
Fault fault
Definition: microop_args.hh:295
gem5::X86ISA::AddrOp::ArgType
Definition: microop_args.hh:309
gem5::X86ISA::DataLowOp
Definition: microop_args.hh:96
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::X86ISA::Imm64Op::imm64
uint64_t imm64
Definition: microop_args.hh:263
gem5::X86ISA::DataLowOp::DataLowOp
DataLowOp(RegIndex data_low, size_t _size)
Definition: microop_args.hh:102
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::X86ISA::InstOperands::InstOperands
InstOperands(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, ArgTuple args, CTorArgs... ctor_args)
Definition: microop_args.hh:360
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:257
gem5::X86ISA::Src1Op::size
const size_t size
Definition: microop_args.hh:63
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::INTREG_FOLDED
static IntRegIndex INTREG_FOLDED(int index, int foldBit)
Definition: int.hh:181
gem5::X86ISA::FaultOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:301
gem5::X86ISA::CrOp::CrOp
CrOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:146
gem5::X86ISA::IntOp
Definition: microop_args.hh:107
gem5::X86ISA::AddrOp::base
const RegIndex base
Definition: microop_args.hh:320
faults.hh
gem5::X86ISA::AddrOp
Definition: microop_args.hh:307
gem5::X86ISA::AddrOp::ArgType::disp
uint64_t disp
Definition: microop_args.hh:314
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::X86ISA::FloatOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:211
gem5::X86ISA::AddrOp::ArgType::scale
uint8_t scale
Definition: microop_args.hh:311
gem5::X86ISA::DbgOp
Definition: microop_args.hh:156
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:76
gem5::X86ISA::DestOp::dest
const RegIndex dest
Definition: microop_args.hh:53
gem5::X86ISA::DestOp::size
const size_t size
Definition: microop_args.hh:54
gem5::X86ISA::Src2Op::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:73
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::X86ISA::DataHiOp::dataHi
const RegIndex dataHi
Definition: microop_args.hh:89
gem5::X86ISA::SegOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:180
gem5::X86ISA::NUM_SEGMENTREGS
@ NUM_SEGMENTREGS
Definition: segment.hh:65
gem5::X86ISA::DataLowOp::dataLow
const RegIndex dataLow
Definition: microop_args.hh:98
gem5::X86ISA::FoldedOp
Definition: microop_args.hh:123
int.hh
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::X86ISA::AddrOp::segment
const uint8_t segment
Definition: microop_args.hh:322
gem5::X86ISA::Imm64Op
Definition: microop_args.hh:259
gem5::X86ISA::DataOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:82
gem5::X86ISA::UpcOp::target
MicroPC target
Definition: microop_args.hh:279
gem5::X86ISA::UpcOp::ArgType
MicroPC ArgType
Definition: microop_args.hh:277
gem5::X86ISA::Src2Op::src2
const RegIndex src2
Definition: microop_args.hh:71
cprintf.hh
compiler.hh
gem5::X86ISA::Src2Op::size
const size_t size
Definition: microop_args.hh:72
gem5::X86ISA::SegOp
Definition: microop_args.hh:172
gem5::X86ISA::AddrOp::ArgType::base
GpRegIndex base
Definition: microop_args.hh:313
gem5::X86ISA::Src2Op
Definition: microop_args.hh:69
gem5::X86ISA::SegOp::SegOp
SegOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:177
gem5::X86ISA::Src1Op
Definition: microop_args.hh:60
gem5::X86ISA::AddrOp::size
const size_t size
Definition: microop_args.hh:323
gem5::X86ISA::UpcOp
Definition: microop_args.hh:275
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::InstOperands::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: microop_args.hh:369
gem5::X86ISA::AddrOp::AddrOp
AddrOp(InstType *inst, const ArgType &args)
Definition: microop_args.hh:326
gem5::X86ISA::DataOp
Definition: microop_args.hh:78
gem5::X86ISA::DataOp::DataOp
DataOp(RegIndex _data, size_t _size)
Definition: microop_args.hh:84
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::AddrOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:336
gem5::X86ISA::DataHiOp::DataHiOp
DataHiOp(RegIndex data_hi, size_t _size)
Definition: microop_args.hh:93
gem5::X86ISA::AddrOp::index
const RegIndex index
Definition: microop_args.hh:319
gem5::X86ISA::IntOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:115
gem5::X86ISA::CrOp
Definition: microop_args.hh:141
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::DbgOp::DbgOp
DbgOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:161
gem5::X86ISA::Src1Op::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:64
gem5::X86ISA::Imm8Op::imm8
uint8_t imm8
Definition: microop_args.hh:247
gem5::X86ISA::DataLowOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:100
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::DataOp::size
const size_t size
Definition: microop_args.hh:81
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::AddrOp::ArgType::segment
SegRegIndex segment
Definition: microop_args.hh:315
gem5::X86ISA::Src1Op::src1
const RegIndex src1
Definition: microop_args.hh:62
gem5::X86ISA::CrOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:149
reg_class.hh
gem5::X86ISA::DataOp::data
const RegIndex data
Definition: microop_args.hh:80
gem5::X86ISA::FloatOp
Definition: microop_args.hh:203
gem5::X86ISA::InstOperands::InstOperands
InstOperands(std::index_sequence< I... >, ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, GEM5_VAR_USED ArgTuple args, CTorArgs... ctor_args)
Definition: microop_args.hh:350
gem5::X86ISA::AddrOp::scale
const uint8_t scale
Definition: microop_args.hh:318
gem5::X86ISA::AddrOp::ArgType::index
GpRegIndex index
Definition: microop_args.hh:312
gem5::X86ISA::InstOperands
Definition: microop_args.hh:344
gem5::X86ISA::IntOp::IntOp
IntOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:112
gem5::X86ISA::MiscOp::MiscOp
MiscOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:192
gem5::X86ISA::FoldedOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:133
gem5::X86ISA::CtrlRegIndex
Definition: static_inst.hh:69
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::X86ISA::MiscOp
Definition: microop_args.hh:187
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::SegRegIndex
Definition: static_inst.hh:87
gem5::X86ISA::AddrOp::disp
const uint64_t disp
Definition: microop_args.hh:321
types.hh
gem5::X86ISA::FaultOp
Definition: microop_args.hh:291
gem5::X86ISA::InstOperands< X86MicroopBase >::ArgTuple
std::tuple< typename Operands::ArgType... > ArgTuple
Definition: microop_args.hh:347
gem5::X86ISA::DbgRegIndex
Definition: static_inst.hh:81
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88

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