gem5  v22.0.0.2
microop_args.hh
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27 
28 #ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
29 #define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
30 
31 #include <cstdint>
32 #include <sstream>
33 #include <string>
34 #include <tuple>
35 #include <type_traits>
36 #include <utility>
37 
39 #include "arch/x86/regs/int.hh"
40 #include "arch/x86/regs/segment.hh"
41 #include "arch/x86/types.hh"
42 #include "base/compiler.hh"
43 #include "base/cprintf.hh"
44 #include "cpu/reg_class.hh"
45 #include "sim/faults.hh"
46 
47 namespace gem5
48 {
49 
50 namespace X86ISA
51 {
52 
53 struct DestOp
54 {
55  const RegIndex dest;
56  const size_t size;
57  RegIndex opIndex() const { return dest; }
58 
59  DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
60  template <class InstType>
61  DestOp(RegIndex _dest, InstType *inst) : dest(_dest),
62  size(inst->getDestSize())
63  {}
64 };
65 
66 struct Src1Op
67 {
68  const RegIndex src1;
69  const size_t size;
70  RegIndex opIndex() const { return src1; }
71 
72  Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
73  template <class InstType>
74  Src1Op(RegIndex _src1, InstType *inst) : src1(_src1),
75  size(inst->getSrcSize())
76  {}
77 };
78 
79 struct Src2Op
80 {
81  const RegIndex src2;
82  const size_t size;
83  RegIndex opIndex() const { return src2; }
84 
85  Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
86  template <class InstType>
87  Src2Op(RegIndex _src2, InstType *inst) : src2(_src2),
88  size(inst->getSrcSize())
89  {}
90 };
91 
92 struct DataOp
93 {
94  const RegIndex data;
95  const size_t size;
96  RegIndex opIndex() const { return data; }
97 
98  DataOp(RegIndex _data, size_t _size) : data(_data), size(_size) {}
99 };
100 
101 struct DataHiOp
102 {
104  const size_t size;
105  RegIndex opIndex() const { return dataHi; }
106 
107  DataHiOp(RegIndex data_hi, size_t _size) : dataHi(data_hi), size(_size) {}
108 };
109 
110 struct DataLowOp
111 {
113  const size_t size;
114  RegIndex opIndex() const { return dataLow; }
115 
116  DataLowOp(RegIndex data_low, size_t _size) : dataLow(data_low), size(_size)
117  {}
118 };
119 
120 template <class T, class Enabled=void>
121 struct HasDataSize : public std::false_type {};
122 
123 template <class T>
124 struct HasDataSize<T, decltype((void)&T::dataSize)> : public std::true_type {};
125 
126 template <class T>
128 
129 template <class Base>
130 struct IntOp : public Base
131 {
133 
134  template <class Inst>
135  IntOp(Inst *inst, std::enable_if_t<HasDataSizeV<Inst>, ArgType> idx) :
136  Base(idx.index, inst->dataSize)
137  {}
138 
139  template <class Inst>
140  IntOp(Inst *inst, std::enable_if_t<!HasDataSizeV<Inst>, ArgType> idx) :
141  Base(idx.index, inst)
142  {}
143 
144  void
145  print(std::ostream &os) const
146  {
147  X86StaticInst::printReg(os, RegId(IntRegClass, this->opIndex()),
148  this->size);
149  }
150 };
151 
152 template <class Base>
153 struct FoldedOp : public Base
154 {
156 
157  template <class InstType>
158  FoldedOp(InstType *inst, ArgType idx) :
159  Base(intRegFolded(idx.index, inst->foldOBit), inst->dataSize)
160  {}
161 
162  void
163  print(std::ostream &os) const
164  {
165  X86StaticInst::printReg(os, RegId(IntRegClass, this->opIndex()),
166  this->size);
167  }
168 };
169 
170 template <class Base>
171 struct CrOp : public Base
172 {
174 
175  template <class InstType>
176  CrOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
177 
178  void
179  print(std::ostream &os) const
180  {
181  ccprintf(os, "cr%d", this->opIndex());
182  }
183 };
184 
185 template <class Base>
186 struct DbgOp : public Base
187 {
189 
190  template <class InstType>
191  DbgOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
192 
193  void
194  print(std::ostream &os) const
195  {
196  ccprintf(os, "dr%d", this->opIndex());
197  }
198 
199 };
200 
201 template <class Base>
202 struct SegOp : public Base
203 {
205 
206  template <class InstType>
207  SegOp(InstType *inst, ArgType idx) : Base(idx.index, 0) {}
208 
209  void
210  print(std::ostream &os) const
211  {
212  X86StaticInst::printSegment(os, this->opIndex());
213  }
214 };
215 
216 template <class Base>
217 struct MiscOp : public Base
218 {
220 
221  template <class InstType>
222  MiscOp(InstType *inst, ArgType idx) : Base(idx.index, inst->dataSize) {}
223 
224  void
225  print(std::ostream &os) const
226  {
227  X86StaticInst::printReg(os, RegId(MiscRegClass, this->opIndex()),
228  this->size);
229  }
230 };
231 
232 template <class Base>
233 struct FloatOp : public Base
234 {
236 
237  template <class Inst>
238  FloatOp(Inst *inst, std::enable_if_t<HasDataSizeV<Inst>, ArgType> idx) :
239  Base(idx.index, inst->dataSize)
240  {}
241 
242  template <class Inst>
243  FloatOp(Inst *inst, std::enable_if_t<!HasDataSizeV<Inst>, ArgType> idx) :
244  Base(idx.index, inst)
245  {}
246 
247  void
248  print(std::ostream &os) const
249  {
250  X86StaticInst::printReg(os, RegId(FloatRegClass, this->opIndex()),
251  this->size);
252  }
253 };
254 
262 
270 
274 
279 
280 struct Imm8Op
281 {
282  using ArgType = uint8_t;
283 
284  uint8_t imm8;
285 
286  template <class InstType>
287  Imm8Op(InstType *inst, ArgType _imm8) : imm8(_imm8) {}
288 
289  void
290  print(std::ostream &os) const
291  {
292  ccprintf(os, "%#x", imm8);
293  }
294 };
295 
296 struct Imm64Op
297 {
298  using ArgType = uint64_t;
299 
300  uint64_t imm64;
301 
302  template <class InstType>
303  Imm64Op(InstType *inst, ArgType _imm64) : imm64(_imm64) {}
304 
305  void
306  print(std::ostream &os) const
307  {
308  ccprintf(os, "%#x", imm64);
309  }
310 };
311 
312 struct UpcOp
313 {
314  using ArgType = MicroPC;
315 
317 
318  template <class InstType>
319  UpcOp(InstType *inst, ArgType _target) : target(_target) {}
320 
321  void
322  print(std::ostream &os) const
323  {
324  ccprintf(os, "%#x", target);
325  }
326 };
327 
328 struct FaultOp
329 {
330  using ArgType = Fault;
331 
333 
334  template <class InstType>
335  FaultOp(InstType *inst, ArgType _fault) : fault(_fault) {}
336 
337  void
338  print(std::ostream &os) const
339  {
340  ccprintf(os, fault ? fault->name() : "NoFault");
341  }
342 };
343 
344 struct AddrOp
345 {
346  struct ArgType
347  {
348  uint8_t scale;
351  uint64_t disp;
353  };
354 
355  const uint8_t scale;
357  const RegIndex base;
358  const uint64_t disp;
359  const uint8_t segment;
360  const size_t size;
361 
362  template <class InstType>
363  AddrOp(InstType *inst, const ArgType &args) : scale(args.scale),
364  index(intRegFolded(args.index.index, inst->foldABit)),
365  base(intRegFolded(args.base.index, inst->foldABit)),
366  disp(args.disp), segment(args.segment.index),
367  size(inst->addressSize)
368  {
369  assert(segment < segment_idx::NumIdxs);
370  }
371 
372  void
373  print(std::ostream &os) const
374  {
376  os, segment, scale, index, base, disp, size, false);
377  }
378 };
379 
380 template <typename Base, typename ...Operands>
381 class InstOperands : public Base, public Operands...
382 {
383  private:
384  using ArgTuple = std::tuple<typename Operands::ArgType...>;
385 
386  template <std::size_t ...I, typename ...CTorArgs>
387  InstOperands(std::index_sequence<I...>, ExtMachInst mach_inst,
388  const char *mnem, const char *inst_mnem, uint64_t set_flags,
389  OpClass op_class, [[maybe_unused]] ArgTuple args,
390  CTorArgs... ctor_args) :
391  Base(mach_inst, mnem, inst_mnem, set_flags, op_class, ctor_args...),
392  Operands(this, std::get<I>(args))...
393  {}
394 
395  protected:
396  template <typename ...CTorArgs>
397  InstOperands(ExtMachInst mach_inst, const char *mnem,
398  const char *inst_mnem, uint64_t set_flags, OpClass op_class,
399  ArgTuple args, CTorArgs... ctor_args) :
400  InstOperands(std::make_index_sequence<sizeof...(Operands)>{},
401  mach_inst, mnem, inst_mnem, set_flags, op_class,
402  std::move(args), ctor_args...)
403  {}
404 
405  std::string
407  const loader::SymbolTable *symtab) const override
408  {
409  std::stringstream response;
410  Base::printMnemonic(response, this->instMnem, this->mnemonic);
411  int count = 0;
412  GEM5_FOR_EACH_IN_PACK(ccprintf(response, count++ ? ", " : ""),
413  Operands::print(response));
414  return response.str();
415  }
416 };
417 
418 } // namespace X86ISA
419 } // namespace gem5
420 
421 #endif //__ARCH_X86_INSTS_MICROOP_ARGS_HH__
gem5::X86ISA::UpcOp::UpcOp
UpcOp(InstType *inst, ArgType _target)
Definition: microop_args.hh:319
gem5::X86ISA::FpRegIndex
Definition: static_inst.hh:66
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
gem5::X86ISA::UpcOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:322
gem5::X86ISA::MiscOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:225
gem5::X86ISA::FaultOp::FaultOp
FaultOp(InstType *inst, ArgType _fault)
Definition: microop_args.hh:335
gem5::X86ISA::DestOp
Definition: microop_args.hh:53
gem5::X86ISA::Src1Op::Src1Op
Src1Op(RegIndex _src1, size_t _size)
Definition: microop_args.hh:72
gem5::X86ISA::Imm64Op::ArgType
uint64_t ArgType
Definition: microop_args.hh:298
gem5::X86ISA::FoldedOp::FoldedOp
FoldedOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:158
gem5::X86ISA::Imm8Op::Imm8Op
Imm8Op(InstType *inst, ArgType _imm8)
Definition: microop_args.hh:287
gem5::X86ISA::GpRegIndex
Classes for register indices passed to instruction constructors.
Definition: static_inst.hh:60
gem5::X86ISA::Imm8Op::print
void print(std::ostream &os) const
Definition: microop_args.hh:290
gem5::X86ISA::DataHiOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:105
gem5::X86ISA::FaultOp::ArgType
Fault ArgType
Definition: microop_args.hh:330
gem5::X86ISA::DestOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:57
gem5::X86ISA::Imm8Op::ArgType
uint8_t ArgType
Definition: microop_args.hh:282
gem5::X86ISA::Imm64Op::print
void print(std::ostream &os) const
Definition: microop_args.hh:306
gem5::X86ISA::DestOp::DestOp
DestOp(RegIndex _dest, size_t _size)
Definition: microop_args.hh:59
gem5::X86ISA::DataHiOp
Definition: microop_args.hh:101
gem5::X86ISA::DataLowOp::size
const size_t size
Definition: microop_args.hh:113
gem5::X86ISA::Imm8Op
Definition: microop_args.hh:280
static_inst.hh
gem5::X86ISA::DbgOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:194
gem5::X86ISA::DataHiOp::size
const size_t size
Definition: microop_args.hh:104
gem5::X86ISA::CrRegIndex
Definition: static_inst.hh:78
gem5::X86ISA::Src2Op::Src2Op
Src2Op(RegIndex _src2, size_t _size)
Definition: microop_args.hh:85
gem5::X86ISA::Imm64Op::Imm64Op
Imm64Op(InstType *inst, ArgType _imm64)
Definition: microop_args.hh:303
gem5::X86ISA::FaultOp::fault
Fault fault
Definition: microop_args.hh:332
gem5::X86ISA::AddrOp::ArgType
Definition: microop_args.hh:346
gem5::X86ISA::DataLowOp
Definition: microop_args.hh:110
gem5::X86ISA::Imm64Op::imm64
uint64_t imm64
Definition: microop_args.hh:300
gem5::X86ISA::Src1Op::Src1Op
Src1Op(RegIndex _src1, InstType *inst)
Definition: microop_args.hh:74
gem5::X86ISA::DataLowOp::DataLowOp
DataLowOp(RegIndex data_low, size_t _size)
Definition: microop_args.hh:116
gem5::X86ISA::InstOperands::InstOperands
InstOperands(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, ArgTuple args, CTorArgs... ctor_args)
Definition: microop_args.hh:397
gem5::X86ISA::X86StaticInst::printMem
static void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip)
Definition: static_inst.cc:258
gem5::X86ISA::Src1Op::size
const size_t size
Definition: microop_args.hh:69
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::FaultOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:338
gem5::X86ISA::CrOp::CrOp
CrOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:176
gem5::X86ISA::IntOp
Definition: microop_args.hh:130
gem5::X86ISA::AddrOp::base
const RegIndex base
Definition: microop_args.hh:357
gem5::X86ISA::Src2Op::Src2Op
Src2Op(RegIndex _src2, InstType *inst)
Definition: microop_args.hh:87
faults.hh
gem5::X86ISA::AddrOp
Definition: microop_args.hh:344
gem5::X86ISA::AddrOp::ArgType::disp
uint64_t disp
Definition: microop_args.hh:351
gem5::X86ISA::FloatOp::FloatOp
FloatOp(Inst *inst, std::enable_if_t<!HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:243
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::X86ISA::FloatOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:248
gem5::X86ISA::AddrOp::ArgType::scale
uint8_t scale
Definition: microop_args.hh:348
gem5::X86ISA::IntOp::IntOp
IntOp(Inst *inst, std::enable_if_t<!HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:140
gem5::X86ISA::DbgOp
Definition: microop_args.hh:186
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::X86ISA::HasDataSize
Definition: microop_args.hh:121
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
gem5::X86ISA::DestOp::dest
const RegIndex dest
Definition: microop_args.hh:55
gem5::X86ISA::DestOp::size
const size_t size
Definition: microop_args.hh:56
gem5::X86ISA::Src2Op::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:83
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::X86ISA::DataHiOp::dataHi
const RegIndex dataHi
Definition: microop_args.hh:103
gem5::X86ISA::SegOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:210
gem5::X86ISA::DataLowOp::dataLow
const RegIndex dataLow
Definition: microop_args.hh:112
gem5::X86ISA::FoldedOp
Definition: microop_args.hh:153
int.hh
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::X86ISA::AddrOp::segment
const uint8_t segment
Definition: microop_args.hh:359
gem5::X86ISA::Imm64Op
Definition: microop_args.hh:296
segment.hh
gem5::X86ISA::HasDataSizeV
constexpr bool HasDataSizeV
Definition: microop_args.hh:127
gem5::X86ISA::DataOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:96
gem5::X86ISA::UpcOp::target
MicroPC target
Definition: microop_args.hh:316
gem5::X86ISA::UpcOp::ArgType
MicroPC ArgType
Definition: microop_args.hh:314
gem5::X86ISA::Src2Op::src2
const RegIndex src2
Definition: microop_args.hh:81
gem5::X86ISA::intRegFolded
static constexpr RegId intRegFolded(RegIndex index, RegIndex foldBit)
Definition: int.hh:158
cprintf.hh
compiler.hh
gem5::X86ISA::Src2Op::size
const size_t size
Definition: microop_args.hh:82
gem5::X86ISA::SegOp
Definition: microop_args.hh:202
gem5::X86ISA::AddrOp::ArgType::base
GpRegIndex base
Definition: microop_args.hh:350
gem5::X86ISA::Src2Op
Definition: microop_args.hh:79
gem5::X86ISA::SegOp::SegOp
SegOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:207
gem5::X86ISA::Src1Op
Definition: microop_args.hh:66
gem5::X86ISA::AddrOp::size
const size_t size
Definition: microop_args.hh:360
gem5::X86ISA::UpcOp
Definition: microop_args.hh:312
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::InstOperands::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Definition: microop_args.hh:406
gem5::X86ISA::AddrOp::AddrOp
AddrOp(InstType *inst, const ArgType &args)
Definition: microop_args.hh:363
gem5::X86ISA::DataOp
Definition: microop_args.hh:92
gem5::X86ISA::DataOp::DataOp
DataOp(RegIndex _data, size_t _size)
Definition: microop_args.hh:98
gem5::X86ISA::X86StaticInst::printReg
static void printReg(std::ostream &os, RegId reg, int size)
Definition: static_inst.cc:142
gem5::X86ISA::AddrOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:373
gem5::X86ISA::DataHiOp::DataHiOp
DataHiOp(RegIndex data_hi, size_t _size)
Definition: microop_args.hh:107
gem5::X86ISA::AddrOp::index
const RegIndex index
Definition: microop_args.hh:356
gem5::X86ISA::IntOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:145
gem5::X86ISA::CrOp
Definition: microop_args.hh:171
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::X86ISA::DbgOp::DbgOp
DbgOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:191
gem5::X86ISA::Src1Op::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:70
gem5::X86ISA::Imm8Op::imm8
uint8_t imm8
Definition: microop_args.hh:284
gem5::X86ISA::DataLowOp::opIndex
RegIndex opIndex() const
Definition: microop_args.hh:114
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
std
Overload hash function for BasicBlockRange type.
Definition: misc.hh:2388
gem5::X86ISA::X86StaticInst::printSegment
static void printSegment(std::ostream &os, int segment)
Definition: static_inst.cc:63
gem5::X86ISA::DataOp::size
const size_t size
Definition: microop_args.hh:95
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::AddrOp::ArgType::segment
SegRegIndex segment
Definition: microop_args.hh:352
gem5::X86ISA::Src1Op::src1
const RegIndex src1
Definition: microop_args.hh:68
gem5::X86ISA::CrOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:179
reg_class.hh
gem5::X86ISA::DataOp::data
const RegIndex data
Definition: microop_args.hh:94
gem5::X86ISA::FloatOp::FloatOp
FloatOp(Inst *inst, std::enable_if_t< HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:238
gem5::X86ISA::FloatOp
Definition: microop_args.hh:233
gem5::X86ISA::AddrOp::scale
const uint8_t scale
Definition: microop_args.hh:355
gem5::X86ISA::AddrOp::ArgType::index
GpRegIndex index
Definition: microop_args.hh:349
gem5::X86ISA::DestOp::DestOp
DestOp(RegIndex _dest, InstType *inst)
Definition: microop_args.hh:61
gem5::X86ISA::InstOperands
Definition: microop_args.hh:381
gem5::X86ISA::MiscOp::MiscOp
MiscOp(InstType *inst, ArgType idx)
Definition: microop_args.hh:222
gem5::X86ISA::FoldedOp::print
void print(std::ostream &os) const
Definition: microop_args.hh:163
gem5::X86ISA::CtrlRegIndex
Definition: static_inst.hh:72
gem5::X86ISA::IntOp::IntOp
IntOp(Inst *inst, std::enable_if_t< HasDataSizeV< Inst >, ArgType > idx)
Definition: microop_args.hh:135
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::X86ISA::MiscOp
Definition: microop_args.hh:217
gem5::X86ISA::segment_idx::NumIdxs
@ NumIdxs
Definition: segment.hh:67
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::InstOperands::InstOperands
InstOperands(std::index_sequence< I... >, ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, [[maybe_unused]] ArgTuple args, CTorArgs... ctor_args)
Definition: microop_args.hh:387
gem5::X86ISA::SegRegIndex
Definition: static_inst.hh:90
gem5::X86ISA::AddrOp::disp
const uint64_t disp
Definition: microop_args.hh:358
types.hh
gem5::X86ISA::FaultOp
Definition: microop_args.hh:328
gem5::X86ISA::InstOperands< X86MicroopBase >::ArgTuple
std::tuple< typename Operands::ArgType... > ArgTuple
Definition: microop_args.hh:384
gem5::X86ISA::DbgRegIndex
Definition: static_inst.hh:84
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126

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