gem5  v21.1.0.2
microop.hh
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37 
38 #ifndef __ARCH_X86_INSTS_MICROOP_HH__
39 #define __ARCH_X86_INSTS_MICROOP_HH__
40 
42 #include "base/compiler.hh"
43 
44 namespace gem5
45 {
46 
47 namespace X86ISA
48 {
49 
50 GEM5_DEPRECATED_NAMESPACE(ConditionTests, condition_tests);
51 namespace condition_tests
52 {
53 
55 {
58  ECF,
59  EZF,
65  OF,
66  CF,
67  ZF,
69  SF,
70  PF,
73 
91 };
92 
93 }
94 
95 //A class which is the base of all x86 micro ops. It provides a function to
96 //set necessary flags appropriately.
98 {
99  protected:
100  const char * instMnem;
101  uint8_t opSize;
102  uint8_t addrSize;
103 
105  const char *mnem, const char *_instMnem,
106  uint64_t setFlags, OpClass __opClass) :
107  X86ISA::X86StaticInst(mnem, _machInst, __opClass),
108  instMnem(_instMnem)
109  {
110  const int ChunkSize = sizeof(unsigned long);
111  const int Chunks = sizeof(setFlags) / ChunkSize;
112 
113  // Since the bitset constructor can only handle unsigned long
114  // sized chunks, feed it those one at a time while oring them in.
115  for (int i = 0; i < Chunks; i++) {
116  unsigned shift = i * ChunkSize * 8;
117  flags |= (std::bitset<Num_Flags>(setFlags >> shift) << shift);
118  }
119  }
120 
121  std::string
123  const loader::SymbolTable *symtab) const override
124  {
125  std::stringstream ss;
126 
127  ccprintf(ss, "\t%s.%s", instMnem, mnemonic);
128 
129  return ss.str();
130  }
131 
132  bool checkCondition(uint64_t flags, int condition) const;
133 
134  void
135  advancePC(PCState &pcState) const override
136  {
137  if (flags[IsLastMicroop])
138  pcState.uEnd();
139  else
140  pcState.uAdvance();
141  }
142 
143  PCState branchTarget(const PCState &branchPC) const override;
144 
145  // Explicitly import the otherwise hidden branchTarget.
147 };
148 
150 {
151  protected:
152  uint8_t cc;
153 
154  public:
155  MicroCondBase(ExtMachInst mach_inst, const char *mnem,
156  const char *inst_mnem, uint64_t set_flags, OpClass op_class,
157  uint8_t _cc) :
158  X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, op_class),
159  cc(_cc)
160  {}
161 };
162 
163 } // namespace X86ISA
164 } // namespace gem5
165 
166 #endif //__ARCH_X86_INSTS_MICROOP_HH__
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::condition_tests::ECF
@ ECF
Definition: microop.hh:58
gem5::X86ISA::condition_tests::NotEZF
@ NotEZF
Definition: microop.hh:77
static_inst.hh
gem5::X86ISA::condition_tests::PF
@ PF
Definition: microop.hh:70
gem5::X86ISA::condition_tests::MSTRC
@ MSTRC
Definition: microop.hh:63
gem5::X86ISA::condition_tests::NotECF
@ NotECF
Definition: microop.hh:76
gem5::X86ISA::condition_tests::STRnZnEZF
@ STRnZnEZF
Definition: microop.hh:82
gem5::X86ISA::condition_tests::NotFalse
@ NotFalse
Definition: microop.hh:57
gem5::X86ISA::X86MicroopBase::branchTarget
PCState branchTarget(const PCState &branchPC) const override
Definition: microop.cc:126
gem5::X86ISA::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(IntelMP, intelmp)
gem5::X86ISA::condition_tests::MSTRZ
@ MSTRZ
Definition: microop.hh:61
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::X86ISA::X86MicroopBase::addrSize
uint8_t addrSize
Definition: microop.hh:102
gem5::X86ISA::X86MicroopBase::opSize
uint8_t opSize
Definition: microop.hh:101
gem5::X86ISA::PCState::uEnd
void uEnd()
Definition: pcstate.hh:93
gem5::X86ISA::X86MicroopBase::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: microop.hh:122
gem5::X86ISA::condition_tests::OF
@ OF
Definition: microop.hh:65
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::X86ISA::condition_tests::NotPF
@ NotPF
Definition: microop.hh:88
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::X86ISA::condition_tests::CvZF
@ CvZF
Definition: microop.hh:68
gem5::X86ISA::condition_tests::NotZF
@ NotZF
Definition: microop.hh:85
gem5::ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:117
gem5::X86ISA::X86MicroopBase::checkCondition
bool checkCondition(uint64_t flags, int condition) const
Definition: microop.cc:49
gem5::X86ISA::condition_tests::NotSxOF
@ NotSxOF
Definition: microop.hh:89
gem5::X86ISA::condition_tests::NotMSTRC
@ NotMSTRC
Definition: microop.hh:81
gem5::X86ISA::MicroCondBase
Definition: microop.hh:149
gem5::StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:61
gem5::X86ISA::condition_tests::NotOF
@ NotOF
Definition: microop.hh:83
gem5::X86ISA::condition_tests::SF
@ SF
Definition: microop.hh:69
gem5::X86ISA::condition_tests::STRZ
@ STRZ
Definition: microop.hh:62
gem5::X86ISA::condition_tests::NotSTRZ
@ NotSTRZ
Definition: microop.hh:80
gem5::X86ISA::condition_tests::CondTest
CondTest
Definition: microop.hh:54
gem5::X86ISA::condition_tests::NotCF
@ NotCF
Definition: microop.hh:84
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
ss
std::stringstream ss
Definition: trace.test.cc:45
compiler.hh
gem5::X86ISA::condition_tests::STRZnEZF
@ STRZnEZF
Definition: microop.hh:64
gem5::X86ISA::condition_tests::False
@ False
Definition: microop.hh:74
gem5::X86ISA::condition_tests::NotMSTRZ
@ NotMSTRZ
Definition: microop.hh:79
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GenericISA::UPCState::uAdvance
void uAdvance()
Definition: types.hh:240
gem5::X86ISA::MicroCondBase::cc
uint8_t cc
Definition: microop.hh:152
gem5::X86ISA::condition_tests::SZnZF
@ SZnZF
Definition: microop.hh:60
gem5::X86ISA::condition_tests::SxOF
@ SxOF
Definition: microop.hh:71
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::X86MicroopBase::advancePC
void advancePC(PCState &pcState) const override
Definition: microop.hh:135
gem5::X86ISA::condition_tests::NotTrue
@ NotTrue
Definition: microop.hh:75
gem5::X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:97
gem5::X86ISA::PCState
Definition: pcstate.hh:50
gem5::X86ISA::condition_tests::NotSZnZF
@ NotSZnZF
Definition: microop.hh:78
gem5::X86ISA::MicroCondBase::MicroCondBase
MicroCondBase(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem, uint64_t set_flags, OpClass op_class, uint8_t _cc)
Definition: microop.hh:155
gem5::X86ISA::condition_tests::NotSF
@ NotSF
Definition: microop.hh:87
gem5::X86ISA::X86MicroopBase
Definition: microop.hh:97
gem5::X86ISA::X86MicroopBase::instMnem
const char * instMnem
Definition: microop.hh:100
gem5::X86ISA::X86MicroopBase::X86MicroopBase
X86MicroopBase(ExtMachInst _machInst, const char *mnem, const char *_instMnem, uint64_t setFlags, OpClass __opClass)
Definition: microop.hh:104
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::condition_tests::NotCvZF
@ NotCvZF
Definition: microop.hh:86
gem5::X86ISA::condition_tests::EZF
@ EZF
Definition: microop.hh:59
gem5::X86ISA::condition_tests::ZF
@ ZF
Definition: microop.hh:67
gem5::X86ISA::condition_tests::CF
@ CF
Definition: microop.hh:66
gem5::X86ISA::condition_tests::NotSxOvZF
@ NotSxOvZF
Definition: microop.hh:90
gem5::X86ISA::condition_tests::SxOvZF
@ SxOvZF
Definition: microop.hh:72
gem5::X86ISA::condition_tests::True
@ True
Definition: microop.hh:56

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