gem5 v24.0.0.0
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noncoherent_xbar.hh
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1/*
2 * Copyright (c) 2011-2015, 2019 ARM Limited
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13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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40
46#ifndef __MEM_NONCOHERENT_XBAR_HH__
47#define __MEM_NONCOHERENT_XBAR_HH__
48
49#include "mem/xbar.hh"
50#include "params/NoncoherentXBar.hh"
51
52namespace gem5
53{
54
69{
70
71 protected:
72
79
86 {
87 private:
88
91
94
95 public:
96
98 NoncoherentXBar &_xbar, PortID _id)
99 : QueuedResponsePort(_name, queue, _id), xbar(_xbar),
100 queue(_xbar, *this)
101 { }
102
103 protected:
104
105 bool
107 {
108 return xbar.recvTimingReq(pkt, id);
109 }
110
111 Tick
112 recvAtomic(PacketPtr pkt) override
113 {
114 return xbar.recvAtomicBackdoor(pkt, id);
115 }
116
117 Tick
119 {
120 return xbar.recvAtomicBackdoor(pkt, id, &backdoor);
121 }
122
123 void
125 {
126 xbar.recvFunctional(pkt, id);
127 }
128
129 void
131 MemBackdoorPtr &backdoor) override
132 {
133 xbar.recvMemBackdoorReq(req, backdoor);
134 }
135
137 getAddrRanges() const override
138 {
139 return xbar.getAddrRanges();
140 }
141 };
142
149 {
150 private:
151
154
155 public:
156
158 NoncoherentXBar &_xbar, PortID _id)
159 : RequestPort(_name, _id), xbar(_xbar)
160 { }
161
162 protected:
163
164 bool
166 {
167 return xbar.recvTimingResp(pkt, id);
168 }
169
170 void
172 {
174 }
175
176 void
177 recvReqRetry() override
178 {
179 xbar.recvReqRetry(id);
180 }
181 };
182
183 virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id);
184 virtual bool recvTimingResp(PacketPtr pkt, PortID mem_side_port_id);
185 void recvReqRetry(PortID mem_side_port_id);
186 Tick recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id,
187 MemBackdoorPtr *backdoor=nullptr);
188 void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id);
189 void recvMemBackdoorReq(const MemBackdoorReq &req,
190 MemBackdoorPtr &backdoor);
191
192 public:
193
194 NoncoherentXBar(const NoncoherentXBarParams &p);
195
196 virtual ~NoncoherentXBar();
197};
198
199} // namespace gem5
200
201#endif //__MEM_NONCOHERENT_XBAR_HH__
The base crossbar contains the common elements of the non-coherent and coherent crossbar.
Definition xbar.hh:72
virtual void recvRangeChange(PortID mem_side_port_id)
Function called by the port when the crossbar is recieving a range change.
Definition xbar.cc:374
AddrRangeList getAddrRanges() const
Return the address ranges the crossbar is responsible for.
Definition xbar.cc:536
const std::string _name
Definition named.hh:41
Declaration of the crossbar memory-side port type, one will be instantiated for each of the CPU-side ...
NoncoherentXBar & xbar
A reference to the crossbar to which this port belongs.
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
void recvRangeChange() override
Called to receive an address range change from the peer response port.
NoncoherentXBarRequestPort(const std::string &_name, NoncoherentXBar &_xbar, PortID _id)
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Declaration of the non-coherent crossbar CPU-side port type, one will be instantiated for each of the...
NoncoherentXBar & xbar
A reference to the crossbar to which this port belongs.
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor) override
Receive a request for a back door to a range of memory.
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
RespPacketQueue queue
A normal packet queue used to store responses.
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
NoncoherentXBarResponsePort(const std::string &_name, NoncoherentXBar &_xbar, PortID _id)
A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides,...
NoncoherentXBar(const NoncoherentXBarParams &p)
std::vector< RespLayer * > respLayers
Tick recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id, MemBackdoorPtr *backdoor=nullptr)
void recvReqRetry(PortID mem_side_port_id)
virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
virtual bool recvTimingResp(PacketPtr pkt, PortID mem_side_port_id)
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor)
void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id)
std::vector< ReqLayer * > reqLayers
Declare the layers of this crossbar, one vector for requests and one for responses.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition qport.hh:62
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
STL vector class.
Definition stl.hh:37
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
Declaration of an abstract crossbar base class.

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