gem5  v21.1.0.2
xbar.cc
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40 
46 #include "mem/xbar.hh"
47 
48 #include "base/logging.hh"
49 #include "base/trace.hh"
50 #include "debug/AddrRanges.hh"
51 #include "debug/Drain.hh"
52 #include "debug/XBar.hh"
53 
54 namespace gem5
55 {
56 
57 BaseXBar::BaseXBar(const BaseXBarParams &p)
58  : ClockedObject(p),
59  frontendLatency(p.frontend_latency),
60  forwardLatency(p.forward_latency),
61  responseLatency(p.response_latency),
62  headerLatency(p.header_latency),
63  width(p.width),
64  gotAddrRanges(p.port_default_connection_count +
65  p.port_mem_side_ports_connection_count, false),
66  gotAllAddrRanges(false), defaultPortID(InvalidPortID),
67  useDefaultRange(p.use_default_range),
68 
69  ADD_STAT(transDist, statistics::units::Count::get(),
70  "Transaction distribution"),
71  ADD_STAT(pktCount, statistics::units::Count::get(),
72  "Packet count per connected requestor and responder"),
73  ADD_STAT(pktSize, statistics::units::Byte::get(),
74  "Cumulative packet size per connected requestor and responder")
75 {
76 }
77 
79 {
80  for (auto port: memSidePorts)
81  delete port;
82 
83  for (auto port: cpuSidePorts)
84  delete port;
85 }
86 
87 Port &
88 BaseXBar::getPort(const std::string &if_name, PortID idx)
89 {
90  if (if_name == "mem_side_ports" && idx < memSidePorts.size()) {
91  // the memory-side ports index translates directly to the vector
92  // position
93  return *memSidePorts[idx];
94  } else if (if_name == "default") {
95  return *memSidePorts[defaultPortID];
96  } else if (if_name == "cpu_side_ports" && idx < cpuSidePorts.size()) {
97  // the CPU-side ports index translates directly to the vector position
98  return *cpuSidePorts[idx];
99  } else {
100  return ClockedObject::getPort(if_name, idx);
101  }
102 }
103 
104 void
106 {
107  // the crossbar will be called at a time that is not necessarily
108  // coinciding with its own clock, so start by determining how long
109  // until the next clock edge (could be zero)
110  Tick offset = clockEdge() - curTick();
111 
112  // the header delay depends on the path through the crossbar, and
113  // we therefore rely on the caller to provide the actual
114  // value
115  pkt->headerDelay += offset + header_delay;
116 
117  // note that we add the header delay to the existing value, and
118  // align it to the crossbar clock
119 
120  // do a quick sanity check to ensure the timings are not being
121  // ignored, note that this specific value may cause problems for
122  // slower interconnects
124  "Encountered header delay exceeding 1 us\n");
125 
126  if (pkt->hasData()) {
127  // the payloadDelay takes into account the relative time to
128  // deliver the payload of the packet, after the header delay,
129  // we take the maximum since the payload delay could already
130  // be longer than what this parcitular crossbar enforces.
131  pkt->payloadDelay = std::max<Tick>(pkt->payloadDelay,
132  divCeil(pkt->getSize(), width) *
133  clockPeriod());
134  }
135 
136  // the payload delay is not paying for the clock offset as that is
137  // already done using the header delay, and the payload delay is
138  // also used to determine how long the crossbar layer is busy and
139  // thus regulates throughput
140 }
141 
142 template <typename SrcType, typename DstType>
144  const std::string& _name) :
145  statistics::Group(&_xbar, _name.c_str()),
146  port(_port), xbar(_xbar), _name(xbar.name() + "." + _name), state(IDLE),
147  waitingForPeer(NULL), releaseEvent([this]{ releaseLayer(); }, name()),
148  ADD_STAT(occupancy, statistics::units::Tick::get(), "Layer occupancy (ticks)"),
149  ADD_STAT(utilization, statistics::units::Ratio::get(), "Layer utilization")
150 {
151  occupancy
152  .flags(statistics::nozero);
153 
154  utilization
155  .precision(1)
156  .flags(statistics::nozero);
157 
158  utilization = occupancy / simTicks;
159 }
160 
161 template <typename SrcType, typename DstType>
163 {
164  // ensure the state is busy at this point, as the layer should
165  // transition from idle as soon as it has decided to forward the
166  // packet to prevent any follow-on calls to sendTiming seeing an
167  // unoccupied layer
168  assert(state == BUSY);
169 
170  // until should never be 0 as express snoops never occupy the layer
171  assert(until != 0);
172  xbar.schedule(releaseEvent, until);
173 
174  // account for the occupied ticks
175  occupancy += until - curTick();
176 
177  DPRINTF(BaseXBar, "The crossbar layer is now busy from tick %d to %d\n",
178  curTick(), until);
179 }
180 
181 template <typename SrcType, typename DstType>
182 bool
184 {
185  // if we are in the retry state, we will not see anything but the
186  // retrying port (or in the case of the snoop ports the snoop
187  // response port that mirrors the actual CPU-side port) as we leave
188  // this state again in zero time if the peer does not immediately
189  // call the layer when receiving the retry
190 
191  // first we see if the layer is busy, next we check if the
192  // destination port is already engaged in a transaction waiting
193  // for a retry from the peer
194  if (state == BUSY || waitingForPeer != NULL) {
195  // the port should not be waiting already
196  assert(std::find(waitingForLayer.begin(), waitingForLayer.end(),
197  src_port) == waitingForLayer.end());
198 
199  // put the port at the end of the retry list waiting for the
200  // layer to be freed up (and in the case of a busy peer, for
201  // that transaction to go through, and then the layer to free
202  // up)
203  waitingForLayer.push_back(src_port);
204  return false;
205  }
206 
207  state = BUSY;
208 
209  return true;
210 }
211 
212 template <typename SrcType, typename DstType>
213 void
215 {
216  // we should have gone from idle or retry to busy in the tryTiming
217  // test
218  assert(state == BUSY);
219 
220  // occupy the layer accordingly
221  occupyLayer(busy_time);
222 }
223 
224 template <typename SrcType, typename DstType>
225 void
227  Tick busy_time)
228 {
229  // ensure no one got in between and tried to send something to
230  // this port
231  assert(waitingForPeer == NULL);
232 
233  // if the source port is the current retrying one or not, we have
234  // failed in forwarding and should track that we are now waiting
235  // for the peer to send a retry
236  waitingForPeer = src_port;
237 
238  // we should have gone from idle or retry to busy in the tryTiming
239  // test
240  assert(state == BUSY);
241 
242  // occupy the bus accordingly
243  occupyLayer(busy_time);
244 }
245 
246 template <typename SrcType, typename DstType>
247 void
249 {
250  // releasing the bus means we should now be idle
251  assert(state == BUSY);
252  assert(!releaseEvent.scheduled());
253 
254  // update the state
255  state = IDLE;
256 
257  // bus layer is now idle, so if someone is waiting we can retry
258  if (!waitingForLayer.empty()) {
259  // there is no point in sending a retry if someone is still
260  // waiting for the peer
261  if (waitingForPeer == NULL)
262  retryWaiting();
263  } else if (waitingForPeer == NULL && drainState() == DrainState::Draining) {
264  DPRINTF(Drain, "Crossbar done draining, signaling drain manager\n");
265  //If we weren't able to drain before, do it now.
266  signalDrainDone();
267  }
268 }
269 
270 template <typename SrcType, typename DstType>
271 void
273 {
274  // this should never be called with no one waiting
275  assert(!waitingForLayer.empty());
276 
277  // we always go to retrying from idle
278  assert(state == IDLE);
279 
280  // update the state
281  state = RETRY;
282 
283  // set the retrying port to the front of the retry list and pop it
284  // off the list
285  SrcType* retryingPort = waitingForLayer.front();
286  waitingForLayer.pop_front();
287 
288  // tell the port to retry, which in some cases ends up calling the
289  // layer again
290  sendRetry(retryingPort);
291 
292  // If the layer is still in the retry state, sendTiming wasn't
293  // called in zero time (e.g. the cache does this when a writeback
294  // is squashed)
295  if (state == RETRY) {
296  // update the state to busy and reset the retrying port, we
297  // have done our bit and sent the retry
298  state = BUSY;
299 
300  // occupy the crossbar layer until the next clock edge
301  occupyLayer(xbar.clockEdge());
302  }
303 }
304 
305 template <typename SrcType, typename DstType>
306 void
308 {
309  // we should never get a retry without having failed to forward
310  // something to this port
311  assert(waitingForPeer != NULL);
312 
313  // add the port where the failed packet originated to the front of
314  // the waiting ports for the layer, this allows us to call retry
315  // on the port immediately if the crossbar layer is idle
316  waitingForLayer.push_front(waitingForPeer);
317 
318  // we are no longer waiting for the peer
319  waitingForPeer = NULL;
320 
321  // if the layer is idle, retry this port straight away, if we
322  // are busy, then simply let the port wait for its turn
323  if (state == IDLE) {
324  retryWaiting();
325  } else {
326  assert(state == BUSY);
327  }
328 }
329 
330 PortID
331 BaseXBar::findPort(AddrRange addr_range)
332 {
333  // we should never see any address lookups before we've got the
334  // ranges of all connected CPU-side-port modules
335  assert(gotAllAddrRanges);
336 
337  // Check the address map interval tree
338  auto i = portMap.contains(addr_range);
339  if (i != portMap.end()) {
340  return i->second;
341  }
342 
343  // Check if this matches the default range
344  if (useDefaultRange) {
345  if (addr_range.isSubset(defaultRange)) {
346  DPRINTF(AddrRanges, " found addr %s on default\n",
347  addr_range.to_string());
348  return defaultPortID;
349  }
350  } else if (defaultPortID != InvalidPortID) {
351  DPRINTF(AddrRanges, "Unable to find destination for %s, "
352  "will use default port\n", addr_range.to_string());
353  return defaultPortID;
354  }
355 
356  // we should use the range for the default port and it did not
357  // match, or the default port is not set
358  fatal("Unable to find destination for %s on %s\n", addr_range.to_string(),
359  name());
360 }
361 
363 void
364 BaseXBar::recvRangeChange(PortID mem_side_port_id)
365 {
366  DPRINTF(AddrRanges, "Received range change from cpu_side_ports %s\n",
367  memSidePorts[mem_side_port_id]->getPeer());
368 
369  // remember that we got a range from this memory-side port and thus the
370  // connected CPU-side-port module
371  gotAddrRanges[mem_side_port_id] = true;
372 
373  // update the global flag
374  if (!gotAllAddrRanges) {
375  // take a logical AND of all the ports and see if we got
376  // ranges from everyone
377  gotAllAddrRanges = true;
378  std::vector<bool>::const_iterator r = gotAddrRanges.begin();
379  while (gotAllAddrRanges && r != gotAddrRanges.end()) {
380  gotAllAddrRanges &= *r++;
381  }
382  if (gotAllAddrRanges)
383  DPRINTF(AddrRanges, "Got address ranges from all responders\n");
384  }
385 
386  // note that we could get the range from the default port at any
387  // point in time, and we cannot assume that the default range is
388  // set before the other ones are, so we do additional checks once
389  // all ranges are provided
390  if (mem_side_port_id == defaultPortID) {
391  // only update if we are indeed checking ranges for the
392  // default port since the port might not have a valid range
393  // otherwise
394  if (useDefaultRange) {
395  AddrRangeList ranges = memSidePorts[mem_side_port_id]->
396  getAddrRanges();
397 
398  if (ranges.size() != 1)
399  fatal("Crossbar %s may only have a single default range",
400  name());
401 
402  defaultRange = ranges.front();
403  }
404  } else {
405  // the ports are allowed to update their address ranges
406  // dynamically, so remove any existing entries
407  if (gotAddrRanges[mem_side_port_id]) {
408  for (auto p = portMap.begin(); p != portMap.end(); ) {
409  if (p->second == mem_side_port_id)
410  // erasing invalidates the iterator, so advance it
411  // before the deletion takes place
412  portMap.erase(p++);
413  else
414  p++;
415  }
416  }
417 
418  AddrRangeList ranges = memSidePorts[mem_side_port_id]->
419  getAddrRanges();
420 
421  for (const auto& r: ranges) {
422  DPRINTF(AddrRanges, "Adding range %s for id %d\n",
423  r.to_string(), mem_side_port_id);
424  if (portMap.insert(r, mem_side_port_id) == portMap.end()) {
425  PortID conflict_id = portMap.intersects(r)->second;
426  fatal("%s has two ports responding within range "
427  "%s:\n\t%s\n\t%s\n",
428  name(),
429  r.to_string(),
430  memSidePorts[mem_side_port_id]->getPeer(),
431  memSidePorts[conflict_id]->getPeer());
432  }
433  }
434  }
435 
436  // if we have received ranges from all our neighbouring CPU-side-port
437  // modules, go ahead and tell our connected memory-side-port modules in
438  // turn, this effectively assumes a tree structure of the system
439  if (gotAllAddrRanges) {
440  DPRINTF(AddrRanges, "Aggregating address ranges\n");
441  xbarRanges.clear();
442 
443  // start out with the default range
444  if (useDefaultRange) {
445  if (!gotAddrRanges[defaultPortID])
446  fatal("Crossbar %s uses default range, but none provided",
447  name());
448 
449  xbarRanges.push_back(defaultRange);
450  DPRINTF(AddrRanges, "-- Adding default %s\n",
451  defaultRange.to_string());
452  }
453 
454  // merge all interleaved ranges and add any range that is not
455  // a subset of the default range
456  std::vector<AddrRange> intlv_ranges;
457  for (const auto& r: portMap) {
458  // if the range is interleaved then save it for now
459  if (r.first.interleaved()) {
460  // if we already got interleaved ranges that are not
461  // part of the same range, then first do a merge
462  // before we add the new one
463  if (!intlv_ranges.empty() &&
464  !intlv_ranges.back().mergesWith(r.first)) {
465  DPRINTF(AddrRanges, "-- Merging range from %d ranges\n",
466  intlv_ranges.size());
467  AddrRange merged_range(intlv_ranges);
468  // next decide if we keep the merged range or not
469  if (!(useDefaultRange &&
470  merged_range.isSubset(defaultRange))) {
471  xbarRanges.push_back(merged_range);
472  DPRINTF(AddrRanges, "-- Adding merged range %s\n",
473  merged_range.to_string());
474  }
475  intlv_ranges.clear();
476  }
477  intlv_ranges.push_back(r.first);
478  } else {
479  // keep the current range if not a subset of the default
480  if (!(useDefaultRange &&
481  r.first.isSubset(defaultRange))) {
482  xbarRanges.push_back(r.first);
483  DPRINTF(AddrRanges, "-- Adding range %s\n",
484  r.first.to_string());
485  }
486  }
487  }
488 
489  // if there is still interleaved ranges waiting to be merged,
490  // go ahead and do it
491  if (!intlv_ranges.empty()) {
492  DPRINTF(AddrRanges, "-- Merging range from %d ranges\n",
493  intlv_ranges.size());
494  AddrRange merged_range(intlv_ranges);
495  if (!(useDefaultRange && merged_range.isSubset(defaultRange))) {
496  xbarRanges.push_back(merged_range);
497  DPRINTF(AddrRanges, "-- Adding merged range %s\n",
498  merged_range.to_string());
499  }
500  }
501 
502  // also check that no range partially intersects with the
503  // default range, this has to be done after all ranges are set
504  // as there are no guarantees for when the default range is
505  // update with respect to the other ones
506  if (useDefaultRange) {
507  for (const auto& r: xbarRanges) {
508  // see if the new range is partially
509  // overlapping the default range
510  if (r.intersects(defaultRange) &&
511  !r.isSubset(defaultRange))
512  fatal("Range %s intersects the " \
513  "default range of %s but is not a " \
514  "subset\n", r.to_string(), name());
515  }
516  }
517 
518  // tell all our neighbouring memory-side ports that our address
519  // ranges have changed
520  for (const auto& port: cpuSidePorts)
521  port->sendRangeChange();
522  }
523 }
524 
526 BaseXBar::getAddrRanges() const
527 {
528  // we should never be asked without first having sent a range
529  // change, and the latter is only done once we have all the ranges
530  // of the connected devices
531  assert(gotAllAddrRanges);
532 
533  // at the moment, this never happens, as there are no cycles in
534  // the range queries and no devices on the memory side of a crossbar
535  // (CPU, cache, bridge etc) actually care about the ranges of the
536  // ports they are connected to
537 
538  DPRINTF(AddrRanges, "Received address range request\n");
539 
540  return xbarRanges;
541 }
542 
543 void
544 BaseXBar::regStats()
545 {
546  ClockedObject::regStats();
547 
548  using namespace statistics;
549 
550  transDist
551  .init(MemCmd::NUM_MEM_CMDS)
552  .flags(nozero);
553 
554  // get the string representation of the commands
555  for (int i = 0; i < MemCmd::NUM_MEM_CMDS; i++) {
556  MemCmd cmd(i);
557  const std::string &cstr = cmd.toString();
558  transDist.subname(i, cstr);
559  }
560 
561  pktCount
562  .init(cpuSidePorts.size(), memSidePorts.size())
563  .flags(total | nozero | nonan);
564 
565  pktSize
566  .init(cpuSidePorts.size(), memSidePorts.size())
567  .flags(total | nozero | nonan);
568 
569  // both the packet count and total size are two-dimensional
570  // vectors, indexed by CPU-side port id and memory-side port id, thus the
571  // neighbouring memory-side ports and CPU-side ports, they do not
572  // differentiate what came from the memory-side ports and was forwarded to
573  // the CPU-side ports (requests and snoop responses) and what came from
574  // the CPU-side ports and was forwarded to the memory-side ports (responses
575  // and snoop requests)
576  for (int i = 0; i < cpuSidePorts.size(); i++) {
577  pktCount.subname(i, cpuSidePorts[i]->getPeer().name());
578  pktSize.subname(i, cpuSidePorts[i]->getPeer().name());
579  for (int j = 0; j < memSidePorts.size(); j++) {
580  pktCount.ysubname(j, memSidePorts[j]->getPeer().name());
581  pktSize.ysubname(j, memSidePorts[j]->getPeer().name());
582  }
583  }
584 }
585 
586 template <typename SrcType, typename DstType>
589 {
590  //We should check that we're not "doing" anything, and that noone is
591  //waiting. We might be idle but have someone waiting if the device we
592  //contacted for a retry didn't actually retry.
593  if (state != IDLE) {
594  DPRINTF(Drain, "Crossbar not drained\n");
595  return DrainState::Draining;
596  } else {
597  return DrainState::Drained;
598  }
599 }
600 
608 
609 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::BaseXBar
The base crossbar contains the common elements of the non-coherent and coherent crossbar.
Definition: xbar.hh:71
gem5::AddrRange::to_string
std::string to_string() const
Get a string representation of the range.
Definition: addr_range.hh:333
gem5::scmi::BUSY
@ BUSY
Definition: scmi_protocols.hh:64
gem5::BaseXBar::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
A function used to return the port associated with this object.
Definition: xbar.cc:88
gem5::BaseXBar::width
const uint32_t width
the width of the xbar in bytes
Definition: xbar.hh:317
gem5::BaseXBar::cpuSidePorts
std::vector< QueuedResponsePort * > cpuSidePorts
The memory-side ports and CPU-side ports of the crossbar.
Definition: xbar.hh:379
xbar.hh
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
std::vector
STL vector class.
Definition: stl.hh:37
gem5::statistics::nonan
const FlagsType nonan
Don't print if this is NAN.
Definition: info.hh:70
gem5::sim_clock::as_int::us
Tick us
microsecond
Definition: core.cc:70
gem5::AddrRange::isSubset
bool isSubset(const AddrRange &r) const
Determine if this range is a subset of another range, i.e.
Definition: addr_range.hh:413
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::Packet::hasData
bool hasData() const
Definition: packet.hh:603
gem5::MemCmd
Definition: packet.hh:75
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:75
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::BaseXBar::BaseXBar
BaseXBar(const BaseXBarParams &p)
Definition: xbar.cc:57
gem5::BaseXBar::Layer::Layer
Layer(DstType &_port, BaseXBar &_xbar, const std::string &_name)
Create a layer and give it a name.
Definition: xbar.cc:143
name
const std::string & name()
Definition: trace.cc:49
gem5::BaseXBar::defaultPortID
PortID defaultPortID
Port that handles requests that don't match any of the interfaces.
Definition: xbar.hh:383
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::MemCmd::toString
const std::string & toString() const
Return the string to a cmd given by idx.
Definition: packet.hh:265
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
gem5::BaseXBar::~BaseXBar
virtual ~BaseXBar()
Definition: xbar.cc:78
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::BaseXBar::calcPacketTiming
void calcPacketTiming(PacketPtr pkt, Tick header_delay)
Calculate the timing parameters for the packet.
Definition: xbar.cc:105
trace.hh
gem5::BaseXBar::Layer
A layer is an internal crossbar arbitration point with its own flow control.
Definition: xbar.hh:91
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list< AddrRange >
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::statistics::total
const FlagsType total
Print the total.
Definition: info.hh:60
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::simTicks
statistics::Value & simTicks
Definition: stats.cc:46
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::BaseXBar::memSidePorts
std::vector< RequestPort * > memSidePorts
Definition: xbar.hh:380

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