gem5  v21.1.0.2
noncoherent_xbar.cc
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40 
46 #include "mem/noncoherent_xbar.hh"
47 
48 #include "base/logging.hh"
49 #include "base/trace.hh"
50 #include "debug/NoncoherentXBar.hh"
51 #include "debug/XBar.hh"
52 
53 namespace gem5
54 {
55 
56 NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams &p)
57  : BaseXBar(p)
58 {
59  // create the ports based on the size of the memory-side port and
60  // CPU-side port vector ports, and the presence of the default port,
61  // the ports are enumerated starting from zero
62  for (int i = 0; i < p.port_mem_side_ports_connection_count; ++i) {
63  std::string portName = csprintf("%s.mem_side_port[%d]", name(), i);
64  RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this, i);
65  memSidePorts.push_back(bp);
66  reqLayers.push_back(new ReqLayer(*bp, *this,
67  csprintf("reqLayer%d", i)));
68  }
69 
70  // see if we have a default CPU-side-port device connected and if so add
71  // our corresponding memory-side port
72  if (p.port_default_connection_count) {
73  defaultPortID = memSidePorts.size();
74  std::string portName = name() + ".default";
75  RequestPort* bp = new NoncoherentXBarRequestPort(portName, *this,
77  memSidePorts.push_back(bp);
78  reqLayers.push_back(new ReqLayer(*bp, *this, csprintf("reqLayer%d",
79  defaultPortID)));
80  }
81 
82  // create the CPU-side ports, once again starting at zero
83  for (int i = 0; i < p.port_cpu_side_ports_connection_count; ++i) {
84  std::string portName = csprintf("%s.cpu_side_ports[%d]", name(), i);
86  *this, i);
87  cpuSidePorts.push_back(bp);
88  respLayers.push_back(new RespLayer(*bp, *this,
89  csprintf("respLayer%d", i)));
90  }
91 }
92 
94 {
95  for (auto l: reqLayers)
96  delete l;
97  for (auto l: respLayers)
98  delete l;
99 }
100 
101 bool
103 {
104  // determine the source port based on the id
105  ResponsePort *src_port = cpuSidePorts[cpu_side_port_id];
106 
107  // we should never see express snoops on a non-coherent crossbar
108  assert(!pkt->isExpressSnoop());
109 
110  // determine the destination based on the address
111  PortID mem_side_port_id = findPort(pkt->getAddrRange());
112 
113  // test if the layer should be considered occupied for the current
114  // port
115  if (!reqLayers[mem_side_port_id]->tryTiming(src_port)) {
116  DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x BUSY\n",
117  src_port->name(), pkt->cmdString(), pkt->getAddr());
118  return false;
119  }
120 
121  DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x\n",
122  src_port->name(), pkt->cmdString(), pkt->getAddr());
123 
124  // store size and command as they might be modified when
125  // forwarding the packet
126  unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
127  unsigned int pkt_cmd = pkt->cmdToIndex();
128 
129  // store the old header delay so we can restore it if needed
130  Tick old_header_delay = pkt->headerDelay;
131 
132  // a request sees the frontend and forward latency
133  Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
134 
135  // set the packet header and payload delay
136  calcPacketTiming(pkt, xbar_delay);
137 
138  // determine how long to be crossbar layer is busy
139  Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
140 
141  // before forwarding the packet (and possibly altering it),
142  // remember if we are expecting a response
143  const bool expect_response = pkt->needsResponse() &&
144  !pkt->cacheResponding();
145 
146  // since it is a normal request, attempt to send the packet
147  bool success = memSidePorts[mem_side_port_id]->sendTimingReq(pkt);
148 
149  if (!success) {
150  DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
151  src_port->name(), pkt->cmdString(), pkt->getAddr());
152 
153  // restore the header delay as it is additive
154  pkt->headerDelay = old_header_delay;
155 
156  // occupy until the header is sent
157  reqLayers[mem_side_port_id]->failedTiming(src_port,
158  clockEdge(Cycles(1)));
159 
160  return false;
161  }
162 
163  // remember where to route the response to
164  if (expect_response) {
165  assert(routeTo.find(pkt->req) == routeTo.end());
166  routeTo[pkt->req] = cpu_side_port_id;
167  }
168 
169  reqLayers[mem_side_port_id]->succeededTiming(packetFinishTime);
170 
171  // stats updates
172  pktCount[cpu_side_port_id][mem_side_port_id]++;
173  pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
174  transDist[pkt_cmd]++;
175 
176  return true;
177 }
178 
179 bool
181 {
182  // determine the source port based on the id
183  RequestPort *src_port = memSidePorts[mem_side_port_id];
184 
185  // determine the destination
186  const auto route_lookup = routeTo.find(pkt->req);
187  assert(route_lookup != routeTo.end());
188  const PortID cpu_side_port_id = route_lookup->second;
189  assert(cpu_side_port_id != InvalidPortID);
190  assert(cpu_side_port_id < respLayers.size());
191 
192  // test if the layer should be considered occupied for the current
193  // port
194  if (!respLayers[cpu_side_port_id]->tryTiming(src_port)) {
195  DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x BUSY\n",
196  src_port->name(), pkt->cmdString(), pkt->getAddr());
197  return false;
198  }
199 
200  DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x\n",
201  src_port->name(), pkt->cmdString(), pkt->getAddr());
202 
203  // store size and command as they might be modified when
204  // forwarding the packet
205  unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
206  unsigned int pkt_cmd = pkt->cmdToIndex();
207 
208  // a response sees the response latency
209  Tick xbar_delay = responseLatency * clockPeriod();
210 
211  // set the packet header and payload delay
212  calcPacketTiming(pkt, xbar_delay);
213 
214  // determine how long to be crossbar layer is busy
215  Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
216 
217  // send the packet through the destination CPU-side port, and pay for
218  // any outstanding latency
219  Tick latency = pkt->headerDelay;
220  pkt->headerDelay = 0;
221  cpuSidePorts[cpu_side_port_id]->schedTimingResp(pkt,
222  curTick() + latency);
223 
224  // remove the request from the routing table
225  routeTo.erase(route_lookup);
226 
227  respLayers[cpu_side_port_id]->succeededTiming(packetFinishTime);
228 
229  // stats updates
230  pktCount[cpu_side_port_id][mem_side_port_id]++;
231  pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
232  transDist[pkt_cmd]++;
233 
234  return true;
235 }
236 
237 void
239 {
240  // responses never block on forwarding them, so the retry will
241  // always be coming from a port to which we tried to forward a
242  // request
243  reqLayers[mem_side_port_id]->recvRetry();
244 }
245 
246 Tick
248  MemBackdoorPtr *backdoor)
249 {
250  DPRINTF(NoncoherentXBar, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
251  cpuSidePorts[cpu_side_port_id]->name(), pkt->getAddr(),
252  pkt->cmdString());
253 
254  unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
255  unsigned int pkt_cmd = pkt->cmdToIndex();
256 
257  // determine the destination port
258  PortID mem_side_port_id = findPort(pkt->getAddrRange());
259 
260  // stats updates for the request
261  pktCount[cpu_side_port_id][mem_side_port_id]++;
262  pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
263  transDist[pkt_cmd]++;
264 
265  // forward the request to the appropriate destination
266  auto mem_side_port = memSidePorts[mem_side_port_id];
267  Tick response_latency = backdoor ?
268  mem_side_port->sendAtomicBackdoor(pkt, *backdoor) :
269  mem_side_port->sendAtomic(pkt);
270 
271  // add the response data
272  if (pkt->isResponse()) {
273  pkt_size = pkt->hasData() ? pkt->getSize() : 0;
274  pkt_cmd = pkt->cmdToIndex();
275 
276  // stats updates
277  pktCount[cpu_side_port_id][mem_side_port_id]++;
278  pktSize[cpu_side_port_id][mem_side_port_id] += pkt_size;
279  transDist[pkt_cmd]++;
280  }
281 
282  // @todo: Not setting first-word time
283  pkt->payloadDelay = response_latency;
284  return response_latency;
285 }
286 
287 void
289 {
290  if (!pkt->isPrint()) {
291  // don't do DPRINTFs on PrintReq as it clutters up the output
293  "recvFunctional: packet src %s addr 0x%x cmd %s\n",
294  cpuSidePorts[cpu_side_port_id]->name(), pkt->getAddr(),
295  pkt->cmdString());
296  }
297 
298  // since our CPU-side ports are queued ports we need to check them as well
299  for (const auto& p : cpuSidePorts) {
300  // if we find a response that has the data, then the
301  // downstream caches/memories may be out of date, so simply stop
302  // here
303  if (p->trySatisfyFunctional(pkt)) {
304  if (pkt->needsResponse())
305  pkt->makeResponse();
306  return;
307  }
308  }
309 
310  // determine the destination port
311  PortID dest_id = findPort(pkt->getAddrRange());
312 
313  // forward the request to the appropriate destination
314  memSidePorts[dest_id]->sendFunctional(pkt);
315 }
316 
317 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:577
gem5::BaseXBar
The base crossbar contains the common elements of the non-coherent and coherent crossbar.
Definition: xbar.hh:71
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::NoncoherentXBar::NoncoherentXBarRequestPort
Declaration of the crossbar memory-side port type, one will be instantiated for each of the CPU-side ...
Definition: noncoherent_xbar.hh:141
gem5::BaseXBar::cpuSidePorts
std::vector< QueuedResponsePort * > cpuSidePorts
The memory-side ports and CPU-side ports of the crossbar.
Definition: xbar.hh:379
gem5::BaseXBar::frontendLatency
const Cycles frontendLatency
Cycles of front-end pipeline including the delay to accept the request and to decode the address.
Definition: xbar.hh:311
gem5::BaseXBar::ReqLayer
Definition: xbar.hh:237
gem5::NoncoherentXBar
A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides,...
Definition: noncoherent_xbar.hh:68
gem5::BaseXBar::routeTo
std::unordered_map< RequestPtr, PortID > routeTo
Remember where request packets came from so that we can route responses to the appropriate port.
Definition: xbar.hh:327
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
noncoherent_xbar.hh
gem5::NoncoherentXBar::reqLayers
std::vector< ReqLayer * > reqLayers
Declare the layers of this crossbar, one vector for requests and one for responses.
Definition: noncoherent_xbar.hh:77
gem5::NoncoherentXBar::recvFunctional
void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id)
Definition: noncoherent_xbar.cc:288
gem5::BaseXBar::pktCount
statistics::Vector2d pktCount
Definition: xbar.hh:403
gem5::Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:646
gem5::BaseXBar::responseLatency
const Cycles responseLatency
Definition: xbar.hh:313
gem5::BaseXBar::RespLayer
Definition: xbar.hh:260
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::NoncoherentXBar::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id, MemBackdoorPtr *backdoor=nullptr)
Definition: noncoherent_xbar.cc:247
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Packet::hasData
bool hasData() const
Definition: packet.hh:603
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::NoncoherentXBar::NoncoherentXBarResponsePort
Declaration of the non-coherent crossbar CPU-side port type, one will be instantiated for each of the...
Definition: noncoherent_xbar.hh:85
gem5::NoncoherentXBar::~NoncoherentXBar
virtual ~NoncoherentXBar()
Definition: noncoherent_xbar.cc:93
gem5::BaseXBar::forwardLatency
const Cycles forwardLatency
Definition: xbar.hh:312
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::BaseXBar::transDist
statistics::Vector transDist
Stats for transaction distribution and data passing through the crossbar.
Definition: xbar.hh:402
gem5::QueuedResponsePort
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition: qport.hh:61
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::NoncoherentXBar::respLayers
std::vector< RespLayer * > respLayers
Definition: noncoherent_xbar.hh:78
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::Packet::isPrint
bool isPrint() const
Definition: packet.hh:611
gem5::Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:597
gem5::NoncoherentXBar::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
Definition: noncoherent_xbar.cc:102
gem5::BaseXBar::defaultPortID
PortID defaultPortID
Port that handles requests that don't match any of the interfaces.
Definition: xbar.hh:383
gem5::MemBackdoor
Definition: backdoor.hh:41
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::NoncoherentXBar::NoncoherentXBar
NoncoherentXBar(const NoncoherentXBarParams &p)
Definition: noncoherent_xbar.cc:56
gem5::BaseXBar::pktSize
statistics::Vector2d pktSize
Definition: xbar.hh:404
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
logging.hh
gem5::NoncoherentXBar::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt, PortID mem_side_port_id)
Definition: noncoherent_xbar.cc:180
gem5::BaseXBar::calcPacketTiming
void calcPacketTiming(PacketPtr pkt, Tick header_delay)
Calculate the timing parameters for the packet.
Definition: xbar.cc:105
gem5::Packet::isExpressSnoop
bool isExpressSnoop() const
Definition: packet.hh:689
trace.hh
gem5::BaseXBar::findPort
PortID findPort(AddrRange addr_range)
Find which port connected to this crossbar (if any) should be given a packet with this address range.
Definition: xbar.cc:331
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::getAddrRange
AddrRange getAddrRange() const
Get address range to which this packet belongs.
Definition: packet.cc:225
gem5::Packet::cmdToIndex
int cmdToIndex() const
Return the index of this command.
Definition: packet.hh:580
gem5::NoncoherentXBar::recvReqRetry
void recvReqRetry(PortID mem_side_port_id)
Definition: noncoherent_xbar.cc:238
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Clocked::clockPeriod
Tick clockPeriod() const
Definition: clocked_object.hh:217
gem5::BaseXBar::memSidePorts
std::vector< RequestPort * > memSidePorts
Definition: xbar.hh:380

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