gem5
v24.0.0.0
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arch
riscv
pagetable.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2020 Barkhausen Institut
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/riscv/pagetable.hh
"
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#include "
sim/serialize.hh
"
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namespace
gem5
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{
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namespace
RiscvISA
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{
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void
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TlbEntry::serialize
(
CheckpointOut
&cp)
const
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{
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SERIALIZE_SCALAR
(
paddr
);
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SERIALIZE_SCALAR
(
vaddr
);
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SERIALIZE_SCALAR
(
logBytes
);
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SERIALIZE_SCALAR
(
asid
);
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SERIALIZE_SCALAR
(
pte
);
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SERIALIZE_SCALAR
(
lruSeq
);
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}
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void
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TlbEntry::unserialize
(
CheckpointIn
&cp)
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{
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UNSERIALIZE_SCALAR
(
paddr
);
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UNSERIALIZE_SCALAR
(
vaddr
);
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UNSERIALIZE_SCALAR
(
logBytes
);
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UNSERIALIZE_SCALAR
(
asid
);
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UNSERIALIZE_SCALAR
(
pte
);
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UNSERIALIZE_SCALAR
(
lruSeq
);
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}
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}
// namespace RiscvISA
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}
// namespace gem5
gem5::CheckpointIn
Definition
serialize.hh:69
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::CheckpointOut
std::ostream CheckpointOut
Definition
serialize.hh:66
pagetable.hh
serialize.hh
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition
serialize.hh:575
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition
serialize.hh:568
gem5::RiscvISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition
pagetable.cc:53
gem5::RiscvISA::TlbEntry::vaddr
Addr vaddr
Definition
pagetable.hh:88
gem5::RiscvISA::TlbEntry::lruSeq
uint64_t lruSeq
Definition
pagetable.hh:99
gem5::RiscvISA::TlbEntry::asid
uint16_t asid
Definition
pagetable.hh:92
gem5::RiscvISA::TlbEntry::paddr
Addr paddr
Definition
pagetable.hh:85
gem5::RiscvISA::TlbEntry::pte
PTESv39 pte
Definition
pagetable.hh:94
gem5::RiscvISA::TlbEntry::logBytes
unsigned logBytes
Definition
pagetable.hh:90
gem5::RiscvISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition
pagetable.cc:42
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