gem5 v24.0.0.0
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sc_lv_base.cc
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 sc_lv_base.cpp -- Arbitrary size logic vector class.
23
24 Original Author: Gene Bushuyev, Synopsys, Inc.
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38
39// $Log: sc_lv_base.cpp,v $
40// Revision 1.2 2011/08/24 22:05:40 acg
41// Torsten Maehne: initialization changes to remove warnings.
42//
43// Revision 1.1.1.1 2006/12/15 20:20:04 acg
44// SystemC 2.3
45//
46// Revision 1.3 2006/01/13 18:53:53 acg
47// Andy Goodrich: added $Log command so that CVS comments are reproduced in
48// the source.
49//
50
51#include <sstream>
52
56
57namespace sc_dt
58{
59
60// explicit template instantiations
61template class sc_proxy<sc_lv_base>;
62template class sc_proxy<sc_bv_base>;
63
64void
65sc_proxy_out_of_bounds(const char *msg, int64 val)
66{
67 std::stringstream ss;
68 if (msg != NULL)
69 ss << msg;
70 if (val != 0)
71 ss << val;
73}
74
75// ----------------------------------------------------------------------------
76// CLASS : sc_lv_base
77//
78// Arbitrary size logic vector base class.
79// ----------------------------------------------------------------------------
80
81static const sc_digit data_array[] = {
82 SC_DIGIT_ZERO, ~SC_DIGIT_ZERO, SC_DIGIT_ZERO, ~SC_DIGIT_ZERO
83};
84
85static const sc_digit ctrl_array[] = {
86 SC_DIGIT_ZERO, SC_DIGIT_ZERO, ~SC_DIGIT_ZERO, ~SC_DIGIT_ZERO
87};
88
89void
90sc_lv_base::init(int length_, const sc_logic& init_value)
91{
92 // check the length
93 if (length_ <= 0) {
95 sc_core::sc_abort(); // can't recover from here
96 }
97 // allocate memory for the data and control words
98 m_len = length_;
99 m_size = (m_len - 1) / SC_DIGIT_SIZE + 1;
100 m_data = new sc_digit[m_size * 2];
101 m_ctrl = m_data + m_size;
102 // initialize the bits to 'init_value'
103 sc_digit dw = data_array[init_value.value()];
104 sc_digit cw = ctrl_array[init_value.value()];
105 int sz = m_size;
106 for (int i = 0; i < sz; ++i) {
107 m_data[i] = dw;
108 m_ctrl[i] = cw;
109 }
110 clean_tail();
111}
112
113void
115{
116 // s must have been converted to bin
117 int len = m_len;
118 int s_len = s.length() - 1;
119 int min_len = sc_min(len, s_len);
120 int i = 0;
121 for (; i < min_len; ++i) {
122 char c = s[s_len - i - 1];
124 }
125 // if formatted, fill the rest with sign(s), otherwise fill with zeros
126 sc_logic_value_t fill = (s[s_len] == 'F' ? sc_logic_value_t(s[0] - '0')
127 : sc_logic_value_t(0));
128 for (; i < len; ++i) {
129 set_bit(i, fill);
130 }
131}
132
133// constructors
135 m_len(0), m_size(0), m_data(0), m_ctrl(0)
136{
137 std::string s = convert_to_bin(a);
138 init(s.length() - 1);
140}
141
142sc_lv_base::sc_lv_base(const char *a, int length_) :
143 m_len(0), m_size(0), m_data(0), m_ctrl(0)
144{
145 init(length_);
147}
148
150 sc_proxy<sc_lv_base>(), m_len(a.m_len), m_size(a.m_size),
151 m_data(new sc_digit[m_size * 2]), m_ctrl(m_data + m_size)
152{
153 // copy the bits
154 int sz = m_size;
155 for (int i = 0; i < sz; ++i) {
156 m_data[i] = a.m_data[i];
157 m_ctrl[i] = a.m_ctrl[i];
158 }
159}
160
161// assignment operators
164{
166 return *this;
167}
168
169// returns true if logic vector contains only 0's and 1's
170bool
172{
173 int sz = m_size;
174 for (int i = 0; i < sz; ++i) {
175 if (m_ctrl[i] != 0) {
176 return false;
177 }
178 }
179 return true;
180}
181
182} // namespace sc_dt
static const sc_logic_value_t char_to_logic[128]
Definition sc_logic.hh:146
sc_logic_value_t value() const
Definition sc_logic.hh:236
void set_bit(int i, value_type value)
sc_lv_base & operator=(const sc_proxy< X > &a)
sc_lv_base(int length_=sc_length_param().len())
Definition sc_lv_base.hh:97
bool is_01() const
sc_digit * m_data
sc_digit * m_ctrl
void assign_from_string(const std::string &)
void init(int length_, const sc_logic &init_value=SC_LOGIC_X)
Definition sc_lv_base.cc:90
SwitchingFiber c
SwitchingFiber a
uint16_t len
Definition helpers.cc:83
void sc_abort()
Definition sc_report.cc:178
const char SC_ID_ZERO_LENGTH_[]
Definition messages.cc:40
const char SC_ID_OUT_OF_BOUNDS_[]
Definition messages.cc:40
sc_logic_value_t
Definition sc_logic.hh:85
const int SC_DIGIT_SIZE
Definition sc_proxy.hh:98
const sc_digit SC_DIGIT_ZERO
Definition sc_proxy.hh:100
const T sc_min(const T &a, const T &b)
Definition functions.hh:59
int64_t int64
Definition sc_nbdefs.hh:171
static const sc_digit data_array[]
Definition sc_lv_base.cc:81
unsigned int sc_digit
Definition sc_nbdefs.hh:163
static const sc_digit ctrl_array[]
Definition sc_lv_base.cc:85
const std::string convert_to_bin(const char *s)
void sc_proxy_out_of_bounds(const char *msg, int64 val)
Definition sc_lv_base.cc:65
#define SC_REPORT_ERROR(msg_type, msg)
std::stringstream ss
Definition trace.test.cc:45

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