gem5  v22.0.0.1
Classes | Namespaces | Macros | Functions | Variables
sinicreg.hh File Reference
#include <cstdint>
#include "base/compiler.hh"

Go to the source code of this file.

Classes

struct  gem5::sinic::registers::Info
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::sinic
 
 gem5::sinic::registers
 

Macros

#define __SINIC_REG32(NAME, VAL)   static const uint32_t NAME = (VAL);
 
#define __SINIC_REG64(NAME, VAL)   static const uint64_t NAME = (VAL);
 
#define __SINIC_VAL32(NAME, OFFSET, WIDTH)
 
#define __SINIC_VAL64(NAME, OFFSET, WIDTH)
 

Functions

 gem5::GEM5_DEPRECATED_NAMESPACE (Sinic, sinic)
 
 gem5::sinic::GEM5_DEPRECATED_NAMESPACE (Regs, registers)
 
 gem5::sinic::registers::__SINIC_REG32 (Config, 0x00) __SINIC_REG32(Command
 
 gem5::sinic::registers::__SINIC_REG32 (IntrStatus, 0x08) __SINIC_REG32(IntrMask
 
 gem5::sinic::registers::__SINIC_REG32 (RxMaxCopy, 0x10) __SINIC_REG32(TxMaxCopy
 
 gem5::sinic::registers::__SINIC_REG32 (ZeroCopySize, 0x18) __SINIC_REG32(ZeroCopyMark
 
 gem5::sinic::registers::__SINIC_REG32 (VirtualCount, 0x20) __SINIC_REG32(RxMaxIntr
 
 gem5::sinic::registers::__SINIC_REG32 (RxFifoSize, 0x28) __SINIC_REG32(TxFifoSize
 
 gem5::sinic::registers::__SINIC_REG32 (RxFifoLow, 0x30) __SINIC_REG32(TxFifoLow
 
 gem5::sinic::registers::__SINIC_REG32 (RxFifoHigh, 0x38) __SINIC_REG32(TxFifoHigh
 
 gem5::sinic::registers::__SINIC_REG32 (RxData, 0x40) __SINIC_REG32(RxDone
 
 gem5::sinic::registers::__SINIC_REG32 (RxWait, 0x50) __SINIC_REG32(TxData
 
 gem5::sinic::registers::__SINIC_REG32 (TxDone, 0x60) __SINIC_REG32(TxWait
 
 gem5::sinic::registers::__SINIC_REG32 (HwAddr, 0x70) __SINIC_REG32(Size
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_ZeroCopy, 12, 1) __SINIC_VAL32(Config_DelayCopy
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_RSS, 10, 1) __SINIC_VAL32(Config_RxThread
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_TxThread, 8, 1) __SINIC_VAL32(Config_Filter
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_Vlan, 6, 1) __SINIC_VAL32(Config_Vaddr
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_Desc, 4, 1) __SINIC_VAL32(Config_Poll
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_IntEn, 2, 1) __SINIC_VAL32(Config_TxEn
 
 gem5::sinic::registers::__SINIC_VAL32 (Config_RxEn, 0, 1) __SINIC_VAL32(Command_Intr
 
 gem5::sinic::registers::__SINIC_VAL32 (Command_Reset, 0, 1) __SINIC_VAL32(Intr_Soft
 
 gem5::sinic::registers::__SINIC_VAL32 (Intr_TxLow, 7, 1) __SINIC_VAL32(Intr_TxFull
 
 gem5::sinic::registers::__SINIC_VAL32 (Intr_TxDMA, 5, 1) __SINIC_VAL32(Intr_TxPacket
 
 gem5::sinic::registers::__SINIC_VAL32 (Intr_RxHigh, 3, 1) __SINIC_VAL32(Intr_RxEmpty
 
 gem5::sinic::registers::__SINIC_VAL32 (Intr_RxDMA, 1, 1) __SINIC_VAL32(Intr_RxPacket
 
 gem5::sinic::registers::__SINIC_REG32 (Intr_All, 0x01ff) __SINIC_REG32(Intr_NoDelay
 
 gem5::sinic::registers::__SINIC_REG32 (Intr_Res, ~0x01ff) __SINIC_VAL64(RxData_NoDelay
 
 gem5::sinic::registers::__SINIC_VAL64 (RxData_Vaddr, 60, 1) __SINIC_VAL64(RxData_Len
 
 gem5::sinic::registers::__SINIC_VAL64 (RxData_Addr, 0, 40) __SINIC_VAL64(TxData_More
 
 gem5::sinic::registers::__SINIC_VAL64 (TxData_Checksum, 62, 1) __SINIC_VAL64(TxData_Vaddr
 
 gem5::sinic::registers::__SINIC_VAL64 (TxData_Len, 40, 20) __SINIC_VAL64(TxData_Addr
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_Packets, 32, 16) __SINIC_VAL64(RxDone_Busy
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_Complete, 30, 1) __SINIC_VAL64(RxDone_More
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_Empty, 28, 1) __SINIC_VAL64(RxDone_High
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_NotHigh, 26, 1) __SINIC_VAL64(RxDone_TcpError
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_UdpError, 24, 1) __SINIC_VAL64(RxDone_IpError
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_TcpPacket, 22, 1) __SINIC_VAL64(RxDone_UdpPacket
 
 gem5::sinic::registers::__SINIC_VAL64 (RxDone_IpPacket, 20, 1) __SINIC_VAL64(RxDone_CopyLen
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Packets, 32, 16) __SINIC_VAL64(TxDone_Busy
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Complete, 30, 1) __SINIC_VAL64(TxDone_Full
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Low, 28, 1) __SINIC_VAL64(TxDone_Res0
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Res1, 26, 1) __SINIC_VAL64(TxDone_Res2
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Res3, 24, 1) __SINIC_VAL64(TxDone_Res4
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Res5, 22, 1) __SINIC_VAL64(TxDone_Res6
 
 gem5::sinic::registers::__SINIC_VAL64 (TxDone_Res7, 20, 1) __SINIC_VAL64(TxDone_CopyLen
 
const registers::Info & gem5::sinic::regInfo (Addr daddr)
 
bool gem5::sinic::regValid (Addr daddr)
 

Variables

static const int gem5::sinic::registers::VirtualShift = 8
 
static const int gem5::sinic::registers::VirtualMask = 0xff
 

Macro Definition Documentation

◆ __SINIC_REG32

#define __SINIC_REG32 (   NAME,
  VAL 
)    static const uint32_t NAME = (VAL);

Definition at line 36 of file sinicreg.hh.

◆ __SINIC_REG64

#define __SINIC_REG64 (   NAME,
  VAL 
)    static const uint64_t NAME = (VAL);

Definition at line 37 of file sinicreg.hh.

◆ __SINIC_VAL32

#define __SINIC_VAL32 (   NAME,
  OFFSET,
  WIDTH 
)
Value:
static const uint32_t NAME##_width = WIDTH; \
static const uint32_t NAME##_offset = OFFSET; \
static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
static inline uint32_t get_##NAME(uint32_t reg) \
{ return (reg & NAME) >> OFFSET; } \
static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }

Definition at line 39 of file sinicreg.hh.

◆ __SINIC_VAL64

#define __SINIC_VAL64 (   NAME,
  OFFSET,
  WIDTH 
)
Value:
static const uint64_t NAME##_width = WIDTH; \
static const uint64_t NAME##_offset = OFFSET; \
static const uint64_t NAME##_mask = (1ULL << WIDTH) - 1; \
static const uint64_t NAME = ((1ULL << WIDTH) - 1) << OFFSET; \
static inline uint64_t get_##NAME(uint64_t reg) \
{ return (reg & NAME) >> OFFSET; } \
static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
{ return (reg & ~NAME) | ((val << OFFSET) & NAME); }

Definition at line 49 of file sinicreg.hh.

gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
WIDTH
#define WIDTH
Definition: define.h:41
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92

Generated on Sat Jun 18 2022 08:12:49 for gem5 by doxygen 1.8.17