gem5 v24.0.0.0
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sinicreg.hh
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1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __DEV_NET_SINICREG_HH__
30#define __DEV_NET_SINICREG_HH__
31
32#include <cstdint>
33
34#include "base/compiler.hh"
35
36#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
37#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
38
39#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
40 static const uint32_t NAME##_width = WIDTH; \
41 static const uint32_t NAME##_offset = OFFSET; \
42 static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
43 static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
44 static inline uint32_t get_##NAME(uint32_t reg) \
45 { return (reg & NAME) >> OFFSET; } \
46 static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
47 { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
48
49#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
50 static const uint64_t NAME##_width = WIDTH; \
51 static const uint64_t NAME##_offset = OFFSET; \
52 static const uint64_t NAME##_mask = (1ULL << WIDTH) - 1; \
53 static const uint64_t NAME = ((1ULL << WIDTH) - 1) << OFFSET; \
54 static inline uint64_t get_##NAME(uint64_t reg) \
55 { return (reg & NAME) >> OFFSET; } \
56 static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
57 { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
58
59namespace gem5
60{
61
62namespace sinic
63{
64
65namespace registers
66{
67
68static const int VirtualShift = 8;
69static const int VirtualMask = 0xff;
70
71// Registers
72__SINIC_REG32(Config, 0x00) // 32: configuration register
73__SINIC_REG32(Command, 0x04) // 32: command register
74__SINIC_REG32(IntrStatus, 0x08) // 32: interrupt status
75__SINIC_REG32(IntrMask, 0x0c) // 32: interrupt mask
76__SINIC_REG32(RxMaxCopy, 0x10) // 32: max bytes per rx copy
77__SINIC_REG32(TxMaxCopy, 0x14) // 32: max bytes per tx copy
78__SINIC_REG32(ZeroCopySize, 0x18) // 32: bytes to copy if below threshold
79__SINIC_REG32(ZeroCopyMark, 0x1c) // 32: only zero-copy above this threshold
80__SINIC_REG32(VirtualCount, 0x20) // 32: number of virutal NICs
81__SINIC_REG32(RxMaxIntr, 0x24) // 32: max receives per interrupt
82__SINIC_REG32(RxFifoSize, 0x28) // 32: rx fifo capacity in bytes
83__SINIC_REG32(TxFifoSize, 0x2c) // 32: tx fifo capacity in bytes
84__SINIC_REG32(RxFifoLow, 0x30) // 32: rx fifo low watermark
85__SINIC_REG32(TxFifoLow, 0x34) // 32: tx fifo low watermark
86__SINIC_REG32(RxFifoHigh, 0x38) // 32: rx fifo high watermark
87__SINIC_REG32(TxFifoHigh, 0x3c) // 32: tx fifo high watermark
88__SINIC_REG32(RxData, 0x40) // 64: receive data
89__SINIC_REG32(RxDone, 0x48) // 64: receive done
90__SINIC_REG32(RxWait, 0x50) // 64: receive done (busy wait)
91__SINIC_REG32(TxData, 0x58) // 64: transmit data
92__SINIC_REG32(TxDone, 0x60) // 64: transmit done
93__SINIC_REG32(TxWait, 0x68) // 64: transmit done (busy wait)
94__SINIC_REG32(HwAddr, 0x70) // 64: mac address
95__SINIC_REG32(RxStatus, 0x78)
96__SINIC_REG32(Size, 0x80) // register addres space size
97
98// Config register bits
99__SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy
100__SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy
101__SINIC_VAL32(Config_RSS, 10, 1) // enable receive side scaling
102__SINIC_VAL32(Config_RxThread, 9, 1) // enable receive threads
103__SINIC_VAL32(Config_TxThread, 8, 1) // enable transmit thread
104__SINIC_VAL32(Config_Filter, 7, 1) // enable receive filter
105__SINIC_VAL32(Config_Vlan, 6, 1) // enable vlan tagging
106__SINIC_VAL32(Config_Vaddr, 5, 1) // enable virtual addressing
107__SINIC_VAL32(Config_Desc, 4, 1) // enable tx/rx descriptors
108__SINIC_VAL32(Config_Poll, 3, 1) // enable polling
109__SINIC_VAL32(Config_IntEn, 2, 1) // enable interrupts
110__SINIC_VAL32(Config_TxEn, 1, 1) // enable transmit
111__SINIC_VAL32(Config_RxEn, 0, 1) // enable receive
112
113// Command register bits
114__SINIC_VAL32(Command_Intr, 1, 1) // software interrupt
115__SINIC_VAL32(Command_Reset, 0, 1) // reset chip
116
117// Interrupt register bits
118__SINIC_VAL32(Intr_Soft, 8, 1) // software interrupt
119__SINIC_VAL32(Intr_TxLow, 7, 1) // tx fifo dropped below watermark
120__SINIC_VAL32(Intr_TxFull, 6, 1) // tx fifo full
121__SINIC_VAL32(Intr_TxDMA, 5, 1) // tx dma completed w/ interrupt
122__SINIC_VAL32(Intr_TxPacket, 4, 1) // packet transmitted
123__SINIC_VAL32(Intr_RxHigh, 3, 1) // rx fifo above high watermark
124__SINIC_VAL32(Intr_RxEmpty, 2, 1) // rx fifo empty
125__SINIC_VAL32(Intr_RxDMA, 1, 1) // rx dma completed w/ interrupt
126__SINIC_VAL32(Intr_RxPacket, 0, 1) // packet received
127__SINIC_REG32(Intr_All, 0x01ff) // all valid interrupts
128__SINIC_REG32(Intr_NoDelay, 0x01cc) // interrupts that aren't coalesced
129__SINIC_REG32(Intr_Res, ~0x01ff) // reserved interrupt bits
130
131// RX Data Description
132__SINIC_VAL64(RxData_NoDelay, 61, 1) // Don't Delay this copy
133__SINIC_VAL64(RxData_Vaddr, 60, 1) // Addr is virtual
134__SINIC_VAL64(RxData_Len, 40, 20) // 0 - 256k
135__SINIC_VAL64(RxData_Addr, 0, 40) // Address 1TB
136
137// TX Data Description
138__SINIC_VAL64(TxData_More, 63, 1) // Packet not complete (will dma more)
139__SINIC_VAL64(TxData_Checksum, 62, 1) // do checksum
140__SINIC_VAL64(TxData_Vaddr, 60, 1) // Addr is virtual
141__SINIC_VAL64(TxData_Len, 40, 20) // 0 - 256k
142__SINIC_VAL64(TxData_Addr, 0, 40) // Address 1TB
143
144// RX Done/Busy Information
145__SINIC_VAL64(RxDone_Packets, 32, 16) // number of packets in rx fifo
146__SINIC_VAL64(RxDone_Busy, 31, 1) // receive dma busy copying
147__SINIC_VAL64(RxDone_Complete, 30, 1) // valid data (packet complete)
148__SINIC_VAL64(RxDone_More, 29, 1) // Packet has more data (dma again)
149__SINIC_VAL64(RxDone_Empty, 28, 1) // rx fifo is empty
150__SINIC_VAL64(RxDone_High, 27, 1) // rx fifo is above the watermark
151__SINIC_VAL64(RxDone_NotHigh, 26, 1) // rxfifo never hit the high watermark
152__SINIC_VAL64(RxDone_TcpError, 25, 1) // TCP packet error (bad checksum)
153__SINIC_VAL64(RxDone_UdpError, 24, 1) // UDP packet error (bad checksum)
154__SINIC_VAL64(RxDone_IpError, 23, 1) // IP packet error (bad checksum)
155__SINIC_VAL64(RxDone_TcpPacket, 22, 1) // this is a TCP packet
156__SINIC_VAL64(RxDone_UdpPacket, 21, 1) // this is a UDP packet
157__SINIC_VAL64(RxDone_IpPacket, 20, 1) // this is an IP packet
158__SINIC_VAL64(RxDone_CopyLen, 0, 20) // up to 256k
159
160// TX Done/Busy Information
161__SINIC_VAL64(TxDone_Packets, 32, 16) // number of packets in tx fifo
162__SINIC_VAL64(TxDone_Busy, 31, 1) // transmit dma busy copying
163__SINIC_VAL64(TxDone_Complete, 30, 1) // valid data (packet complete)
164__SINIC_VAL64(TxDone_Full, 29, 1) // tx fifo is full
165__SINIC_VAL64(TxDone_Low, 28, 1) // tx fifo is below the watermark
166__SINIC_VAL64(TxDone_Res0, 27, 1) // reserved
167__SINIC_VAL64(TxDone_Res1, 26, 1) // reserved
168__SINIC_VAL64(TxDone_Res2, 25, 1) // reserved
169__SINIC_VAL64(TxDone_Res3, 24, 1) // reserved
170__SINIC_VAL64(TxDone_Res4, 23, 1) // reserved
171__SINIC_VAL64(TxDone_Res5, 22, 1) // reserved
172__SINIC_VAL64(TxDone_Res6, 21, 1) // reserved
173__SINIC_VAL64(TxDone_Res7, 20, 1) // reserved
174__SINIC_VAL64(TxDone_CopyLen, 0, 20) // up to 256k
175
176__SINIC_VAL64(RxStatus_Dirty, 48, 16)
177__SINIC_VAL64(RxStatus_Mapped, 32, 16)
178__SINIC_VAL64(RxStatus_Busy, 16, 16)
179__SINIC_VAL64(RxStatus_Head, 0, 16)
180
181struct Info
182{
183 uint8_t size;
184 bool read;
185 bool write;
186 const char *name;
187};
188
189} // namespace registers
190
191inline const registers::Info&
192regInfo(Addr daddr)
193{
194 static registers::Info invalid = { 0, false, false, "invalid" };
195 static registers::Info info [] = {
196 { 4, true, true, "Config" },
197 { 4, false, true, "Command" },
198 { 4, true, true, "IntrStatus" },
199 { 4, true, true, "IntrMask" },
200 { 4, true, false, "RxMaxCopy" },
201 { 4, true, false, "TxMaxCopy" },
202 { 4, true, false, "ZeroCopySize" },
203 { 4, true, false, "ZeroCopyMark" },
204 { 4, true, false, "VirtualCount" },
205 { 4, true, false, "RxMaxIntr" },
206 { 4, true, false, "RxFifoSize" },
207 { 4, true, false, "TxFifoSize" },
208 { 4, true, false, "RxFifoLow" },
209 { 4, true, false, "TxFifoLow" },
210 { 4, true, false, "RxFifoHigh" },
211 { 4, true, false, "TxFifoHigh" },
212 { 8, true, true, "RxData" },
213 invalid,
214 { 8, true, false, "RxDone" },
215 invalid,
216 { 8, true, false, "RxWait" },
217 invalid,
218 { 8, true, true, "TxData" },
219 invalid,
220 { 8, true, false, "TxDone" },
221 invalid,
222 { 8, true, false, "TxWait" },
223 invalid,
224 { 8, true, false, "HwAddr" },
225 invalid,
226 { 8, true, false, "RxStatus" },
227 invalid,
228 };
229
230 return info[daddr / 4];
231}
232
233inline bool
234regValid(Addr daddr)
235{
236 if (daddr > registers::Size)
237 return false;
238
239 if (regInfo(daddr).size == 0)
240 return false;
241
242 return true;
243}
244
245} // namespace sinic
246
247} // namespace gem5
248
249#endif // __DEV_NET_SINICREG_HH__
gem5::sinic::registers::VirtualMask
static const int VirtualMask
Definition sinicreg.hh:69
gem5::sinic::registers::VirtualShift
static const int VirtualShift
Definition sinicreg.hh:68
gem5::sinic::regInfo
const registers::Info & regInfo(Addr daddr)
Definition sinicreg.hh:192
gem5::sinic::regValid
bool regValid(Addr daddr)
Definition sinicreg.hh:234
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
__SINIC_VAL32
#define __SINIC_VAL32(NAME, OFFSET, WIDTH)
Definition sinicreg.hh:39
__SINIC_REG32
#define __SINIC_REG32(NAME, VAL)
Definition sinicreg.hh:36
__SINIC_VAL64
#define __SINIC_VAL64(NAME, OFFSET, WIDTH)
Definition sinicreg.hh:49
Generated on Tue Jun 18 2024 16:24:03 for gem5 by doxygen 1.11.0