gem5  v21.1.0.2
branch.hh
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28 
29 #ifndef __ARCH_SPARC_INSTS_BRANCH_HH__
30 #define __ARCH_SPARC_INSTS_BRANCH_HH__
31 
33 
34 namespace gem5
35 {
36 
38 //
39 // Branch instructions
40 //
41 
42 namespace SparcISA
43 {
44 
48 class Branch : public SparcStaticInst
49 {
50  protected:
52 
53  std::string generateDisassembly(
54  Addr pc, const loader::SymbolTable *symtab) const override;
55 };
56 
60 class BranchDisp : public Branch
61 {
62  protected:
63  BranchDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
64  int32_t _disp) :
65  Branch(mnem, _machInst, __opClass), disp(_disp)
66  {}
67 
68  std::string generateDisassembly(
69  Addr pc, const loader::SymbolTable *symtab) const override;
70 
71  int32_t disp;
72 };
73 
77 template<int bits>
78 class BranchNBits : public BranchDisp
79 {
80  protected:
81  // Constructor
82  BranchNBits(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
83  BranchDisp(mnem, _machInst, __opClass, szext<bits>(_machInst) << 2)
84  {}
85 };
86 
90 class BranchSplit : public BranchDisp
91 {
92  protected:
93  // Constructor
94  BranchSplit(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
95  BranchDisp(mnem, _machInst, __opClass,
96  sext<18>((bits(_machInst, 21, 20) << 16) |
97  (bits(_machInst, 13, 0) << 2)))
98  {}
99 };
100 
105 class BranchImm13 : public Branch
106 {
107  protected:
108  // Constructor
109  BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
110  Branch(mnem, _machInst, __opClass), imm(szext<13>(_machInst))
111  {}
112 
113  std::string generateDisassembly(
114  Addr pc, const loader::SymbolTable *symtab) const override;
115 
116  int32_t imm;
117 };
118 
119 } // namespace SparcISA
120 } // namespace gem5
121 
122 #endif // __ARCH_SPARC_INSTS_BRANCH_HH__
gem5::SparcISA::SparcStaticInst
Base class for all SPARC static instructions.
Definition: static_inst.hh:91
gem5::SparcISA::Branch::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:47
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:42
gem5::SparcISA::BranchNBits
Base class for branches with n bit displacements.
Definition: branch.hh:78
gem5::SparcISA::BranchImm13
Base class for branches that use an immediate and a register to compute their displacements.
Definition: branch.hh:105
gem5::SparcISA::BranchDisp
Base class for branch operations with an immediate displacement.
Definition: branch.hh:60
gem5::sext
constexpr uint64_t sext(uint64_t val)
Sign-extend an N-bit value to 64 bits.
Definition: bitfield.hh:126
gem5::SparcISA::BranchNBits::BranchNBits
BranchNBits(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch.hh:82
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::SparcISA::BranchImm13::imm
int32_t imm
Definition: branch.hh:116
gem5::SparcISA::BranchSplit::BranchSplit
BranchSplit(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch.hh:94
gem5::SparcISA::BranchImm13::BranchImm13
BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: branch.hh:109
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::szext
constexpr uint64_t szext(uint64_t val)
Sign-extend an N-bit value to 64 bits.
Definition: bitfield.hh:142
gem5::SparcISA::BranchDisp::BranchDisp
BranchDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _disp)
Definition: branch.hh:63
gem5::SparcISA::BranchSplit
Base class for 16bit split displacements.
Definition: branch.hh:90
gem5::SparcISA::BranchDisp::disp
int32_t disp
Definition: branch.hh:71
gem5::SparcISA::SparcStaticInst::SparcStaticInst
SparcStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:96
gem5::SparcISA::Branch
Base class for branch operations.
Definition: branch.hh:48
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::BranchImm13::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:61
gem5::SparcISA::BranchDisp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:79
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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