gem5  v21.2.1.1
static_inst.hh
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29 
30 #ifndef __ARCH_SPARC_INSTS_STATIC_INST_HH__
31 #define __ARCH_SPARC_INSTS_STATIC_INST_HH__
32 
33 #include <cstdint>
34 
35 #include "arch/sparc/pcstate.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/trace.hh"
38 #include "cpu/exec_context.hh"
39 #include "cpu/static_inst.hh"
40 #include "cpu/thread_context.hh"
41 
42 namespace gem5
43 {
44 
45 namespace SparcISA
46 {
47 
49 {
50  Always=0x8,
51  Never=0x0,
52  NotEqual=0x9,
53  Equal=0x1,
54  Greater=0xA,
57  Less=0x3,
61  CarrySet=0x5,
62  Positive=0xE,
63  Negative=0x6,
66 };
67 
68 extern const char *CondTestAbbrev[];
69 
71 {
72  FAlways=0x8,
73  FNever=0x0,
75  FGreater=0x6,
77  FLess=0x4,
80  FNotEqual=0x1,
81  FEqual=0x9,
88 };
89 
94 {
95  protected:
97 
98  SparcStaticInst(const char *_mnemonic, ExtMachInst _machInst,
99  OpClass __opClass) :
100  StaticInst(_mnemonic, __opClass), machInst(_machInst)
101  {}
102 
103  std::string generateDisassembly(
104  Addr pc, const loader::SymbolTable *symtab) const override;
105 
106  static void printMnemonic(std::ostream &os, const char *mnemonic);
107  static void printReg(std::ostream &os, RegId reg);
108 
109  void printSrcReg(std::ostream &os, int reg) const;
110  void printDestReg(std::ostream &os, int reg) const;
111 
112  void printRegArray(std::ostream &os,
113  const RegId *indexArray, int num) const;
114 
115  void advancePC(PCStateBase &pcState) const override;
116  void advancePC(ThreadContext *tc) const override;
117 
118  static bool passesFpCondition(uint32_t fcc, uint32_t condition);
119  static bool passesCondition(uint32_t codes, uint32_t condition);
120 
121  size_t
122  asBytes(void *buf, size_t size) override
123  {
124  return simpleAsBytes(buf, size, machInst);
125  }
126 
127  std::unique_ptr<PCStateBase>
128  buildRetPC(const PCStateBase &cur_pc,
129  const PCStateBase &call_pc) const override
130  {
131  PCStateBase *ret_ptr = call_pc.clone();
132  auto &ret = ret_ptr->as<PCState>();
133  ret.uEnd();
134  ret.pc(cur_pc.as<PCState>().npc());
135  return std::unique_ptr<PCStateBase>{ret_ptr};
136  }
137 };
138 
139 } // namespace SparcISA
140 } // namespace gem5
141 
142 #endif //__ARCH_SPARC_INSTS_STATIC_INST_HH__
gem5::SparcISA::FGreaterOrEqual
@ FGreaterOrEqual
Definition: static_inst.hh:83
gem5::SparcISA::OverflowSet
@ OverflowSet
Definition: static_inst.hh:65
gem5::SparcISA::FUnorderedOrGreater
@ FUnorderedOrGreater
Definition: static_inst.hh:76
gem5::SparcISA::Less
@ Less
Definition: static_inst.hh:57
gem5::SparcISA::SparcStaticInst
Base class for all SPARC static instructions.
Definition: static_inst.hh:93
gem5::SparcISA::FUnorderedOrLessOrEqual
@ FUnorderedOrLessOrEqual
Definition: static_inst.hh:86
gem5::SparcISA::Never
@ Never
Definition: static_inst.hh:51
gem5::SparcISA::FUnorderedOrLess
@ FUnorderedOrLess
Definition: static_inst.hh:78
gem5::SparcISA::CarryClear
@ CarryClear
Definition: static_inst.hh:60
gem5::SparcISA::FAlways
@ FAlways
Definition: static_inst.hh:72
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:42
pcstate.hh
gem5::SparcISA::SparcStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:265
gem5::SparcISA::CarrySet
@ CarrySet
Definition: static_inst.hh:61
gem5::SparcISA::NotEqual
@ NotEqual
Definition: static_inst.hh:52
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::SparcISA::SparcStaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg) const
Definition: static_inst.cc:97
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:377
gem5::SparcISA::Equal
@ Equal
Definition: static_inst.hh:53
gem5::SparcISA::FLess
@ FLess
Definition: static_inst.hh:77
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::SparcISA::FUnorderedOrEqual
@ FUnorderedOrEqual
Definition: static_inst.hh:82
gem5::SparcISA::OverflowClear
@ OverflowClear
Definition: static_inst.hh:64
gem5::SparcISA::SparcStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:96
gem5::SparcISA::SparcStaticInst::printRegArray
void printRegArray(std::ostream &os, const RegId *indexArray, int num) const
Definition: static_inst.cc:70
gem5::SparcISA::FpCondTest
FpCondTest
Definition: static_inst.hh:70
gem5::SparcISA::LessOrEqual
@ LessOrEqual
Definition: static_inst.hh:55
gem5::SparcISA::LessOrEqualUnsigned
@ LessOrEqualUnsigned
Definition: static_inst.hh:59
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
gem5::SparcISA::GreaterUnsigned
@ GreaterUnsigned
Definition: static_inst.hh:58
gem5::SparcISA::SparcStaticInst::buildRetPC
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
Definition: static_inst.hh:128
gem5::SparcISA::SparcStaticInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.cc:83
gem5::SparcISA::SparcStaticInst::printDestReg
void printDestReg(std::ostream &os, int reg) const
Definition: static_inst.cc:104
gem5::SparcISA::FGreater
@ FGreater
Definition: static_inst.hh:75
gem5::SparcISA::GreaterOrEqual
@ GreaterOrEqual
Definition: static_inst.hh:56
static_inst.hh
gem5::SparcISA::FLessOrGreater
@ FLessOrGreater
Definition: static_inst.hh:79
types.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::FOrdered
@ FOrdered
Definition: static_inst.hh:87
gem5::SparcISA::FNotEqual
@ FNotEqual
Definition: static_inst.hh:80
gem5::SparcISA::SparcStaticInst::printReg
static void printReg(std::ostream &os, RegId reg)
Definition: static_inst.cc:111
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SparcISA::CondTestAbbrev
const char * CondTestAbbrev[]
Definition: static_inst.cc:43
gem5::SparcISA::SparcStaticInst::SparcStaticInst
SparcStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:98
gem5::SparcISA::FUnorderedOrGreaterOrEqual
@ FUnorderedOrGreaterOrEqual
Definition: static_inst.hh:84
gem5::SparcISA::FUnordered
@ FUnordered
Definition: static_inst.hh:74
gem5::SparcISA::FEqual
@ FEqual
Definition: static_inst.hh:81
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::SparcISA::SparcStaticInst::passesCondition
static bool passesCondition(uint32_t codes, uint32_t condition)
Definition: static_inst.cc:339
gem5::SparcISA::Greater
@ Greater
Definition: static_inst.hh:54
gem5::GenericISA::DelaySlotUPCState
Definition: pcstate.hh:530
exec_context.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::FLessOrEqual
@ FLessOrEqual
Definition: static_inst.hh:85
gem5::SparcISA::SparcStaticInst::asBytes
size_t asBytes(void *buf, size_t size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:122
gem5::SparcISA::Positive
@ Positive
Definition: static_inst.hh:62
trace.hh
gem5::SparcISA::SparcStaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:64
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::SparcISA::FNever
@ FNever
Definition: static_inst.hh:73
gem5::SparcISA::Negative
@ Negative
Definition: static_inst.hh:63
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::SparcISA::Always
@ Always
Definition: static_inst.hh:50
thread_context.hh
gem5::SparcISA::SparcStaticInst::passesFpCondition
static bool passesFpCondition(uint32_t fcc, uint32_t condition)
Definition: static_inst.cc:294
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::SparcISA::CondTest
CondTest
Definition: static_inst.hh:48
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::GenericISA::DelaySlotUPCState::uEnd
void uEnd()
Definition: pcstate.hh:578

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