gem5 v24.0.0.0
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static_inst.hh
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1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 * Copyright 2017 Google Inc.
5 *
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15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 */
29
30#ifndef __ARCH_SPARC_INSTS_STATIC_INST_HH__
31#define __ARCH_SPARC_INSTS_STATIC_INST_HH__
32
33#include <cstdint>
34
35#include "arch/sparc/pcstate.hh"
36#include "arch/sparc/types.hh"
37#include "base/trace.hh"
38#include "cpu/exec_context.hh"
39#include "cpu/static_inst.hh"
40#include "cpu/thread_context.hh"
41
42namespace gem5
43{
44
45namespace SparcISA
46{
47
67
68extern const char *CondTestAbbrev[];
69
89
94{
95 protected:
97
98 SparcStaticInst(const char *_mnemonic, ExtMachInst _machInst,
99 OpClass __opClass) :
100 StaticInst(_mnemonic, __opClass), machInst(_machInst)
101 {}
102
103 std::string generateDisassembly(
104 Addr pc, const loader::SymbolTable *symtab) const override;
105
106 static void printMnemonic(std::ostream &os, const char *mnemonic);
107 static void printReg(std::ostream &os, RegId reg);
108
109 void printSrcReg(std::ostream &os, int reg) const;
110 void printDestReg(std::ostream &os, int reg) const;
111
112 void printRegArray(std::ostream &os,
113 const RegId *indexArray, int num) const;
114
115 void advancePC(PCStateBase &pcState) const override;
116 void advancePC(ThreadContext *tc) const override;
117
118 static bool passesFpCondition(uint32_t fcc, uint32_t condition);
119 static bool passesCondition(uint32_t codes, uint32_t condition);
120
121 size_t
122 asBytes(void *buf, size_t size) override
123 {
124 return simpleAsBytes(buf, size, machInst);
125 }
126
127 std::unique_ptr<PCStateBase>
128 buildRetPC(const PCStateBase &cur_pc,
129 const PCStateBase &call_pc) const override
130 {
131 PCStateBase *ret_ptr = call_pc.clone();
132 auto &ret = ret_ptr->as<PCState>();
133 ret.uEnd();
134 ret.pc(cur_pc.as<PCState>().npc());
135 return std::unique_ptr<PCStateBase>{ret_ptr};
136 }
137};
138
139} // namespace SparcISA
140} // namespace gem5
141
142#endif //__ARCH_SPARC_INSTS_STATIC_INST_HH__
Target & as()
Definition pcstate.hh:73
virtual PCStateBase * clone() const =0
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
Base class for all SPARC static instructions.
void printRegArray(std::ostream &os, const RegId *indexArray, int num) const
static bool passesCondition(uint32_t codes, uint32_t condition)
SparcStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
static void printReg(std::ostream &os, RegId reg)
static void printMnemonic(std::ostream &os, const char *mnemonic)
void advancePC(PCStateBase &pcState) const override
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
void printDestReg(std::ostream &os, int reg) const
static bool passesFpCondition(uint32_t fcc, uint32_t condition)
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
size_t asBytes(void *buf, size_t size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
void printSrcReg(std::ostream &os, int reg) const
Base, ISA-independent static instruction class.
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
size_t size() const
const char * mnemonic
Base mnemonic (e.g., "add").
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Bitfield< 4 > pc
uint64_t ExtMachInst
Definition types.hh:42
const char * CondTestAbbrev[]
Bitfield< 5, 3 > reg
Definition types.hh:92
Bitfield< 17 > os
Definition misc.hh:838
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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