gem5  v22.0.0.1
store_set.hh
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28 
29 #ifndef __CPU_O3_STORE_SET_HH__
30 #define __CPU_O3_STORE_SET_HH__
31 
32 #include <list>
33 #include <map>
34 #include <utility>
35 #include <vector>
36 
37 #include "base/types.hh"
38 #include "cpu/inst_seq.hh"
39 
40 namespace gem5
41 {
42 
43 namespace o3
44 {
45 
46 struct ltseqnum
47 {
48  bool
49  operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
50  {
51  return lhs > rhs;
52  }
53 };
54 
62 class StoreSet
63 {
64  public:
65  typedef unsigned SSID;
66 
67  public:
69  StoreSet() { };
70 
72  StoreSet(uint64_t clear_period, int SSIT_size, int LFST_size);
73 
75  ~StoreSet();
76 
78  void init(uint64_t clear_period, int SSIT_size, int LFST_size);
79 
82  void violation(Addr store_PC, Addr load_PC);
83 
88  void checkClear();
89 
93  void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
94 
97  void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid);
98 
104 
106  void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
107 
109  void squash(InstSeqNum squashed_num, ThreadID tid);
110 
112  void clear();
113 
115  void dump();
116 
117  private:
119  inline int calcIndex(Addr PC)
120  { return (PC >> offsetBits) & indexMask; }
121 
123  inline SSID calcSSID(Addr PC)
124  { return ((PC ^ (PC >> 10)) % LFSTSize); }
125 
128 
131 
134 
137 
141  std::map<InstSeqNum, int, ltseqnum> storeList;
142 
143  typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
144 
148  uint64_t clearPeriod;
149 
151  int SSITSize;
152 
154  int LFSTSize;
155 
158 
159  // HACK: Hardcoded for now.
161 
164 };
165 
166 } // namespace o3
167 } // namespace gem5
168 
169 #endif // __CPU_O3_STORE_SET_HH__
gem5::o3::StoreSet::SSITSize
int SSITSize
Store Set ID Table size, in entries.
Definition: store_set.hh:151
gem5::o3::StoreSet::offsetBits
int offsetBits
Definition: store_set.hh:160
gem5::o3::StoreSet::issued
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
Records this PC/sequence number as issued.
Definition: store_set.cc:278
gem5::o3::StoreSet::validSSIT
std::vector< bool > validSSIT
Bit vector to tell if the SSIT has a valid entry.
Definition: store_set.hh:130
gem5::o3::StoreSet::init
void init(uint64_t clear_period, int SSIT_size, int LFST_size)
Initializes the store set predictor with the given table sizes.
Definition: store_set.cc:85
gem5::o3::StoreSet::indexMask
int indexMask
Mask to obtain the index.
Definition: store_set.hh:157
gem5::o3::StoreSet::~StoreSet
~StoreSet()
Default destructor.
Definition: store_set.cc:80
gem5::o3::StoreSet::insertStore
void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
Inserts a store into the store set predictor.
Definition: store_set.cc:213
gem5::o3::StoreSet::LFST
std::vector< InstSeqNum > LFST
Last Fetched Store Table.
Definition: store_set.hh:133
gem5::o3::StoreSet::calcIndex
int calcIndex(Addr PC)
Calculates the index into the SSIT based on the PC.
Definition: store_set.hh:119
gem5::o3::StoreSet::memOpsPred
int memOpsPred
Number of memory operations predicted since last clear of predictor.
Definition: store_set.hh:163
gem5::o3::StoreSet::clearPeriod
uint64_t clearPeriod
Number of loads/stores to process before wiping predictor so all entries don't get saturated.
Definition: store_set.hh:148
std::vector< SSID >
gem5::o3::StoreSet::SSIT
std::vector< SSID > SSIT
The Store Set ID Table.
Definition: store_set.hh:127
gem5::o3::StoreSet::SSID
unsigned SSID
Definition: store_set.hh:65
gem5::o3::StoreSet::insertLoad
void insertLoad(Addr load_PC, InstSeqNum load_seq_num)
Inserts a load into the store set predictor.
Definition: store_set.cc:205
gem5::o3::StoreSet
Implements a store set predictor for determining if memory instructions are dependent upon each other...
Definition: store_set.hh:62
gem5::o3::StoreSet::validLFST
std::vector< bool > validLFST
Bit vector to tell if the LFST has a valid entry.
Definition: store_set.hh:136
gem5::o3::StoreSet::checkClear
void checkClear()
Clears the store set predictor every so often so that all the entries aren't used and stores are cons...
Definition: store_set.cc:193
inst_seq.hh
gem5::o3::StoreSet::StoreSet
StoreSet()
Default constructor.
Definition: store_set.hh:69
gem5::o3::StoreSet::LFSTSize
int LFSTSize
Last Fetched Store Table size, in entries.
Definition: store_set.hh:154
gem5::o3::StoreSet::dump
void dump()
Debug function to dump the contents of the store list.
Definition: store_set.cc:359
gem5::o3::StoreSet::clear
void clear()
Resets all tables.
Definition: store_set.cc:345
gem5::o3::StoreSet::calcSSID
SSID calcSSID(Addr PC)
Calculates a Store Set ID based on the PC.
Definition: store_set.hh:123
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::StoreSet::SeqNumMapIt
std::map< InstSeqNum, int, ltseqnum >::iterator SeqNumMapIt
Definition: store_set.hh:143
gem5::o3::StoreSet::violation
void violation(Addr store_PC, Addr load_PC)
Records a memory ordering violation between the younger load and the older store.
Definition: store_set.cc:120
gem5::o3::ltseqnum
Definition: store_set.hh:46
types.hh
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::StoreSet::checkInst
InstSeqNum checkInst(Addr PC)
Checks if the instruction with the given PC is dependent upon any store.
Definition: store_set.cc:243
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::StoreSet::squash
void squash(InstSeqNum squashed_num, ThreadID tid)
Squashes for a specific thread until the given sequence number.
Definition: store_set.cc:315
gem5::o3::StoreSet::storeList
std::map< InstSeqNum, int, ltseqnum > storeList
Map of stores that have been inserted into the store set, but not yet issued or squashed.
Definition: store_set.hh:141
gem5::o3::ltseqnum::operator()
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
Definition: store_set.hh:49
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235

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